4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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17 * * Neither the name of Intel Corporation nor the names of its
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19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
41 #include <rte_common.h>
42 #include <rte_interrupts.h>
43 #include <rte_byteorder.h>
45 #include <rte_debug.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_memory.h>
50 #include <rte_memzone.h>
51 #include <rte_tailq.h>
53 #include <rte_atomic.h>
54 #include <rte_malloc.h>
56 #include "e1000_logs.h"
57 #include "igb/e1000_api.h"
58 #include "igb/e1000_hw.h"
59 #include "e1000_ethdev.h"
61 static int eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
63 static int eth_igb_start(struct rte_eth_dev *dev);
64 static void eth_igb_stop(struct rte_eth_dev *dev);
65 static void eth_igb_close(struct rte_eth_dev *dev);
66 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
67 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
68 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
69 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
70 static int eth_igb_link_update(struct rte_eth_dev *dev,
71 int wait_to_complete);
72 static void eth_igb_stats_get(struct rte_eth_dev *dev,
73 struct rte_eth_stats *rte_stats);
74 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
75 static void eth_igb_infos_get(struct rte_eth_dev *dev,
76 struct rte_eth_dev_info *dev_info);
77 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
78 struct rte_eth_fc_conf *fc_conf);
79 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
80 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
81 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
82 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
84 static int igb_hardware_init(struct e1000_hw *hw);
85 static void igb_hw_control_acquire(struct e1000_hw *hw);
86 static void igb_hw_control_release(struct e1000_hw *hw);
87 static void igb_init_manageability(struct e1000_hw *hw);
88 static void igb_release_manageability(struct e1000_hw *hw);
89 static void igb_vlan_hw_support_enable(struct rte_eth_dev *dev);
90 static void igb_vlan_hw_support_disable(struct rte_eth_dev *dev);
91 static void eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
94 static int eth_igb_led_on(struct rte_eth_dev *dev);
95 static int eth_igb_led_off(struct rte_eth_dev *dev);
97 static void igb_intr_disable(struct e1000_hw *hw);
98 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
99 static void eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
100 uint32_t index, uint32_t pool);
101 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
103 #define IGB_FC_PAUSE_TIME 0x0680
104 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
105 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
107 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
110 * The set of PCI devices this driver supports
112 static struct rte_pci_id pci_id_igb_map[] = {
114 #undef RTE_LIBRTE_IXGBE_PMD
115 #define RTE_PCI_DEV_ID_DECL(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
116 #include "rte_pci_dev_ids.h"
121 static struct eth_dev_ops eth_igb_ops = {
122 .dev_configure = eth_igb_configure,
123 .dev_start = eth_igb_start,
124 .dev_stop = eth_igb_stop,
125 .dev_close = eth_igb_close,
126 .promiscuous_enable = eth_igb_promiscuous_enable,
127 .promiscuous_disable = eth_igb_promiscuous_disable,
128 .allmulticast_enable = eth_igb_allmulticast_enable,
129 .allmulticast_disable = eth_igb_allmulticast_disable,
130 .link_update = eth_igb_link_update,
131 .stats_get = eth_igb_stats_get,
132 .stats_reset = eth_igb_stats_reset,
133 .dev_infos_get = eth_igb_infos_get,
134 .vlan_filter_set = eth_igb_vlan_filter_set,
135 .rx_queue_setup = eth_igb_rx_queue_setup,
136 .tx_queue_setup = eth_igb_tx_queue_setup,
137 .dev_led_on = eth_igb_led_on,
138 .dev_led_off = eth_igb_led_off,
139 .flow_ctrl_set = eth_igb_flow_ctrl_set,
140 .mac_addr_add = eth_igb_rar_set,
141 .mac_addr_remove = eth_igb_rar_clear,
145 * Atomically reads the link status information from global
146 * structure rte_eth_dev.
149 * - Pointer to the structure rte_eth_dev to read from.
150 * - Pointer to the buffer to be saved with the link status.
153 * - On success, zero.
154 * - On failure, negative value.
157 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
158 struct rte_eth_link *link)
160 struct rte_eth_link *dst = link;
161 struct rte_eth_link *src = &(dev->data->dev_link);
163 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
164 *(uint64_t *)src) == 0)
171 * Atomically writes the link status information into global
172 * structure rte_eth_dev.
175 * - Pointer to the structure rte_eth_dev to read from.
176 * - Pointer to the buffer to be saved with the link status.
179 * - On success, zero.
180 * - On failure, negative value.
183 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
184 struct rte_eth_link *link)
186 struct rte_eth_link *dst = &(dev->data->dev_link);
187 struct rte_eth_link *src = link;
189 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
190 *(uint64_t *)src) == 0)
197 igb_identify_hardware(struct rte_eth_dev *dev)
199 struct e1000_hw *hw =
200 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
202 hw->vendor_id = dev->pci_dev->id.vendor_id;
203 hw->device_id = dev->pci_dev->id.device_id;
204 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
205 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
207 e1000_set_mac_type(hw);
209 /* need to check if it is a vf device below */
213 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
214 struct rte_eth_dev *eth_dev)
217 struct rte_pci_device *pci_dev;
218 struct e1000_hw *hw =
219 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
220 struct e1000_vfta * shadow_vfta =
221 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
223 pci_dev = eth_dev->pci_dev;
224 eth_dev->dev_ops = ð_igb_ops;
225 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
226 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
228 /* for secondary processes, we don't initialise any further as primary
229 * has already done this work. Only check we don't need a different
231 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
232 if (eth_dev->data->scattered_rx)
233 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
237 hw->hw_addr= (void *)pci_dev->mem_resource.addr;
239 igb_identify_hardware(eth_dev);
241 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
246 e1000_get_bus_info(hw);
249 hw->phy.autoneg_wait_to_complete = 0;
250 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
253 if (hw->phy.media_type == e1000_media_type_copper) {
254 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
255 hw->phy.disable_polarity_correction = 0;
256 hw->phy.ms_type = e1000_ms_hw_default;
260 * Start from a known state, this is important in reading the nvm
265 /* Make sure we have a good EEPROM before we read from it */
266 if (e1000_validate_nvm_checksum(hw) < 0) {
268 * Some PCI-E parts fail the first check due to
269 * the link being in sleep state, call it again,
270 * if it fails a second time its a real issue.
272 if (e1000_validate_nvm_checksum(hw) < 0) {
273 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
279 /* Read the permanent MAC address out of the EEPROM */
280 if (e1000_read_mac_addr(hw) != 0) {
281 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
286 /* Allocate memory for storing MAC addresses */
287 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
288 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
289 if (eth_dev->data->mac_addrs == NULL) {
290 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
291 "store MAC addresses",
292 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
297 /* Copy the permanent MAC address */
298 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
300 /* initialize the vfta */
301 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
303 /* Now initialize the hardware */
304 if (igb_hardware_init(hw) != 0) {
305 PMD_INIT_LOG(ERR, "Hardware initialization failed");
306 rte_free(eth_dev->data->mac_addrs);
307 eth_dev->data->mac_addrs = NULL;
311 hw->mac.get_link_status = 1;
313 /* Indicate SOL/IDER usage */
314 if (e1000_check_reset_block(hw) < 0) {
315 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
319 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
320 eth_dev->data->port_id, pci_dev->id.vendor_id,
321 pci_dev->id.device_id);
323 rte_intr_callback_register(&(pci_dev->intr_handle),
324 eth_igb_interrupt_handler, (void *)eth_dev);
329 igb_hw_control_release(hw);
334 static struct eth_driver rte_igb_pmd = {
336 .name = "rte_igb_pmd",
337 .id_table = pci_id_igb_map,
338 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
340 .eth_dev_init = eth_igb_dev_init,
341 .dev_private_size = sizeof(struct e1000_adapter),
345 rte_igb_pmd_init(void)
347 rte_eth_driver_register(&rte_igb_pmd);
352 eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q)
354 struct e1000_interrupt *intr =
355 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
358 PMD_INIT_LOG(DEBUG, ">>");
360 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
362 /* Allocate the array of pointers to RX structures */
363 diag = igb_dev_rx_queue_alloc(dev, nb_rx_q);
365 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
366 " pointers to RX queues failed",
367 dev->data->port_id, nb_rx_q);
371 /* Allocate the array of pointers to TX structures */
372 diag = igb_dev_tx_queue_alloc(dev, nb_tx_q);
374 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
375 " pointers to TX queues failed",
376 dev->data->port_id, nb_tx_q);
381 PMD_INIT_LOG(DEBUG, "<<");
387 eth_igb_start(struct rte_eth_dev *dev)
389 struct e1000_hw *hw =
390 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
393 PMD_INIT_LOG(DEBUG, ">>");
395 igb_intr_disable(hw);
397 /* Power up the phy. Needed to make the link go Up */
398 e1000_power_up_phy(hw);
401 * Packet Buffer Allocation (PBA)
402 * Writing PBA sets the receive portion of the buffer
403 * the remainder is used for the transmit buffer.
405 if (hw->mac.type == e1000_82575) {
408 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
409 E1000_WRITE_REG(hw, E1000_PBA, pba);
412 /* Put the address into the Receive Address Array */
413 e1000_rar_set(hw, hw->mac.addr, 0);
415 /* Initialize the hardware */
416 if (igb_hardware_init(hw)) {
417 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
421 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
423 /* Configure for OS presence */
424 igb_init_manageability(hw);
426 eth_igb_tx_init(dev);
428 /* This can fail when allocating mbufs for descriptor rings */
429 ret = eth_igb_rx_init(dev);
431 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
435 e1000_clear_hw_cntrs_base_generic(hw);
438 * If VLAN filtering is enabled, set up VLAN tag offload and filtering
439 * and restore the VFTA.
441 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
442 igb_vlan_hw_support_enable(dev);
444 igb_vlan_hw_support_disable(dev);
447 * Configure the Interrupt Moderation register (EITR) with the maximum
448 * possible value (0xFFFF) to minimize "System Partial Write" issued by
449 * spurious [DMA] memory updates of RX and TX ring descriptors.
451 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
452 * spurious memory updates per second should be expected.
453 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
455 * Because interrupts are not used at all, the MSI-X is not activated
456 * and interrupt moderation is controlled by EITR[0].
458 * Note that having [almost] disabled memory updates of RX and TX ring
459 * descriptors through the Interrupt Moderation mechanism, memory
460 * updates of ring descriptors are now moderated by the configurable
461 * value of Write-Back Threshold registers.
463 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
464 (hw->mac.type == e1000_i350)) {
467 /* Enable all RX & TX queues in the IVAR registers */
468 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
469 for (i = 0; i < 8; i++)
470 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
472 /* Configure EITR with the maximum possible value (0xFFFF) */
473 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
476 /* Don't reset the phy next time init gets called */
477 hw->phy.reset_disable = 1;
479 /* Setup link speed and duplex */
480 switch (dev->data->dev_conf.link_speed) {
481 case ETH_LINK_SPEED_AUTONEG:
482 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
483 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
484 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
485 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
486 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
487 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
489 goto error_invalid_config;
491 case ETH_LINK_SPEED_10:
492 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
493 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
494 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
495 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
496 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
497 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
499 goto error_invalid_config;
501 case ETH_LINK_SPEED_100:
502 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
503 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
504 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
505 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
506 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
507 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
509 goto error_invalid_config;
511 case ETH_LINK_SPEED_1000:
512 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
513 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
514 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
516 goto error_invalid_config;
518 case ETH_LINK_SPEED_10000:
520 goto error_invalid_config;
522 e1000_setup_link(hw);
524 PMD_INIT_LOG(DEBUG, "<<");
526 /* check if lsc interrupt feature is enabled */
527 if (dev->data->dev_conf.intr_conf.lsc != 0)
528 return eth_igb_interrupt_setup(dev);
532 error_invalid_config:
533 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
534 dev->data->dev_conf.link_speed,
535 dev->data->dev_conf.link_duplex, dev->data->port_id);
539 /*********************************************************************
541 * This routine disables all traffic on the adapter by issuing a
542 * global reset on the MAC.
544 **********************************************************************/
546 eth_igb_stop(struct rte_eth_dev *dev)
548 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
549 struct rte_eth_link link;
551 igb_intr_disable(hw);
553 E1000_WRITE_REG(hw, E1000_WUC, 0);
555 /* Power down the phy. Needed to make the link go Down */
556 e1000_power_down_phy(hw);
558 igb_dev_clear_queues(dev);
560 /* clear the recorded link status */
561 memset(&link, 0, sizeof(link));
562 rte_igb_dev_atomic_write_link_status(dev, &link);
566 eth_igb_close(struct rte_eth_dev *dev)
568 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
569 struct rte_eth_link link;
572 e1000_phy_hw_reset(hw);
573 igb_release_manageability(hw);
574 igb_hw_control_release(hw);
576 igb_dev_clear_queues(dev);
578 memset(&link, 0, sizeof(link));
579 rte_igb_dev_atomic_write_link_status(dev, &link);
583 igb_get_rx_buffer_size(struct e1000_hw *hw)
585 uint32_t rx_buf_size;
586 if (hw->mac.type == e1000_82576) {
587 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
588 } else if (hw->mac.type == e1000_82580) {
589 /* PBS needs to be translated according to a lookup table */
590 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
591 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
592 rx_buf_size = (rx_buf_size << 10);
594 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
600 /*********************************************************************
602 * Initialize the hardware
604 **********************************************************************/
606 igb_hardware_init(struct e1000_hw *hw)
608 uint32_t rx_buf_size;
611 /* Let the firmware know the OS is in control */
612 igb_hw_control_acquire(hw);
615 * These parameters control the automatic generation (Tx) and
616 * response (Rx) to Ethernet PAUSE frames.
617 * - High water mark should allow for at least two standard size (1518)
618 * frames to be received after sending an XOFF.
619 * - Low water mark works best when it is very near the high water mark.
620 * This allows the receiver to restart by sending XON when it has
621 * drained a bit. Here we use an arbitary value of 1500 which will
622 * restart after one full frame is pulled from the buffer. There
623 * could be several smaller frames in the buffer and if so they will
624 * not trigger the XON until their total number reduces the buffer
626 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
628 rx_buf_size = igb_get_rx_buffer_size(hw);
630 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
631 hw->fc.low_water = hw->fc.high_water - 1500;
632 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
635 /* Set Flow control, use the tunable location if sane */
636 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
637 hw->fc.requested_mode = igb_fc_setting;
639 hw->fc.requested_mode = e1000_fc_none;
641 /* Issue a global reset */
643 E1000_WRITE_REG(hw, E1000_WUC, 0);
645 diag = e1000_init_hw(hw);
649 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
650 e1000_get_phy_info(hw);
651 e1000_check_for_link(hw);
656 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
658 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
660 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
661 struct e1000_hw_stats *stats =
662 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
665 if(hw->phy.media_type == e1000_media_type_copper ||
666 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
668 E1000_READ_REG(hw,E1000_SYMERRS);
669 stats->sec += E1000_READ_REG(hw, E1000_SEC);
672 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
673 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
674 stats->scc += E1000_READ_REG(hw, E1000_SCC);
675 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
677 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
678 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
679 stats->colc += E1000_READ_REG(hw, E1000_COLC);
680 stats->dc += E1000_READ_REG(hw, E1000_DC);
681 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
682 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
683 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
685 ** For watchdog management we need to know if we have been
686 ** paused during the last interval, so capture that here.
688 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
689 stats->xoffrxc += pause_frames;
690 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
691 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
692 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
693 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
694 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
695 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
696 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
697 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
698 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
699 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
700 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
701 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
703 /* For the 64-bit byte counters the low dword must be read first. */
704 /* Both registers clear on the read of the high dword */
706 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
707 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
708 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
709 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
711 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
712 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
713 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
714 stats->roc += E1000_READ_REG(hw, E1000_ROC);
715 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
717 stats->tor += E1000_READ_REG(hw, E1000_TORH);
718 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
720 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
721 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
722 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
723 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
724 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
725 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
726 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
727 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
728 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
729 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
731 /* Interrupt Counts */
733 stats->iac += E1000_READ_REG(hw, E1000_IAC);
734 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
735 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
736 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
737 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
738 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
739 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
740 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
741 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
743 /* Host to Card Statistics */
745 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
746 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
747 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
748 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
749 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
750 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
751 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
752 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
753 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
754 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
755 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
756 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
757 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
758 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
760 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
761 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
762 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
763 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
764 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
765 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
767 if (rte_stats == NULL)
771 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
772 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
775 rte_stats->oerrors = stats->ecol + stats->latecol;
777 rte_stats->ipackets = stats->gprc;
778 rte_stats->opackets = stats->gptc;
779 rte_stats->ibytes = stats->gorc;
780 rte_stats->obytes = stats->gotc;
784 eth_igb_stats_reset(struct rte_eth_dev *dev)
786 struct e1000_hw_stats *hw_stats =
787 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
789 /* HW registers are cleared on read */
790 eth_igb_stats_get(dev, NULL);
792 /* Reset software totals */
793 memset(hw_stats, 0, sizeof(*hw_stats));
797 eth_igb_infos_get(struct rte_eth_dev *dev,
798 struct rte_eth_dev_info *dev_info)
800 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
802 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
803 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
804 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
806 switch (hw->mac.type) {
808 dev_info->max_rx_queues = 4;
809 dev_info->max_tx_queues = 4;
813 dev_info->max_rx_queues = 16;
814 dev_info->max_tx_queues = 16;
818 dev_info->max_rx_queues = 8;
819 dev_info->max_tx_queues = 8;
823 dev_info->max_rx_queues = 8;
824 dev_info->max_tx_queues = 8;
828 /* Should not happen */
829 dev_info->max_rx_queues = 0;
830 dev_info->max_tx_queues = 0;
834 /* return 0 means link status changed, -1 means not changed */
836 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
838 struct e1000_hw *hw =
839 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
840 struct rte_eth_link link, old;
841 int link_check, count;
844 hw->mac.get_link_status = 1;
846 /* possible wait-to-complete in up to 9 seconds */
847 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
848 /* Read the real link status */
849 switch (hw->phy.media_type) {
850 case e1000_media_type_copper:
851 /* Do the work to read phy */
852 e1000_check_for_link(hw);
853 link_check = !hw->mac.get_link_status;
856 case e1000_media_type_fiber:
857 e1000_check_for_link(hw);
858 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
862 case e1000_media_type_internal_serdes:
863 e1000_check_for_link(hw);
864 link_check = hw->mac.serdes_has_link;
868 case e1000_media_type_unknown:
871 if (link_check || wait_to_complete == 0)
873 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
875 memset(&link, 0, sizeof(link));
876 rte_igb_dev_atomic_read_link_status(dev, &link);
879 /* Now we check if a transition has happened */
881 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
883 link.link_status = 1;
884 } else if (!link_check) {
886 link.link_duplex = 0;
887 link.link_status = 0;
889 rte_igb_dev_atomic_write_link_status(dev, &link);
892 if (old.link_status == link.link_status)
900 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
901 * For ASF and Pass Through versions of f/w this means
902 * that the driver is loaded.
905 igb_hw_control_acquire(struct e1000_hw *hw)
909 /* Let firmware know the driver has taken over */
910 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
911 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
915 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
916 * For ASF and Pass Through versions of f/w this means that the
917 * driver is no longer loaded.
920 igb_hw_control_release(struct e1000_hw *hw)
924 /* Let firmware taken over control of h/w */
925 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
926 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
927 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
931 * Bit of a misnomer, what this really means is
932 * to enable OS management of the system... aka
933 * to disable special hardware management features.
936 igb_init_manageability(struct e1000_hw *hw)
938 if (e1000_enable_mng_pass_thru(hw)) {
939 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
940 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
942 /* disable hardware interception of ARP */
943 manc &= ~(E1000_MANC_ARP_EN);
945 /* enable receiving management packets to the host */
946 manc |= E1000_MANC_EN_MNG2HOST;
947 manc2h |= 1 << 5; /* Mng Port 623 */
948 manc2h |= 1 << 6; /* Mng Port 664 */
949 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
950 E1000_WRITE_REG(hw, E1000_MANC, manc);
955 igb_release_manageability(struct e1000_hw *hw)
957 if (e1000_enable_mng_pass_thru(hw)) {
958 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
960 manc |= E1000_MANC_ARP_EN;
961 manc &= ~E1000_MANC_EN_MNG2HOST;
963 E1000_WRITE_REG(hw, E1000_MANC, manc);
968 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
970 struct e1000_hw *hw =
971 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
974 rctl = E1000_READ_REG(hw, E1000_RCTL);
975 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
976 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
980 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
982 struct e1000_hw *hw =
983 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
986 rctl = E1000_READ_REG(hw, E1000_RCTL);
987 rctl &= (~E1000_RCTL_UPE);
988 if (dev->data->all_multicast == 1)
989 rctl |= E1000_RCTL_MPE;
991 rctl &= (~E1000_RCTL_MPE);
992 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
996 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
998 struct e1000_hw *hw =
999 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002 rctl = E1000_READ_REG(hw, E1000_RCTL);
1003 rctl |= E1000_RCTL_MPE;
1004 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1008 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1010 struct e1000_hw *hw =
1011 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014 if (dev->data->promiscuous == 1)
1015 return; /* must remain in all_multicast mode */
1016 rctl = E1000_READ_REG(hw, E1000_RCTL);
1017 rctl &= (~E1000_RCTL_MPE);
1018 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1022 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1024 struct e1000_hw *hw =
1025 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026 struct e1000_vfta * shadow_vfta =
1027 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1032 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1033 E1000_VFTA_ENTRY_MASK);
1034 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1035 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1040 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1042 /* update local VFTA copy */
1043 shadow_vfta->vfta[vid_idx] = vfta;
1047 igb_vlan_hw_support_enable(struct rte_eth_dev *dev)
1049 struct e1000_hw *hw =
1050 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1051 struct e1000_vfta * shadow_vfta =
1052 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1056 /* VLAN Mode Enable */
1057 reg = E1000_READ_REG(hw, E1000_CTRL);
1058 reg |= E1000_CTRL_VME;
1059 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1061 /* Filter Table Enable */
1062 reg = E1000_READ_REG(hw, E1000_RCTL);
1063 reg &= ~E1000_RCTL_CFIEN;
1064 reg |= E1000_RCTL_VFE;
1065 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1067 /* Update maximum frame size */
1068 reg = E1000_READ_REG(hw, E1000_RLPML);
1069 reg += VLAN_TAG_SIZE;
1070 E1000_WRITE_REG(hw, E1000_RLPML, reg);
1072 /* restore VFTA table */
1073 for (i = 0; i < E1000_VFTA_SIZE; i++)
1074 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1078 igb_vlan_hw_support_disable(struct rte_eth_dev *dev)
1080 struct e1000_hw *hw =
1081 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1084 /* VLAN Mode disable */
1085 reg = E1000_READ_REG(hw, E1000_CTRL);
1086 reg &= ~E1000_CTRL_VME;
1087 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1091 igb_intr_disable(struct e1000_hw *hw)
1093 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1094 E1000_WRITE_FLUSH(hw);
1098 * It enables the interrupt mask and then enable the interrupt.
1101 * Pointer to struct rte_eth_dev.
1104 * - On success, zero.
1105 * - On failure, a negative value.
1108 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1110 struct e1000_hw *hw =
1111 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1114 E1000_WRITE_FLUSH(hw);
1115 rte_intr_enable(&(dev->pci_dev->intr_handle));
1121 * It reads ICR and gets interrupt causes, check it and set a bit flag
1122 * to update link status.
1125 * Pointer to struct rte_eth_dev.
1128 * - On success, zero.
1129 * - On failure, a negative value.
1132 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1135 struct e1000_hw *hw =
1136 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1137 struct e1000_interrupt *intr =
1138 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1140 /* read-on-clear nic registers here */
1141 icr = E1000_READ_REG(hw, E1000_ICR);
1142 if (icr & E1000_ICR_LSC) {
1143 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1150 * It executes link_update after knowing an interrupt is prsent.
1153 * Pointer to struct rte_eth_dev.
1156 * - On success, zero.
1157 * - On failure, a negative value.
1160 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1162 struct e1000_hw *hw =
1163 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1164 struct e1000_interrupt *intr =
1165 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1166 uint32_t tctl, rctl;
1167 struct rte_eth_link link;
1170 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1173 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1174 rte_intr_enable(&(dev->pci_dev->intr_handle));
1176 /* set get_link_status to check register later */
1177 hw->mac.get_link_status = 1;
1178 ret = eth_igb_link_update(dev, 0);
1180 /* check if link has changed */
1184 memset(&link, 0, sizeof(link));
1185 rte_igb_dev_atomic_read_link_status(dev, &link);
1186 if (link.link_status) {
1188 " Port %d: Link Up - speed %u Mbps - %s\n",
1189 dev->data->port_id, (unsigned)link.link_speed,
1190 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1191 "full-duplex" : "half-duplex");
1193 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1194 dev->data->port_id);
1196 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1197 dev->pci_dev->addr.domain,
1198 dev->pci_dev->addr.bus,
1199 dev->pci_dev->addr.devid,
1200 dev->pci_dev->addr.function);
1201 tctl = E1000_READ_REG(hw, E1000_TCTL);
1202 rctl = E1000_READ_REG(hw, E1000_RCTL);
1203 if (link.link_status) {
1205 tctl |= E1000_TCTL_EN;
1206 rctl |= E1000_RCTL_EN;
1209 tctl &= ~E1000_TCTL_EN;
1210 rctl &= ~E1000_RCTL_EN;
1212 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1213 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1214 E1000_WRITE_FLUSH(hw);
1220 * Interrupt handler which shall be registered at first.
1223 * Pointer to interrupt handle.
1225 * The address of parameter (struct rte_eth_dev *) regsitered before.
1231 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1233 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1235 eth_igb_interrupt_get_status(dev);
1236 eth_igb_interrupt_action(dev);
1237 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1241 eth_igb_led_on(struct rte_eth_dev *dev)
1243 struct e1000_hw *hw;
1245 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1250 eth_igb_led_off(struct rte_eth_dev *dev)
1252 struct e1000_hw *hw;
1254 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1255 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1259 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1261 struct e1000_hw *hw;
1263 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1269 uint32_t rx_buf_size;
1270 uint32_t max_high_water;
1272 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 rx_buf_size = igb_get_rx_buffer_size(hw);
1274 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1276 /* At least reserve one Ethernet frame for watermark */
1277 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1278 if ((fc_conf->high_water > max_high_water) ||
1279 (fc_conf->high_water < fc_conf->low_water)) {
1280 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1281 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1285 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1286 hw->fc.pause_time = fc_conf->pause_time;
1287 hw->fc.high_water = fc_conf->high_water;
1288 hw->fc.low_water = fc_conf->low_water;
1289 hw->fc.send_xon = fc_conf->send_xon;
1291 err = e1000_setup_link_generic(hw);
1292 if (err == E1000_SUCCESS) {
1296 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1301 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1302 uint32_t index, __rte_unused uint32_t pool)
1304 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1310 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1312 uint8_t addr[ETHER_ADDR_LEN];
1313 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1315 memset(addr, 0, sizeof(addr));
1317 e1000_rar_set(hw, addr, index);