1 /*******************************************************************************
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32 ***************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82598.h"
38 #include "ixgbe_dcb_82599.h"
39 #ident "$Id: ixgbe_dcb.c,v 1.55 2013/11/22 01:02:01 jtkirshe Exp $"
42 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
43 * credits from the configured bandwidth percentages. Credits
44 * are the smallest unit programmable into the underlying
45 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
46 * groups so this is much simplified from the CEE case.
48 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
51 int min_percent = 100;
52 int min_credit, multiplier;
55 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
56 IXGBE_DCB_CREDIT_QUANTUM;
58 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
59 if (bw[i] < min_percent && bw[i])
63 multiplier = (min_credit / min_percent) + 1;
65 /* Find out the hw credits for each TC */
66 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
67 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
73 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
80 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
81 * @ixgbe_dcb_config: Struct containing DCB settings.
82 * @direction: Configuring either Tx or Rx.
84 * This function calculates the credits allocated to each traffic class.
85 * It should be called only after the rules are checked by
86 * ixgbe_dcb_check_config_cee().
88 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
89 struct ixgbe_dcb_config *dcb_config,
90 u32 max_frame_size, u8 direction)
92 struct ixgbe_dcb_tc_path *p;
93 u32 min_multiplier = 0;
94 u16 min_percent = 100;
95 s32 ret_val = IXGBE_SUCCESS;
96 /* Initialization values default for Tx settings */
98 u32 credit_refill = 0;
100 u16 link_percentage = 0;
104 if (dcb_config == NULL) {
105 ret_val = IXGBE_ERR_CONFIG;
109 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
110 IXGBE_DCB_CREDIT_QUANTUM;
112 /* Find smallest link percentage */
113 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
114 p = &dcb_config->tc_config[i].path[direction];
115 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
116 link_percentage = p->bwg_percent;
118 link_percentage = (link_percentage * bw_percent) / 100;
120 if (link_percentage && link_percentage < min_percent)
121 min_percent = link_percentage;
125 * The ratio between traffic classes will control the bandwidth
126 * percentages seen on the wire. To calculate this ratio we use
127 * a multiplier. It is required that the refill credits must be
128 * larger than the max frame size so here we find the smallest
129 * multiplier that will allow all bandwidth percentages to be
130 * greater than the max frame size.
132 min_multiplier = (min_credit / min_percent) + 1;
134 /* Find out the link percentage for each TC first */
135 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
136 p = &dcb_config->tc_config[i].path[direction];
137 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
139 link_percentage = p->bwg_percent;
140 /* Must be careful of integer division for very small nums */
141 link_percentage = (link_percentage * bw_percent) / 100;
142 if (p->bwg_percent > 0 && link_percentage == 0)
145 /* Save link_percentage for reference */
146 p->link_percent = (u8)link_percentage;
148 /* Calculate credit refill ratio using multiplier */
149 credit_refill = min(link_percentage * min_multiplier,
150 (u32)IXGBE_DCB_MAX_CREDIT_REFILL);
151 p->data_credits_refill = (u16)credit_refill;
153 /* Calculate maximum credit for the TC */
154 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
157 * Adjustment based on rule checking, if the percentage
158 * of a TC is too small, the maximum credit may not be
159 * enough to send out a jumbo frame in data plane arbitration.
161 if (credit_max && (credit_max < min_credit))
162 credit_max = min_credit;
164 if (direction == IXGBE_DCB_TX_CONFIG) {
166 * Adjustment based on rule checking, if the
167 * percentage of a TC is too small, the maximum
168 * credit may not be enough to send out a TSO
169 * packet in descriptor plane arbitration.
171 if (credit_max && (credit_max <
172 IXGBE_DCB_MIN_TSO_CREDIT)
173 && (hw->mac.type == ixgbe_mac_82598EB))
174 credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
176 dcb_config->tc_config[i].desc_credits_max =
180 p->data_credits_max = (u16)credit_max;
188 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
189 * @cfg: dcb configuration to unpack into hardware consumable fields
190 * @map: user priority to traffic class map
191 * @pfc_up: u8 to store user priority PFC bitmask
193 * This unpacks the dcb configuration PFC info which is stored per
194 * traffic class into a 8bit user priority bitmask that can be
195 * consumed by hardware routines. The priority to tc map must be
196 * updated before calling this routine to use current up-to maps.
198 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
200 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
204 * If the TC for this user priority has PFC enabled then set the
205 * matching bit in 'pfc_up' to reflect that PFC is enabled.
207 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
208 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
213 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
216 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
219 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
220 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
223 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
225 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
228 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
229 max[tc] = tc_config[tc].desc_credits_max;
232 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
235 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
238 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
239 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
242 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
245 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
248 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
249 tsa[tc] = tc_config[tc].path[direction].tsa;
252 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
254 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
255 u8 prio_mask = 1 << up;
256 u8 tc = cfg->num_tcs.pg_tcs;
258 /* If tc is 0 then DCB is likely not enabled or supported */
263 * Test from maximum TC to 1 and report the first match we find. If
264 * we find no match we can assume that the TC is 0 since the TC must
265 * be set for all user priorities
267 for (tc--; tc; tc--) {
268 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
275 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
280 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
281 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
285 * ixgbe_dcb_config - Struct containing DCB settings.
286 * @dcb_config: Pointer to DCB config structure
288 * This function checks DCB rules for DCB settings.
289 * The following rules are checked:
290 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
291 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
292 * Group must total 100.
293 * 3. A Traffic Class should not be set to both Link Strict Priority
294 * and Group Strict Priority.
295 * 4. Link strict Bandwidth Groups can only have link strict traffic classes
296 * with zero bandwidth.
298 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
300 struct ixgbe_dcb_tc_path *p;
301 s32 ret_val = IXGBE_SUCCESS;
302 u8 i, j, bw = 0, bw_id;
303 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
304 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
306 memset(bw_sum, 0, sizeof(bw_sum));
307 memset(link_strict, 0, sizeof(link_strict));
309 /* First Tx, then Rx */
310 for (i = 0; i < 2; i++) {
311 /* Check each traffic class for rule violation */
312 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
313 p = &dcb_config->tc_config[j].path[i];
318 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
319 ret_val = IXGBE_ERR_CONFIG;
322 if (p->tsa == ixgbe_dcb_tsa_strict) {
323 link_strict[i][bw_id] = true;
324 /* Link strict should have zero bandwidth */
326 ret_val = IXGBE_ERR_CONFIG;
331 * Traffic classes without link strict
332 * should have non-zero bandwidth.
334 ret_val = IXGBE_ERR_CONFIG;
337 bw_sum[i][bw_id] += bw;
342 /* Check each bandwidth group for rule violation */
343 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
344 bw += dcb_config->bw_percentage[i][j];
346 * Sum of bandwidth percentages of all traffic classes
347 * within a Bandwidth Group must total 100 except for
348 * link strict group (zero bandwidth).
350 if (link_strict[i][j]) {
353 * Link strict group should have zero
356 ret_val = IXGBE_ERR_CONFIG;
359 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
361 ret_val = IXGBE_ERR_CONFIG;
366 if (bw != IXGBE_DCB_BW_PERCENT) {
367 ret_val = IXGBE_ERR_CONFIG;
373 DEBUGOUT2("DCB error code %d while checking %s settings.\n",
374 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
380 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
381 * @hw: pointer to hardware structure
382 * @stats: pointer to statistics structure
383 * @tc_count: Number of elements in bwg_array.
385 * This function returns the status data for each of the Traffic Classes in use.
387 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
390 s32 ret = IXGBE_NOT_IMPLEMENTED;
391 switch (hw->mac.type) {
392 case ixgbe_mac_82598EB:
393 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
395 case ixgbe_mac_82599EB:
397 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
406 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
407 * @hw: pointer to hardware structure
408 * @stats: pointer to statistics structure
409 * @tc_count: Number of elements in bwg_array.
411 * This function returns the CBFC status data for each of the Traffic Classes.
413 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
416 s32 ret = IXGBE_NOT_IMPLEMENTED;
417 switch (hw->mac.type) {
418 case ixgbe_mac_82598EB:
419 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
421 case ixgbe_mac_82599EB:
423 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
432 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
433 * @hw: pointer to hardware structure
434 * @dcb_config: pointer to ixgbe_dcb_config structure
436 * Configure Rx Data Arbiter and credits for each traffic class.
438 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
439 struct ixgbe_dcb_config *dcb_config)
441 s32 ret = IXGBE_NOT_IMPLEMENTED;
442 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
443 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
444 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
445 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
446 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
448 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
449 ixgbe_dcb_unpack_max_cee(dcb_config, max);
450 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
451 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
452 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
454 switch (hw->mac.type) {
455 case ixgbe_mac_82598EB:
456 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
458 case ixgbe_mac_82599EB:
460 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
470 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
471 * @hw: pointer to hardware structure
472 * @dcb_config: pointer to ixgbe_dcb_config structure
474 * Configure Tx Descriptor Arbiter and credits for each traffic class.
476 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
477 struct ixgbe_dcb_config *dcb_config)
479 s32 ret = IXGBE_NOT_IMPLEMENTED;
480 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
481 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
482 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
483 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
485 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
486 ixgbe_dcb_unpack_max_cee(dcb_config, max);
487 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
488 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
490 switch (hw->mac.type) {
491 case ixgbe_mac_82598EB:
492 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
495 case ixgbe_mac_82599EB:
497 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
507 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
508 * @hw: pointer to hardware structure
509 * @dcb_config: pointer to ixgbe_dcb_config structure
511 * Configure Tx Data Arbiter and credits for each traffic class.
513 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
514 struct ixgbe_dcb_config *dcb_config)
516 s32 ret = IXGBE_NOT_IMPLEMENTED;
517 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
518 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
519 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
520 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
521 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
523 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
524 ixgbe_dcb_unpack_max_cee(dcb_config, max);
525 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
526 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
527 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
529 switch (hw->mac.type) {
530 case ixgbe_mac_82598EB:
531 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
534 case ixgbe_mac_82599EB:
536 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
547 * ixgbe_dcb_config_pfc_cee - Config priority flow control
548 * @hw: pointer to hardware structure
549 * @dcb_config: pointer to ixgbe_dcb_config structure
551 * Configure Priority Flow Control for each traffic class.
553 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
554 struct ixgbe_dcb_config *dcb_config)
556 s32 ret = IXGBE_NOT_IMPLEMENTED;
558 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
560 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
561 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
563 switch (hw->mac.type) {
564 case ixgbe_mac_82598EB:
565 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
567 case ixgbe_mac_82599EB:
569 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
578 * ixgbe_dcb_config_tc_stats - Config traffic class statistics
579 * @hw: pointer to hardware structure
581 * Configure queue statistics registers, all queues belonging to same traffic
582 * class uses a single set of queue statistics counters.
584 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
586 s32 ret = IXGBE_NOT_IMPLEMENTED;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 ret = ixgbe_dcb_config_tc_stats_82598(hw);
591 case ixgbe_mac_82599EB:
593 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
602 * ixgbe_dcb_hw_config_cee - Config and enable DCB
603 * @hw: pointer to hardware structure
604 * @dcb_config: pointer to ixgbe_dcb_config structure
606 * Configure dcb settings and enable dcb mode.
608 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
609 struct ixgbe_dcb_config *dcb_config)
611 s32 ret = IXGBE_NOT_IMPLEMENTED;
613 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
614 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
615 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
616 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
617 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
619 /* Unpack CEE standard containers */
620 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
621 ixgbe_dcb_unpack_max_cee(dcb_config, max);
622 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
623 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
624 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
626 switch (hw->mac.type) {
627 case ixgbe_mac_82598EB:
628 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
629 refill, max, bwgid, tsa);
631 case ixgbe_mac_82599EB:
633 ixgbe_dcb_config_82599(hw, dcb_config);
634 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
638 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
644 if (!ret && dcb_config->pfc_mode_enable) {
645 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
646 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
652 /* Helper routines to abstract HW specifics from DCB netlink ops */
653 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
655 int ret = IXGBE_ERR_PARAM;
657 switch (hw->mac.type) {
658 case ixgbe_mac_82598EB:
659 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
661 case ixgbe_mac_82599EB:
663 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
671 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
672 u8 *bwg_id, u8 *tsa, u8 *map)
674 switch (hw->mac.type) {
675 case ixgbe_mac_82598EB:
676 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
677 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
679 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
682 case ixgbe_mac_82599EB:
684 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
686 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
688 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,