1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_x540.h"
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 #define IXGBE_X540_MAX_TX_QUEUES 128
41 #define IXGBE_X540_MAX_RX_QUEUES 128
42 #define IXGBE_X540_RAR_ENTRIES 128
43 #define IXGBE_X540_MC_TBL_SIZE 128
44 #define IXGBE_X540_VFT_TBL_SIZE 128
45 #define IXGBE_X540_RX_PB_SIZE 384
47 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
48 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
49 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
52 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
53 * @hw: pointer to hardware structure
55 * Initialize the function pointers and assign the MAC type for X540.
56 * Does not touch the hardware.
58 s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
61 struct ixgbe_phy_info *phy = &hw->phy;
62 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
65 DEBUGFUNC("ixgbe_init_ops_X540");
67 ret_val = ixgbe_init_phy_ops_generic(hw);
68 ret_val = ixgbe_init_ops_generic(hw);
72 eeprom->ops.init_params = &ixgbe_init_eeprom_params_X540;
73 eeprom->ops.read = &ixgbe_read_eerd_X540;
74 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_X540;
75 eeprom->ops.write = &ixgbe_write_eewr_X540;
76 eeprom->ops.write_buffer = &ixgbe_write_eewr_buffer_X540;
77 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_X540;
78 eeprom->ops.validate_checksum = &ixgbe_validate_eeprom_checksum_X540;
79 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_X540;
82 phy->ops.init = &ixgbe_init_phy_ops_generic;
83 phy->ops.reset = NULL;
86 mac->ops.reset_hw = &ixgbe_reset_hw_X540;
87 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
88 mac->ops.get_media_type = &ixgbe_get_media_type_X540;
89 mac->ops.get_supported_physical_layer =
90 &ixgbe_get_supported_physical_layer_X540;
91 mac->ops.read_analog_reg8 = NULL;
92 mac->ops.write_analog_reg8 = NULL;
93 mac->ops.start_hw = &ixgbe_start_hw_X540;
94 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
95 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
96 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
97 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
98 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
99 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540;
100 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540;
101 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
102 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
104 /* RAR, Multicast, VLAN */
105 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
106 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
107 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
108 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
109 mac->rar_highwater = 1;
110 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
111 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
112 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
113 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
114 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
115 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
118 mac->ops.get_link_capabilities =
119 &ixgbe_get_copper_link_capabilities_generic;
120 mac->ops.setup_link = &ixgbe_setup_mac_link_X540;
121 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
122 mac->ops.check_link = &ixgbe_check_mac_link_generic;
125 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
126 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
127 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
128 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
129 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
130 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
131 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
135 * ARC supported; valid only if manageability features are
138 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
139 IXGBE_FWSM_MODE_MASK) ? true : false;
141 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
144 mac->ops.blink_led_start = ixgbe_blink_led_start_X540;
145 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540;
147 /* Manageability interface */
148 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
150 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
156 * ixgbe_get_link_capabilities_X540 - Determines link capabilities
157 * @hw: pointer to hardware structure
158 * @speed: pointer to link speed
159 * @autoneg: true when autoneg or autotry is enabled
161 * Determines the link capabilities by reading the AUTOC register.
163 s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
164 ixgbe_link_speed *speed,
167 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg);
169 return IXGBE_SUCCESS;
173 * ixgbe_get_media_type_X540 - Get media type
174 * @hw: pointer to hardware structure
176 * Returns the media type (fiber, copper, backplane)
178 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
180 UNREFERENCED_1PARAMETER(hw);
181 return ixgbe_media_type_copper;
185 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities
186 * @hw: pointer to hardware structure
187 * @speed: new link speed
188 * @autoneg_wait_to_complete: true when waiting for completion is needed
190 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
191 ixgbe_link_speed speed,
192 bool autoneg_wait_to_complete)
194 DEBUGFUNC("ixgbe_setup_mac_link_X540");
195 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete);
199 * ixgbe_reset_hw_X540 - Perform hardware reset
200 * @hw: pointer to hardware structure
202 * Resets the hardware by resetting the transmit and receive units, masks
203 * and clears all interrupts, and perform a reset.
205 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
210 DEBUGFUNC("ixgbe_reset_hw_X540");
212 /* Call adapter stop to disable tx/rx and clear interrupts */
213 status = hw->mac.ops.stop_adapter(hw);
214 if (status != IXGBE_SUCCESS)
217 /* flush pending Tx transactions */
218 ixgbe_clear_tx_pending(hw);
221 ctrl = IXGBE_CTRL_RST;
222 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
223 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
224 IXGBE_WRITE_FLUSH(hw);
226 /* Poll for reset bit to self-clear indicating reset is complete */
227 for (i = 0; i < 10; i++) {
229 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
230 if (!(ctrl & IXGBE_CTRL_RST_MASK))
234 if (ctrl & IXGBE_CTRL_RST_MASK) {
235 status = IXGBE_ERR_RESET_FAILED;
236 ERROR_REPORT1(IXGBE_ERROR_POLLING,
237 "Reset polling failed to complete.\n");
242 * Double resets are required for recovery from certain error
243 * conditions. Between resets, it is necessary to stall to allow time
244 * for any pending HW events to complete.
246 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
247 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
251 /* Set the Rx packet buffer size. */
252 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
254 /* Store the permanent mac address */
255 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
258 * Store MAC address from RAR0, clear receive address registers, and
259 * clear the multicast table. Also reset num_rar_entries to 128,
260 * since we modify this value when programming the SAN MAC address.
262 hw->mac.num_rar_entries = 128;
263 hw->mac.ops.init_rx_addrs(hw);
265 /* Store the permanent SAN mac address */
266 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
268 /* Add the SAN MAC address to the RAR only if it's a valid address */
269 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
270 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
271 hw->mac.san_addr, 0, IXGBE_RAH_AV);
273 /* Save the SAN MAC RAR index */
274 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
276 /* Reserve the last RAR for the SAN MAC address */
277 hw->mac.num_rar_entries--;
280 /* Store the alternative WWNN/WWPN prefix */
281 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
282 &hw->mac.wwpn_prefix);
289 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
290 * @hw: pointer to hardware structure
292 * Starts the hardware using the generic start_hw function
293 * and the generation start_hw function.
294 * Then performs revision-specific operations, if any.
296 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
298 s32 ret_val = IXGBE_SUCCESS;
300 DEBUGFUNC("ixgbe_start_hw_X540");
302 ret_val = ixgbe_start_hw_generic(hw);
303 if (ret_val != IXGBE_SUCCESS)
306 ret_val = ixgbe_start_hw_gen2(hw);
313 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
314 * @hw: pointer to hardware structure
316 * Determines physical layer capabilities of the current configuration.
318 u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
320 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
323 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540");
325 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
326 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
327 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
328 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
329 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
330 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
331 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
332 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
334 return physical_layer;
338 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
339 * @hw: pointer to hardware structure
341 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
342 * ixgbe_hw struct in order to set up EEPROM access.
344 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
346 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
350 DEBUGFUNC("ixgbe_init_eeprom_params_X540");
352 if (eeprom->type == ixgbe_eeprom_uninitialized) {
353 eeprom->semaphore_delay = 10;
354 eeprom->type = ixgbe_flash;
356 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
357 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
358 IXGBE_EEC_SIZE_SHIFT);
359 eeprom->word_size = 1 << (eeprom_size +
360 IXGBE_EEPROM_WORD_SIZE_SHIFT);
362 DEBUGOUT2("Eeprom params: type = %d, size = %d\n",
363 eeprom->type, eeprom->word_size);
366 return IXGBE_SUCCESS;
370 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
371 * @hw: pointer to hardware structure
372 * @offset: offset of word in the EEPROM to read
373 * @data: word read from the EEPROM
375 * Reads a 16 bit word from the EEPROM using the EERD register.
377 s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
379 s32 status = IXGBE_SUCCESS;
381 DEBUGFUNC("ixgbe_read_eerd_X540");
382 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
384 status = ixgbe_read_eerd_generic(hw, offset, data);
385 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
387 status = IXGBE_ERR_SWFW_SYNC;
394 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD
395 * @hw: pointer to hardware structure
396 * @offset: offset of word in the EEPROM to read
397 * @words: number of words
398 * @data: word(s) read from the EEPROM
400 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
402 s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
403 u16 offset, u16 words, u16 *data)
405 s32 status = IXGBE_SUCCESS;
407 DEBUGFUNC("ixgbe_read_eerd_buffer_X540");
408 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
410 status = ixgbe_read_eerd_buffer_generic(hw, offset,
412 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
414 status = IXGBE_ERR_SWFW_SYNC;
421 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
422 * @hw: pointer to hardware structure
423 * @offset: offset of word in the EEPROM to write
424 * @data: word write to the EEPROM
426 * Write a 16 bit word to the EEPROM using the EEWR register.
428 s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
430 s32 status = IXGBE_SUCCESS;
432 DEBUGFUNC("ixgbe_write_eewr_X540");
433 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
435 status = ixgbe_write_eewr_generic(hw, offset, data);
436 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
438 status = IXGBE_ERR_SWFW_SYNC;
445 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
446 * @hw: pointer to hardware structure
447 * @offset: offset of word in the EEPROM to write
448 * @words: number of words
449 * @data: word(s) write to the EEPROM
451 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
453 s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
454 u16 offset, u16 words, u16 *data)
456 s32 status = IXGBE_SUCCESS;
458 DEBUGFUNC("ixgbe_write_eewr_buffer_X540");
459 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
461 status = ixgbe_write_eewr_buffer_generic(hw, offset,
463 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
465 status = IXGBE_ERR_SWFW_SYNC;
472 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
474 * This function does not use synchronization for EERD and EEWR. It can
475 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
477 * @hw: pointer to hardware structure
479 * Returns a negative error code on error, or the 16-bit checksum
481 s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
488 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
489 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
491 /* Do not use hw->eeprom.ops.read because we do not want to take
492 * the synchronization semaphores here. Instead use
493 * ixgbe_read_eerd_generic
496 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540");
498 /* Include 0x0-0x3F in the checksum */
499 for (i = 0; i <= checksum_last_word; i++) {
500 if (ixgbe_read_eerd_generic(hw, i, &word)) {
501 DEBUGOUT("EEPROM read failed\n");
502 return IXGBE_ERR_EEPROM;
504 if (i != IXGBE_EEPROM_CHECKSUM)
508 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
509 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
511 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
512 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
515 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
516 DEBUGOUT("EEPROM read failed\n");
517 return IXGBE_ERR_EEPROM;
520 /* Skip pointer section if the pointer is invalid. */
521 if (pointer == 0xFFFF || pointer == 0 ||
522 pointer >= hw->eeprom.word_size)
525 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
526 DEBUGOUT("EEPROM read failed\n");
527 return IXGBE_ERR_EEPROM;
530 /* Skip pointer section if length is invalid. */
531 if (length == 0xFFFF || length == 0 ||
532 (pointer + length) >= hw->eeprom.word_size)
535 for (j = pointer + 1; j <= pointer + length; j++) {
536 if (ixgbe_read_eerd_generic(hw, j, &word)) {
537 DEBUGOUT("EEPROM read failed\n");
538 return IXGBE_ERR_EEPROM;
544 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
546 return (s32)checksum;
550 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
551 * @hw: pointer to hardware structure
552 * @checksum_val: calculated checksum
554 * Performs checksum calculation and validates the EEPROM checksum. If the
555 * caller does not need checksum_val, the value can be NULL.
557 s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
562 u16 read_checksum = 0;
564 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540");
566 /* Read the first word from the EEPROM. If this times out or fails, do
567 * not continue or we could be in for a very long wait while every
570 status = hw->eeprom.ops.read(hw, 0, &checksum);
572 DEBUGOUT("EEPROM read failed\n");
576 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
577 return IXGBE_ERR_SWFW_SYNC;
579 status = hw->eeprom.ops.calc_checksum(hw);
583 checksum = (u16)(status & 0xffff);
585 /* Do not use hw->eeprom.ops.read because we do not want to take
586 * the synchronization semaphores twice here.
588 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
593 /* Verify read checksum from EEPROM is the same as
594 * calculated checksum
596 if (read_checksum != checksum) {
597 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,
598 "Invalid EEPROM checksum");
599 status = IXGBE_ERR_EEPROM_CHECKSUM;
602 /* If the user cares, return the calculated checksum */
604 *checksum_val = checksum;
607 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
613 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
614 * @hw: pointer to hardware structure
616 * After writing EEPROM to shadow RAM using EEWR register, software calculates
617 * checksum and updates the EEPROM and instructs the hardware to update
620 s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
625 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540");
627 /* Read the first word from the EEPROM. If this times out or fails, do
628 * not continue or we could be in for a very long wait while every
631 status = hw->eeprom.ops.read(hw, 0, &checksum);
633 DEBUGOUT("EEPROM read failed\n");
637 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
638 return IXGBE_ERR_SWFW_SYNC;
640 status = hw->eeprom.ops.calc_checksum(hw);
644 checksum = (u16)(status & 0xffff);
646 /* Do not use hw->eeprom.ops.write because we do not want to
647 * take the synchronization semaphores twice here.
649 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
653 status = ixgbe_update_flash_X540(hw);
656 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
662 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
663 * @hw: pointer to hardware structure
665 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
666 * EEPROM from shadow RAM to the flash device.
668 s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
673 DEBUGFUNC("ixgbe_update_flash_X540");
675 status = ixgbe_poll_flash_update_done_X540(hw);
676 if (status == IXGBE_ERR_EEPROM) {
677 DEBUGOUT("Flash update time out\n");
681 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
682 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
684 status = ixgbe_poll_flash_update_done_X540(hw);
685 if (status == IXGBE_SUCCESS)
686 DEBUGOUT("Flash update complete\n");
688 DEBUGOUT("Flash update time out\n");
690 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) {
691 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
693 if (flup & IXGBE_EEC_SEC1VAL) {
694 flup |= IXGBE_EEC_FLUP;
695 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
698 status = ixgbe_poll_flash_update_done_X540(hw);
699 if (status == IXGBE_SUCCESS)
700 DEBUGOUT("Flash update complete\n");
702 DEBUGOUT("Flash update time out\n");
709 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
710 * @hw: pointer to hardware structure
712 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
713 * flash update is done.
715 STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
719 s32 status = IXGBE_ERR_EEPROM;
721 DEBUGFUNC("ixgbe_poll_flash_update_done_X540");
723 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
724 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
725 if (reg & IXGBE_EEC_FLUDONE) {
726 status = IXGBE_SUCCESS;
732 if (i == IXGBE_FLUDONE_ATTEMPTS)
733 ERROR_REPORT1(IXGBE_ERROR_POLLING,
734 "Flash update status polling timed out");
740 * ixgbe_set_mux - Set mux for port 1 access with CS4227
741 * @hw: pointer to hardware structure
742 * @state: set mux if 1, clear if 0
744 STATIC void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
750 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
752 esdp |= IXGBE_ESDP_SDP1;
754 esdp &= ~IXGBE_ESDP_SDP1;
755 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
756 IXGBE_WRITE_FLUSH(hw);
760 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
761 * @hw: pointer to hardware structure
762 * @mask: Mask to specify which semaphore to acquire
764 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
765 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
767 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
769 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
770 u32 fwmask = swmask << 5;
771 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
777 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540");
779 if (swmask & IXGBE_GSSR_EEP_SM)
780 hwmask |= IXGBE_GSSR_FLASH_SM;
782 /* SW only mask doesn't have FW bit pair */
783 if (mask & IXGBE_GSSR_SW_MNG_SM)
784 swmask |= IXGBE_GSSR_SW_MNG_SM;
786 swmask |= swi2c_mask;
787 fwmask |= swi2c_mask << 2;
788 for (i = 0; i < timeout; i++) {
789 /* SW NVM semaphore bit is used for access to all
790 * SW_FW_SYNC bits (not just NVM)
792 if (ixgbe_get_swfw_sync_semaphore(hw))
793 return IXGBE_ERR_SWFW_SYNC;
795 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
796 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
798 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
799 ixgbe_release_swfw_sync_semaphore(hw);
802 ixgbe_set_mux(hw, 1);
803 return IXGBE_SUCCESS;
805 /* Firmware currently using resource (fwmask), hardware
806 * currently using resource (hwmask), or other software
807 * thread currently using resource (swmask)
809 ixgbe_release_swfw_sync_semaphore(hw);
813 /* Failed to get SW only semaphore */
814 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
815 ERROR_REPORT1(IXGBE_ERROR_POLLING,
816 "Failed to get SW only semaphore");
817 return IXGBE_ERR_SWFW_SYNC;
820 /* If the resource is not released by the FW/HW the SW can assume that
821 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
822 * of the requested resource(s) while ignoring the corresponding FW/HW
823 * bits in the SW_FW_SYNC register.
825 if (ixgbe_get_swfw_sync_semaphore(hw))
826 return IXGBE_ERR_SWFW_SYNC;
827 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
828 if (swfw_sync & (fwmask | hwmask)) {
830 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
831 ixgbe_release_swfw_sync_semaphore(hw);
834 ixgbe_set_mux(hw, 1);
835 return IXGBE_SUCCESS;
837 /* If the resource is not released by other SW the SW can assume that
838 * the other SW malfunctions. In that case the SW should clear all SW
839 * flags that it does not own and then repeat the whole process once
842 if (swfw_sync & swmask) {
843 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
844 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
847 rmask |= IXGBE_GSSR_I2C_MASK;
848 ixgbe_release_swfw_sync_X540(hw, rmask);
849 ixgbe_release_swfw_sync_semaphore(hw);
850 return IXGBE_ERR_SWFW_SYNC;
852 ixgbe_release_swfw_sync_semaphore(hw);
854 return IXGBE_ERR_SWFW_SYNC;
858 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
859 * @hw: pointer to hardware structure
860 * @mask: Mask to specify which semaphore to release
862 * Releases the SWFW semaphore through the SW_FW_SYNC register
863 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
865 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
867 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
870 DEBUGFUNC("ixgbe_release_swfw_sync_X540");
872 if (mask & IXGBE_GSSR_I2C_MASK) {
873 swmask |= mask & IXGBE_GSSR_I2C_MASK;
874 ixgbe_set_mux(hw, 0);
876 ixgbe_get_swfw_sync_semaphore(hw);
878 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
879 swfw_sync &= ~swmask;
880 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
882 ixgbe_release_swfw_sync_semaphore(hw);
887 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
888 * @hw: pointer to hardware structure
890 * Sets the hardware semaphores so SW/FW can gain control of shared resources
892 STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
894 s32 status = IXGBE_ERR_EEPROM;
899 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore");
901 /* Get SMBI software semaphore between device drivers first */
902 for (i = 0; i < timeout; i++) {
904 * If the SMBI bit is 0 when we read it, then the bit will be
905 * set and we have the semaphore
907 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
908 if (!(swsm & IXGBE_SWSM_SMBI)) {
909 status = IXGBE_SUCCESS;
915 /* Now get the semaphore between SW/FW through the REGSMP bit */
916 if (status == IXGBE_SUCCESS) {
917 for (i = 0; i < timeout; i++) {
918 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
919 if (!(swsm & IXGBE_SWFW_REGSMP))
926 * Release semaphores and return error if SW NVM semaphore
927 * was not granted because we don't have access to the EEPROM
930 ERROR_REPORT1(IXGBE_ERROR_POLLING,
931 "REGSMP Software NVM semaphore not granted.\n");
932 ixgbe_release_swfw_sync_semaphore(hw);
933 status = IXGBE_ERR_EEPROM;
936 ERROR_REPORT1(IXGBE_ERROR_POLLING,
937 "Software semaphore SMBI between device drivers "
945 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
946 * @hw: pointer to hardware structure
948 * This function clears hardware semaphore bits.
950 STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
954 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore");
956 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
958 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
959 swsm &= ~IXGBE_SWSM_SMBI;
960 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
962 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
963 swsm &= ~IXGBE_SWFW_REGSMP;
964 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
966 IXGBE_WRITE_FLUSH(hw);
970 * ixgbe_blink_led_start_X540 - Blink LED based on index.
971 * @hw: pointer to hardware structure
972 * @index: led number to blink
974 * Devices that implement the version 2 interface:
977 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
981 ixgbe_link_speed speed;
984 DEBUGFUNC("ixgbe_blink_led_start_X540");
987 * Link should be up in order for the blink bit in the LED control
988 * register to work. Force link and speed in the MAC if link is down.
989 * This will be reversed when we stop the blinking.
991 hw->mac.ops.check_link(hw, &speed, &link_up, false);
992 if (link_up == false) {
993 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
994 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
995 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
997 /* Set the LED to LINK_UP + BLINK. */
998 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
999 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1000 ledctl_reg |= IXGBE_LED_BLINK(index);
1001 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1002 IXGBE_WRITE_FLUSH(hw);
1004 return IXGBE_SUCCESS;
1008 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
1009 * @hw: pointer to hardware structure
1010 * @index: led number to stop blinking
1012 * Devices that implement the version 2 interface:
1015 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
1020 DEBUGFUNC("ixgbe_blink_led_stop_X540");
1022 /* Restore the LED to its default value. */
1023 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1024 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
1025 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
1026 ledctl_reg &= ~IXGBE_LED_BLINK(index);
1027 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
1029 /* Unforce link and speed in the MAC. */
1030 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
1031 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
1032 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
1033 IXGBE_WRITE_FLUSH(hw);
1035 return IXGBE_SUCCESS;