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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_atomic.h>
51 #include <rte_branch_prediction.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_malloc.h>
62 #include "ixgbe_logs.h"
63 #include "ixgbe/ixgbe_api.h"
64 #include "ixgbe/ixgbe_vf.h"
65 #include "ixgbe/ixgbe_common.h"
66 #include "ixgbe_ethdev.h"
67 #include "ixgbe_bypass.h"
70 * High threshold controlling when to start sending XOFF frames. Must be at
71 * least 8 bytes less than receive packet buffer size. This value is in units
74 #define IXGBE_FC_HI 0x80
77 * Low threshold controlling when to start sending XON frames. This value is
78 * in units of 1024 bytes.
80 #define IXGBE_FC_LO 0x40
82 /* Timer value included in XOFF frames. */
83 #define IXGBE_FC_PAUSE 0x680
85 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
86 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
87 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
90 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
92 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
94 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
95 struct rte_eth_dev *eth_dev);
96 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
97 static int ixgbe_dev_start(struct rte_eth_dev *dev);
98 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
99 static void ixgbe_dev_close(struct rte_eth_dev *dev);
100 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
101 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
102 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
103 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
104 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
105 int wait_to_complete);
106 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
107 struct rte_eth_stats *stats);
108 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
109 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
113 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
114 struct rte_eth_dev_info *dev_info);
115 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
116 uint16_t vlan_id, int on);
117 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
118 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
119 uint16_t queue, bool on);
120 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
122 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
124 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
125 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
126 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
128 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
129 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
130 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
131 struct rte_eth_fc_conf *fc_conf);
132 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
133 struct rte_eth_pfc_conf *pfc_conf);
134 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
135 struct rte_eth_rss_reta *reta_conf);
136 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
137 struct rte_eth_rss_reta *reta_conf);
138 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
139 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
140 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
141 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
142 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
144 static void ixgbe_dev_interrupt_delayed_handler(void *param);
145 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
146 uint32_t index, uint32_t pool);
147 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
148 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
150 /* For Virtual Function support */
151 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
152 struct rte_eth_dev *eth_dev);
153 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
154 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
155 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
156 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
157 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
158 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
159 struct rte_eth_stats *stats);
160 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
161 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
162 uint16_t vlan_id, int on);
163 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
164 uint16_t queue, int on);
165 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
166 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
168 /* For Eth VMDQ APIs support */
169 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
170 ether_addr* mac_addr,uint8_t on);
171 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
172 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
173 uint16_t rx_mask, uint8_t on);
174 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
175 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
176 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
177 uint64_t pool_mask,uint8_t vlan_on);
178 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
179 struct rte_eth_vmdq_mirror_conf *mirror_conf,
180 uint8_t rule_id, uint8_t on);
181 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
185 * Define VF Stats MACRO for Non "cleared on read" register
187 #define UPDATE_VF_STAT(reg, last, cur) \
189 u32 latest = IXGBE_READ_REG(hw, reg); \
190 cur += latest - last; \
194 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
196 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
197 u64 new_msb = IXGBE_READ_REG(hw, msb); \
198 u64 latest = ((new_msb << 32) | new_lsb); \
199 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
203 #define IXGBE_SET_HWSTRIP(h, q) do{\
204 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
205 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
206 (h)->bitmap[idx] |= 1 << bit;\
209 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
210 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
211 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
212 (h)->bitmap[idx] &= ~(1 << bit);\
215 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
216 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
217 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
218 (r) = (h)->bitmap[idx] >> bit & 1;\
222 * The set of PCI devices this driver supports
224 static struct rte_pci_id pci_id_ixgbe_map[] = {
226 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
227 #include "rte_pci_dev_ids.h"
229 { .vendor_id = 0, /* sentinel */ },
234 * The set of PCI devices this driver supports (for 82599 VF)
236 static struct rte_pci_id pci_id_ixgbevf_map[] = {
238 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
239 #include "rte_pci_dev_ids.h"
240 { .vendor_id = 0, /* sentinel */ },
244 static struct eth_dev_ops ixgbe_eth_dev_ops = {
245 .dev_configure = ixgbe_dev_configure,
246 .dev_start = ixgbe_dev_start,
247 .dev_stop = ixgbe_dev_stop,
248 .dev_close = ixgbe_dev_close,
249 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
250 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
251 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
252 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
253 .link_update = ixgbe_dev_link_update,
254 .stats_get = ixgbe_dev_stats_get,
255 .stats_reset = ixgbe_dev_stats_reset,
256 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
257 .dev_infos_get = ixgbe_dev_info_get,
258 .vlan_filter_set = ixgbe_vlan_filter_set,
259 .vlan_tpid_set = ixgbe_vlan_tpid_set,
260 .vlan_offload_set = ixgbe_vlan_offload_set,
261 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
262 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
263 .rx_queue_release = ixgbe_dev_rx_queue_release,
264 .rx_queue_count = ixgbe_dev_rx_queue_count,
265 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
266 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
267 .tx_queue_release = ixgbe_dev_tx_queue_release,
268 .dev_led_on = ixgbe_dev_led_on,
269 .dev_led_off = ixgbe_dev_led_off,
270 .flow_ctrl_set = ixgbe_flow_ctrl_set,
271 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
272 .mac_addr_add = ixgbe_add_rar,
273 .mac_addr_remove = ixgbe_remove_rar,
274 .uc_hash_table_set = ixgbe_uc_hash_table_set,
275 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
276 .mirror_rule_set = ixgbe_mirror_rule_set,
277 .mirror_rule_reset = ixgbe_mirror_rule_reset,
278 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
279 .set_vf_rx = ixgbe_set_pool_rx,
280 .set_vf_tx = ixgbe_set_pool_tx,
281 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
282 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
283 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
284 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
285 .fdir_infos_get = ixgbe_fdir_info_get,
286 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
287 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
288 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
289 .fdir_set_masks = ixgbe_fdir_set_masks,
290 .reta_update = ixgbe_dev_rss_reta_update,
291 .reta_query = ixgbe_dev_rss_reta_query,
292 #ifdef RTE_NIC_BYPASS
293 .bypass_init = ixgbe_bypass_init,
294 .bypass_state_set = ixgbe_bypass_state_store,
295 .bypass_state_show = ixgbe_bypass_state_show,
296 .bypass_event_set = ixgbe_bypass_event_store,
297 .bypass_event_show = ixgbe_bypass_event_show,
298 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
299 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
300 .bypass_ver_show = ixgbe_bypass_ver_show,
301 .bypass_wd_reset = ixgbe_bypass_wd_reset,
302 #endif /* RTE_NIC_BYPASS */
306 * dev_ops for virtual function, bare necessities for basic vf
307 * operation have been implemented
309 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
311 .dev_configure = ixgbevf_dev_configure,
312 .dev_start = ixgbevf_dev_start,
313 .dev_stop = ixgbevf_dev_stop,
314 .link_update = ixgbe_dev_link_update,
315 .stats_get = ixgbevf_dev_stats_get,
316 .stats_reset = ixgbevf_dev_stats_reset,
317 .dev_close = ixgbevf_dev_close,
318 .dev_infos_get = ixgbe_dev_info_get,
319 .vlan_filter_set = ixgbevf_vlan_filter_set,
320 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
321 .vlan_offload_set = ixgbevf_vlan_offload_set,
322 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
323 .rx_queue_release = ixgbe_dev_rx_queue_release,
324 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
325 .tx_queue_release = ixgbe_dev_tx_queue_release,
329 * Atomically reads the link status information from global
330 * structure rte_eth_dev.
333 * - Pointer to the structure rte_eth_dev to read from.
334 * - Pointer to the buffer to be saved with the link status.
337 * - On success, zero.
338 * - On failure, negative value.
341 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
342 struct rte_eth_link *link)
344 struct rte_eth_link *dst = link;
345 struct rte_eth_link *src = &(dev->data->dev_link);
347 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
348 *(uint64_t *)src) == 0)
355 * Atomically writes the link status information into global
356 * structure rte_eth_dev.
359 * - Pointer to the structure rte_eth_dev to read from.
360 * - Pointer to the buffer to be saved with the link status.
363 * - On success, zero.
364 * - On failure, negative value.
367 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
368 struct rte_eth_link *link)
370 struct rte_eth_link *dst = &(dev->data->dev_link);
371 struct rte_eth_link *src = link;
373 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
374 *(uint64_t *)src) == 0)
381 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
384 ixgbe_is_sfp(struct ixgbe_hw *hw)
386 switch (hw->phy.type) {
387 case ixgbe_phy_sfp_avago:
388 case ixgbe_phy_sfp_ftl:
389 case ixgbe_phy_sfp_intel:
390 case ixgbe_phy_sfp_unknown:
391 case ixgbe_phy_sfp_passive_tyco:
392 case ixgbe_phy_sfp_passive_unknown:
399 static inline int32_t
400 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
405 status = ixgbe_reset_hw(hw);
407 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
408 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
409 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
410 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
411 IXGBE_WRITE_FLUSH(hw);
417 ixgbe_enable_intr(struct rte_eth_dev *dev)
419 struct ixgbe_interrupt *intr =
420 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
421 struct ixgbe_hw *hw =
422 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
424 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
425 IXGBE_WRITE_FLUSH(hw);
429 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
432 ixgbe_disable_intr(struct ixgbe_hw *hw)
434 PMD_INIT_FUNC_TRACE();
436 if (hw->mac.type == ixgbe_mac_82598EB) {
437 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
439 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
440 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
441 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
443 IXGBE_WRITE_FLUSH(hw);
447 * This function resets queue statistics mapping registers.
448 * From Niantic datasheet, Initialization of Statistics section:
449 * "...if software requires the queue counters, the RQSMR and TQSM registers
450 * must be re-programmed following a device reset.
453 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
457 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
458 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
459 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
465 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
470 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
471 #define NB_QMAP_FIELDS_PER_QSM_REG 4
472 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
474 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
475 struct ixgbe_stat_mapping_registers *stat_mappings =
476 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
477 uint32_t qsmr_mask = 0;
478 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
482 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
485 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
486 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
488 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
489 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
490 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
493 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
495 /* Now clear any previous stat_idx set */
496 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
498 stat_mappings->tqsm[n] &= ~clearing_mask;
500 stat_mappings->rqsmr[n] &= ~clearing_mask;
502 q_map = (uint32_t)stat_idx;
503 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
504 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
506 stat_mappings->tqsm[n] |= qsmr_mask;
508 stat_mappings->rqsmr[n] |= qsmr_mask;
510 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
512 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
513 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
515 /* Now write the mapping in the appropriate register */
517 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
518 stat_mappings->rqsmr[n], n);
519 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
522 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
523 stat_mappings->tqsm[n], n);
524 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
530 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
532 struct ixgbe_stat_mapping_registers *stat_mappings =
533 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
534 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
537 /* write whatever was in stat mapping table to the NIC */
538 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
540 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
543 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
548 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
551 struct ixgbe_dcb_tc_config *tc;
552 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
554 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
555 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
556 for (i = 0; i < dcb_max_tc; i++) {
557 tc = &dcb_config->tc_config[i];
558 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
559 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
560 (uint8_t)(100/dcb_max_tc + (i & 1));
561 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
562 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
563 (uint8_t)(100/dcb_max_tc + (i & 1));
564 tc->pfc = ixgbe_dcb_pfc_disabled;
567 /* Initialize default user to priority mapping, UPx->TC0 */
568 tc = &dcb_config->tc_config[0];
569 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
570 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
571 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
572 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
573 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
575 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
576 dcb_config->pfc_mode_enable = false;
577 dcb_config->vt_mode = true;
578 dcb_config->round_robin_enable = false;
579 /* support all DCB capabilities in 82599 */
580 dcb_config->support.capabilities = 0xFF;
582 /*we only support 4 Tcs for X540*/
583 if (hw->mac.type == ixgbe_mac_X540) {
584 dcb_config->num_tcs.pg_tcs = 4;
585 dcb_config->num_tcs.pfc_tcs = 4;
590 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
591 * It returns 0 on success.
594 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
595 struct rte_eth_dev *eth_dev)
597 struct rte_pci_device *pci_dev;
598 struct ixgbe_hw *hw =
599 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
600 struct ixgbe_vfta * shadow_vfta =
601 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
602 struct ixgbe_hwstrip *hwstrip =
603 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
604 struct ixgbe_dcb_config *dcb_config =
605 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
610 PMD_INIT_FUNC_TRACE();
612 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
613 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
614 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
616 /* for secondary processes, we don't initialise any further as primary
617 * has already done this work. Only check we don't need a different
619 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
620 if (eth_dev->data->scattered_rx)
621 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
624 pci_dev = eth_dev->pci_dev;
626 /* Vendor and Device ID need to be set before init of shared code */
627 hw->device_id = pci_dev->id.device_id;
628 hw->vendor_id = pci_dev->id.vendor_id;
629 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
630 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
631 hw->allow_unsupported_sfp = 1;
634 /* Initialize the shared code */
635 #ifdef RTE_NIC_BYPASS
636 diag = ixgbe_bypass_init_shared_code(hw);
638 diag = ixgbe_init_shared_code(hw);
639 #endif /* RTE_NIC_BYPASS */
641 if (diag != IXGBE_SUCCESS) {
642 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
646 /* Initialize DCB configuration*/
647 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
648 ixgbe_dcb_init(hw,dcb_config);
649 /* Get Hardware Flow Control setting */
650 hw->fc.requested_mode = ixgbe_fc_full;
651 hw->fc.current_mode = ixgbe_fc_full;
652 hw->fc.pause_time = IXGBE_FC_PAUSE;
653 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
654 hw->fc.low_water[i] = IXGBE_FC_LO;
655 hw->fc.high_water[i] = IXGBE_FC_HI;
659 /* Make sure we have a good EEPROM before we read from it */
660 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
661 if (diag != IXGBE_SUCCESS) {
662 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
666 #ifdef RTE_NIC_BYPASS
667 diag = ixgbe_bypass_init_hw(hw);
669 diag = ixgbe_init_hw(hw);
670 #endif /* RTE_NIC_BYPASS */
673 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
674 * is called too soon after the kernel driver unbinding/binding occurs.
675 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
676 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
677 * also called. See ixgbe_identify_phy_82599(). The reason for the
678 * failure is not known, and only occuts when virtualisation features
679 * are disabled in the bios. A delay of 100ms was found to be enough by
680 * trial-and-error, and is doubled to be safe.
682 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
684 diag = ixgbe_init_hw(hw);
687 if (diag == IXGBE_ERR_EEPROM_VERSION) {
688 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
689 "LOM. Please be aware there may be issues associated "
690 "with your hardware.\n If you are experiencing problems "
691 "please contact your Intel or hardware representative "
692 "who provided you with this hardware.\n");
693 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
694 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
696 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
700 /* disable interrupt */
701 ixgbe_disable_intr(hw);
703 /* pick up the PCI bus settings for reporting later */
704 ixgbe_get_bus_info(hw);
706 /* reset mappings for queue statistics hw counters*/
707 ixgbe_reset_qstat_mappings(hw);
709 /* Allocate memory for storing MAC addresses */
710 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
711 hw->mac.num_rar_entries, 0);
712 if (eth_dev->data->mac_addrs == NULL) {
714 "Failed to allocate %d bytes needed to store MAC addresses",
715 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
718 /* Copy the permanent MAC address */
719 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
720 ð_dev->data->mac_addrs[0]);
722 /* Allocate memory for storing hash filter MAC addresses */
723 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
724 IXGBE_VMDQ_NUM_UC_MAC, 0);
725 if (eth_dev->data->hash_mac_addrs == NULL) {
727 "Failed to allocate %d bytes needed to store MAC addresses",
728 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
732 /* initialize the vfta */
733 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
735 /* initialize the hw strip bitmap*/
736 memset(hwstrip, 0, sizeof(*hwstrip));
738 /* initialize PF if max_vfs not zero */
739 ixgbe_pf_host_init(eth_dev);
741 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
742 /* let hardware know driver is loaded */
743 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
744 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
745 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
746 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
747 IXGBE_WRITE_FLUSH(hw);
749 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
751 "MAC: %d, PHY: %d, SFP+: %d<n",
752 (int) hw->mac.type, (int) hw->phy.type,
753 (int) hw->phy.sfp_type);
755 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
756 (int) hw->mac.type, (int) hw->phy.type);
758 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
759 eth_dev->data->port_id, pci_dev->id.vendor_id,
760 pci_dev->id.device_id);
762 rte_intr_callback_register(&(pci_dev->intr_handle),
763 ixgbe_dev_interrupt_handler, (void *)eth_dev);
765 /* enable uio intr after callback register */
766 rte_intr_enable(&(pci_dev->intr_handle));
768 /* enable support intr */
769 ixgbe_enable_intr(eth_dev);
775 * Virtual Function device init
778 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
779 struct rte_eth_dev *eth_dev)
781 struct rte_pci_device *pci_dev;
782 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
784 struct ixgbe_vfta * shadow_vfta =
785 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
786 struct ixgbe_hwstrip *hwstrip =
787 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
789 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
791 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
792 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
793 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
795 /* for secondary processes, we don't initialise any further as primary
796 * has already done this work. Only check we don't need a different
798 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
799 if (eth_dev->data->scattered_rx)
800 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
804 pci_dev = eth_dev->pci_dev;
806 hw->device_id = pci_dev->id.device_id;
807 hw->vendor_id = pci_dev->id.vendor_id;
808 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
810 /* initialize the vfta */
811 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
813 /* initialize the hw strip bitmap*/
814 memset(hwstrip, 0, sizeof(*hwstrip));
816 /* Initialize the shared code */
817 diag = ixgbe_init_shared_code(hw);
818 if (diag != IXGBE_SUCCESS) {
819 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
823 /* init_mailbox_params */
824 hw->mbx.ops.init_params(hw);
826 /* Disable the interrupts for VF */
827 ixgbevf_intr_disable(hw);
829 hw->mac.num_rar_entries = hw->mac.max_rx_queues;
830 diag = hw->mac.ops.reset_hw(hw);
832 if (diag != IXGBE_SUCCESS) {
833 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
834 RTE_LOG(ERR, PMD, "\tThe MAC address is not valid.\n"
835 "\tThe most likely cause of this error is that the VM host\n"
836 "\thas not assigned a valid MAC address to this VF device.\n"
837 "\tPlease consult the DPDK Release Notes (FAQ section) for\n"
838 "\ta possible solution to this problem.\n");
842 /* Allocate memory for storing MAC addresses */
843 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
844 hw->mac.num_rar_entries, 0);
845 if (eth_dev->data->mac_addrs == NULL) {
847 "Failed to allocate %d bytes needed to store MAC addresses",
848 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
852 /* Copy the permanent MAC address */
853 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
854 ð_dev->data->mac_addrs[0]);
856 /* reset the hardware with the new settings */
857 diag = hw->mac.ops.start_hw(hw);
863 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
867 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
868 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
869 "ixgbe_mac_82599_vf");
874 static struct eth_driver rte_ixgbe_pmd = {
876 .name = "rte_ixgbe_pmd",
877 .id_table = pci_id_ixgbe_map,
878 #ifdef RTE_EAL_UNBIND_PORTS
879 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
882 .eth_dev_init = eth_ixgbe_dev_init,
883 .dev_private_size = sizeof(struct ixgbe_adapter),
887 * virtual function driver struct
889 static struct eth_driver rte_ixgbevf_pmd = {
891 .name = "rte_ixgbevf_pmd",
892 .id_table = pci_id_ixgbevf_map,
893 #ifdef RTE_EAL_UNBIND_PORTS
894 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
897 .eth_dev_init = eth_ixgbevf_dev_init,
898 .dev_private_size = sizeof(struct ixgbe_adapter),
902 * Driver initialization routine.
903 * Invoked once at EAL init time.
904 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
907 rte_ixgbe_pmd_init(void)
909 PMD_INIT_FUNC_TRACE();
911 rte_eth_driver_register(&rte_ixgbe_pmd);
916 * VF Driver initialization routine.
917 * Invoked one at EAL init time.
918 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
921 rte_ixgbevf_pmd_init(void)
923 DEBUGFUNC("rte_ixgbevf_pmd_init");
925 rte_eth_driver_register(&rte_ixgbevf_pmd);
930 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
932 struct ixgbe_hw *hw =
933 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
934 struct ixgbe_vfta * shadow_vfta =
935 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
940 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
941 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
942 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
947 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
949 /* update local VFTA copy */
950 shadow_vfta->vfta[vid_idx] = vfta;
956 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
959 ixgbe_vlan_hw_strip_enable(dev, queue);
961 ixgbe_vlan_hw_strip_disable(dev, queue);
965 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
967 struct ixgbe_hw *hw =
968 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
970 /* Only the high 16-bits is valid */
971 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
975 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
977 struct ixgbe_hw *hw =
978 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
981 PMD_INIT_FUNC_TRACE();
983 /* Filter Table Disable */
984 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
985 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
987 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
991 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
993 struct ixgbe_hw *hw =
994 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
995 struct ixgbe_vfta * shadow_vfta =
996 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1000 PMD_INIT_FUNC_TRACE();
1002 /* Filter Table Enable */
1003 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1004 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1005 vlnctrl |= IXGBE_VLNCTRL_VFE;
1007 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1009 /* write whatever is in local vfta copy */
1010 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1011 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1015 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1017 struct ixgbe_hwstrip *hwstrip =
1018 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1020 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1024 IXGBE_SET_HWSTRIP(hwstrip, queue);
1026 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1030 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1032 struct ixgbe_hw *hw =
1033 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1036 PMD_INIT_FUNC_TRACE();
1038 if (hw->mac.type == ixgbe_mac_82598EB) {
1039 /* No queue level support */
1040 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1044 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1045 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1046 ctrl &= ~IXGBE_RXDCTL_VME;
1047 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1049 /* record those setting for HW strip per queue */
1050 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1054 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1056 struct ixgbe_hw *hw =
1057 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060 PMD_INIT_FUNC_TRACE();
1062 if (hw->mac.type == ixgbe_mac_82598EB) {
1063 /* No queue level supported */
1064 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1068 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1069 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1070 ctrl |= IXGBE_RXDCTL_VME;
1071 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1073 /* record those setting for HW strip per queue */
1074 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1078 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1080 struct ixgbe_hw *hw =
1081 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085 PMD_INIT_FUNC_TRACE();
1087 if (hw->mac.type == ixgbe_mac_82598EB) {
1088 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1089 ctrl &= ~IXGBE_VLNCTRL_VME;
1090 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1093 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1094 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1095 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1096 ctrl &= ~IXGBE_RXDCTL_VME;
1097 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1099 /* record those setting for HW strip per queue */
1100 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1106 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1108 struct ixgbe_hw *hw =
1109 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1113 PMD_INIT_FUNC_TRACE();
1115 if (hw->mac.type == ixgbe_mac_82598EB) {
1116 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1117 ctrl |= IXGBE_VLNCTRL_VME;
1118 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1121 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1122 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1123 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1124 ctrl |= IXGBE_RXDCTL_VME;
1125 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1127 /* record those setting for HW strip per queue */
1128 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1134 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1136 struct ixgbe_hw *hw =
1137 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1140 PMD_INIT_FUNC_TRACE();
1142 /* DMATXCTRL: Geric Double VLAN Disable */
1143 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1144 ctrl &= ~IXGBE_DMATXCTL_GDV;
1145 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1147 /* CTRL_EXT: Global Double VLAN Disable */
1148 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1149 ctrl &= ~IXGBE_EXTENDED_VLAN;
1150 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1155 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1157 struct ixgbe_hw *hw =
1158 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1161 PMD_INIT_FUNC_TRACE();
1163 /* DMATXCTRL: Geric Double VLAN Enable */
1164 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1165 ctrl |= IXGBE_DMATXCTL_GDV;
1166 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1168 /* CTRL_EXT: Global Double VLAN Enable */
1169 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1170 ctrl |= IXGBE_EXTENDED_VLAN;
1171 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1174 * VET EXT field in the EXVET register = 0x8100 by default
1175 * So no need to change. Same to VT field of DMATXCTL register
1180 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1182 if(mask & ETH_VLAN_STRIP_MASK){
1183 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1184 ixgbe_vlan_hw_strip_enable_all(dev);
1186 ixgbe_vlan_hw_strip_disable_all(dev);
1189 if(mask & ETH_VLAN_FILTER_MASK){
1190 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1191 ixgbe_vlan_hw_filter_enable(dev);
1193 ixgbe_vlan_hw_filter_disable(dev);
1196 if(mask & ETH_VLAN_EXTEND_MASK){
1197 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1198 ixgbe_vlan_hw_extend_enable(dev);
1200 ixgbe_vlan_hw_extend_disable(dev);
1205 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1207 struct ixgbe_hw *hw =
1208 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1209 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1210 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1211 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1212 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1216 ixgbe_dev_configure(struct rte_eth_dev *dev)
1218 struct ixgbe_interrupt *intr =
1219 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1221 PMD_INIT_FUNC_TRACE();
1223 /* set flag to update link status after init */
1224 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1230 * Configure device link speed and setup link.
1231 * It returns 0 on success.
1234 ixgbe_dev_start(struct rte_eth_dev *dev)
1236 struct ixgbe_hw *hw =
1237 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238 int err, link_up = 0, negotiate = 0;
1243 PMD_INIT_FUNC_TRACE();
1245 /* IXGBE devices don't support half duplex */
1246 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1247 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1248 PMD_INIT_LOG(ERR, "Invalid link_duplex (%u) for port %u\n",
1249 dev->data->dev_conf.link_duplex,
1250 dev->data->port_id);
1255 hw->adapter_stopped = FALSE;
1256 ixgbe_stop_adapter(hw);
1258 /* reinitialize adapter
1259 * this calls reset and start */
1260 status = ixgbe_pf_reset_hw(hw);
1263 hw->mac.ops.start_hw(hw);
1265 /* configure PF module if SRIOV enabled */
1266 ixgbe_pf_host_configure(dev);
1268 /* initialize transmission unit */
1269 ixgbe_dev_tx_init(dev);
1271 /* This can fail when allocating mbufs for descriptor rings */
1272 err = ixgbe_dev_rx_init(dev);
1274 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1278 ixgbe_dev_rxtx_start(dev);
1280 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1281 err = hw->mac.ops.setup_sfp(hw);
1286 /* Turn on the laser */
1287 ixgbe_enable_tx_laser(hw);
1289 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1292 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1296 switch(dev->data->dev_conf.link_speed) {
1297 case ETH_LINK_SPEED_AUTONEG:
1298 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1299 IXGBE_LINK_SPEED_82599_AUTONEG :
1300 IXGBE_LINK_SPEED_82598_AUTONEG;
1302 case ETH_LINK_SPEED_100:
1304 * Invalid for 82598 but error will be detected by
1305 * ixgbe_setup_link()
1307 speed = IXGBE_LINK_SPEED_100_FULL;
1309 case ETH_LINK_SPEED_1000:
1310 speed = IXGBE_LINK_SPEED_1GB_FULL;
1312 case ETH_LINK_SPEED_10000:
1313 speed = IXGBE_LINK_SPEED_10GB_FULL;
1316 PMD_INIT_LOG(ERR, "Invalid link_speed (%u) for port %u\n",
1317 dev->data->dev_conf.link_speed, dev->data->port_id);
1321 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1325 /* check if lsc interrupt is enabled */
1326 if (dev->data->dev_conf.intr_conf.lsc != 0)
1327 ixgbe_dev_lsc_interrupt_setup(dev);
1329 /* resume enabled intr since hw reset */
1330 ixgbe_enable_intr(dev);
1332 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1333 ETH_VLAN_EXTEND_MASK;
1334 ixgbe_vlan_offload_set(dev, mask);
1336 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1337 /* Enable vlan filtering for VMDq */
1338 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1341 /* Configure DCB hw */
1342 ixgbe_configure_dcb(dev);
1344 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1345 err = ixgbe_fdir_configure(dev);
1350 ixgbe_restore_statistics_mapping(dev);
1355 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1356 ixgbe_dev_clear_queues(dev);
1361 * Stop device: disable rx and tx functions to allow for reconfiguring.
1364 ixgbe_dev_stop(struct rte_eth_dev *dev)
1366 struct rte_eth_link link;
1367 struct ixgbe_hw *hw =
1368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370 PMD_INIT_FUNC_TRACE();
1372 /* disable interrupts */
1373 ixgbe_disable_intr(hw);
1376 ixgbe_pf_reset_hw(hw);
1377 hw->adapter_stopped = FALSE;
1380 ixgbe_stop_adapter(hw);
1382 /* Turn off the laser */
1383 ixgbe_disable_tx_laser(hw);
1385 ixgbe_dev_clear_queues(dev);
1387 /* Clear recorded link status */
1388 memset(&link, 0, sizeof(link));
1389 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1393 * Reest and stop device.
1396 ixgbe_dev_close(struct rte_eth_dev *dev)
1398 struct ixgbe_hw *hw =
1399 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1401 PMD_INIT_FUNC_TRACE();
1403 ixgbe_pf_reset_hw(hw);
1405 ixgbe_dev_stop(dev);
1406 hw->adapter_stopped = 1;
1408 ixgbe_disable_pcie_master(hw);
1410 /* reprogram the RAR[0] in case user changed it. */
1411 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1415 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1418 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1420 struct ixgbe_hw *hw =
1421 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422 struct ixgbe_hw_stats *hw_stats =
1423 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1424 uint32_t bprc, lxon, lxoff, total;
1425 uint64_t total_missed_rx, total_qbrc, total_qprc;
1428 total_missed_rx = 0;
1432 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1433 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1434 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1435 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1437 for (i = 0; i < 8; i++) {
1439 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1440 /* global total per queue */
1441 hw_stats->mpc[i] += mp;
1442 /* Running comprehensive total for stats display */
1443 total_missed_rx += hw_stats->mpc[i];
1444 if (hw->mac.type == ixgbe_mac_82598EB)
1445 hw_stats->rnbc[i] +=
1446 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1447 hw_stats->pxontxc[i] +=
1448 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1449 hw_stats->pxonrxc[i] +=
1450 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1451 hw_stats->pxofftxc[i] +=
1452 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1453 hw_stats->pxoffrxc[i] +=
1454 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1455 hw_stats->pxon2offc[i] +=
1456 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1458 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1459 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1460 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1461 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1462 hw_stats->qbrc[i] +=
1463 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1464 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1465 hw_stats->qbtc[i] +=
1466 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1467 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1469 total_qprc += hw_stats->qprc[i];
1470 total_qbrc += hw_stats->qbrc[i];
1472 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1473 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1474 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1476 /* Note that gprc counts missed packets */
1477 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1479 if (hw->mac.type != ixgbe_mac_82598EB) {
1480 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1481 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1482 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1483 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1484 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1485 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1486 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1487 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1489 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1490 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1491 /* 82598 only has a counter in the high register */
1492 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1493 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1494 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1498 * Workaround: mprc hardware is incorrectly counting
1499 * broadcasts, so for now we subtract those.
1501 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1502 hw_stats->bprc += bprc;
1503 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1504 if (hw->mac.type == ixgbe_mac_82598EB)
1505 hw_stats->mprc -= bprc;
1507 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1508 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1509 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1510 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1511 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1512 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1514 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1515 hw_stats->lxontxc += lxon;
1516 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1517 hw_stats->lxofftxc += lxoff;
1518 total = lxon + lxoff;
1520 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1521 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1522 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1523 hw_stats->gptc -= total;
1524 hw_stats->mptc -= total;
1525 hw_stats->ptc64 -= total;
1526 hw_stats->gotc -= total * ETHER_MIN_LEN;
1528 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1529 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1530 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1531 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1532 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1533 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1534 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1535 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1536 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1537 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1538 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1539 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1540 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1541 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1542 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1543 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1544 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1545 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1546 /* Only read FCOE on 82599 */
1547 if (hw->mac.type != ixgbe_mac_82598EB) {
1548 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1549 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1550 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1551 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1552 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1558 /* Fill out the rte_eth_stats statistics structure */
1559 stats->ipackets = total_qprc;
1560 stats->ibytes = total_qbrc;
1561 stats->opackets = hw_stats->gptc;
1562 stats->obytes = hw_stats->gotc;
1563 stats->imcasts = hw_stats->mprc;
1565 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1566 stats->q_ipackets[i] = hw_stats->qprc[i];
1567 stats->q_opackets[i] = hw_stats->qptc[i];
1568 stats->q_ibytes[i] = hw_stats->qbrc[i];
1569 stats->q_obytes[i] = hw_stats->qbtc[i];
1570 stats->q_errors[i] = hw_stats->qprdc[i];
1574 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1579 /* Flow Director Stats registers */
1580 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1581 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1582 stats->fdirmatch = hw_stats->fdirmatch;
1583 stats->fdirmiss = hw_stats->fdirmiss;
1587 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1589 struct ixgbe_hw_stats *stats =
1590 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1592 /* HW registers are cleared on read */
1593 ixgbe_dev_stats_get(dev, NULL);
1595 /* Reset software totals */
1596 memset(stats, 0, sizeof(*stats));
1600 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1602 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1603 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1604 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1606 /* Good Rx packet, include VF loopback */
1607 UPDATE_VF_STAT(IXGBE_VFGPRC,
1608 hw_stats->last_vfgprc, hw_stats->vfgprc);
1610 /* Good Rx octets, include VF loopback */
1611 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1612 hw_stats->last_vfgorc, hw_stats->vfgorc);
1614 /* Good Tx packet, include VF loopback */
1615 UPDATE_VF_STAT(IXGBE_VFGPTC,
1616 hw_stats->last_vfgptc, hw_stats->vfgptc);
1618 /* Good Tx octets, include VF loopback */
1619 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1620 hw_stats->last_vfgotc, hw_stats->vfgotc);
1622 /* Rx Multicst Packet */
1623 UPDATE_VF_STAT(IXGBE_VFMPRC,
1624 hw_stats->last_vfmprc, hw_stats->vfmprc);
1629 memset(stats, 0, sizeof(*stats));
1630 stats->ipackets = hw_stats->vfgprc;
1631 stats->ibytes = hw_stats->vfgorc;
1632 stats->opackets = hw_stats->vfgptc;
1633 stats->obytes = hw_stats->vfgotc;
1634 stats->imcasts = hw_stats->vfmprc;
1638 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1640 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1641 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1643 /* Sync HW register to the last stats */
1644 ixgbevf_dev_stats_get(dev, NULL);
1646 /* reset HW current stats*/
1647 hw_stats->vfgprc = 0;
1648 hw_stats->vfgorc = 0;
1649 hw_stats->vfgptc = 0;
1650 hw_stats->vfgotc = 0;
1651 hw_stats->vfmprc = 0;
1656 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1658 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1660 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1661 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1662 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1663 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1664 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1665 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1666 dev_info->max_vfs = dev->pci_dev->max_vfs;
1667 if (hw->mac.type == ixgbe_mac_82598EB)
1668 dev_info->max_vmdq_pools = ETH_16_POOLS;
1670 dev_info->max_vmdq_pools = ETH_64_POOLS;
1673 /* return 0 means link status changed, -1 means not changed */
1675 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1677 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1678 struct rte_eth_link link, old;
1679 ixgbe_link_speed link_speed;
1683 link.link_status = 0;
1684 link.link_speed = 0;
1685 link.link_duplex = 0;
1686 memset(&old, 0, sizeof(old));
1687 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1689 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1690 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1691 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1693 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1695 link.link_speed = ETH_LINK_SPEED_100;
1696 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1697 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1698 if (link.link_status == old.link_status)
1704 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1705 if (link.link_status == old.link_status)
1709 link.link_status = 1;
1710 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1712 switch (link_speed) {
1714 case IXGBE_LINK_SPEED_UNKNOWN:
1715 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1716 link.link_speed = ETH_LINK_SPEED_100;
1719 case IXGBE_LINK_SPEED_100_FULL:
1720 link.link_speed = ETH_LINK_SPEED_100;
1723 case IXGBE_LINK_SPEED_1GB_FULL:
1724 link.link_speed = ETH_LINK_SPEED_1000;
1727 case IXGBE_LINK_SPEED_10GB_FULL:
1728 link.link_speed = ETH_LINK_SPEED_10000;
1731 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1733 if (link.link_status == old.link_status)
1740 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
1742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1745 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1746 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1747 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1751 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
1753 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1756 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1757 fctrl &= (~IXGBE_FCTRL_UPE);
1758 if (dev->data->all_multicast == 1)
1759 fctrl |= IXGBE_FCTRL_MPE;
1761 fctrl &= (~IXGBE_FCTRL_MPE);
1762 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1766 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
1768 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1772 fctrl |= IXGBE_FCTRL_MPE;
1773 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1777 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
1779 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782 if (dev->data->promiscuous == 1)
1783 return; /* must remain in all_multicast mode */
1785 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1786 fctrl &= (~IXGBE_FCTRL_MPE);
1787 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1791 * It clears the interrupt causes and enables the interrupt.
1792 * It will be called once only during nic initialized.
1795 * Pointer to struct rte_eth_dev.
1798 * - On success, zero.
1799 * - On failure, a negative value.
1802 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
1804 struct ixgbe_interrupt *intr =
1805 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1807 ixgbe_dev_link_status_print(dev);
1808 intr->mask |= IXGBE_EICR_LSC;
1814 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
1817 * Pointer to struct rte_eth_dev.
1820 * - On success, zero.
1821 * - On failure, a negative value.
1824 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
1827 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828 struct ixgbe_interrupt *intr =
1829 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1831 /* clear all cause mask */
1832 ixgbe_disable_intr(hw);
1834 /* read-on-clear nic registers here */
1835 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1836 PMD_DRV_LOG(INFO, "eicr %x", eicr);
1839 if (eicr & IXGBE_EICR_LSC) {
1840 /* set flag for async link update */
1841 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1844 if (eicr & IXGBE_EICR_MAILBOX)
1845 intr->flags |= IXGBE_FLAG_MAILBOX;
1851 * It gets and then prints the link status.
1854 * Pointer to struct rte_eth_dev.
1857 * - On success, zero.
1858 * - On failure, a negative value.
1861 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
1863 struct rte_eth_link link;
1865 memset(&link, 0, sizeof(link));
1866 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1867 if (link.link_status) {
1868 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
1869 (int)(dev->data->port_id),
1870 (unsigned)link.link_speed,
1871 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1872 "full-duplex" : "half-duplex");
1874 PMD_INIT_LOG(INFO, " Port %d: Link Down",
1875 (int)(dev->data->port_id));
1877 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1878 dev->pci_dev->addr.domain,
1879 dev->pci_dev->addr.bus,
1880 dev->pci_dev->addr.devid,
1881 dev->pci_dev->addr.function);
1885 * It executes link_update after knowing an interrupt occured.
1888 * Pointer to struct rte_eth_dev.
1891 * - On success, zero.
1892 * - On failure, a negative value.
1895 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
1897 struct ixgbe_interrupt *intr =
1898 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1900 struct rte_eth_link link;
1901 int intr_enable_delay = false;
1903 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
1905 if (intr->flags & IXGBE_FLAG_MAILBOX) {
1906 ixgbe_pf_mbx_process(dev);
1907 intr->flags &= ~IXGBE_FLAG_MAILBOX;
1910 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1911 /* get the link status before link update, for predicting later */
1912 memset(&link, 0, sizeof(link));
1913 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
1915 ixgbe_dev_link_update(dev, 0);
1918 if (!link.link_status)
1919 /* handle it 1 sec later, wait it being stable */
1920 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
1921 /* likely to down */
1923 /* handle it 4 sec later, wait it being stable */
1924 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
1926 ixgbe_dev_link_status_print(dev);
1928 intr_enable_delay = true;
1931 if (intr_enable_delay) {
1932 if (rte_eal_alarm_set(timeout * 1000,
1933 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
1934 PMD_DRV_LOG(ERR, "Error setting alarm");
1936 PMD_DRV_LOG(DEBUG, "enable intr immediately");
1937 ixgbe_enable_intr(dev);
1938 rte_intr_enable(&(dev->pci_dev->intr_handle));
1946 * Interrupt handler which shall be registered for alarm callback for delayed
1947 * handling specific interrupt to wait for the stable nic state. As the
1948 * NIC interrupt state is not stable for ixgbe after link is just down,
1949 * it needs to wait 4 seconds to get the stable status.
1952 * Pointer to interrupt handle.
1954 * The address of parameter (struct rte_eth_dev *) regsitered before.
1960 ixgbe_dev_interrupt_delayed_handler(void *param)
1962 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1963 struct ixgbe_interrupt *intr =
1964 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1965 struct ixgbe_hw *hw =
1966 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1969 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1970 if (eicr & IXGBE_EICR_MAILBOX)
1971 ixgbe_pf_mbx_process(dev);
1973 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
1974 ixgbe_dev_link_update(dev, 0);
1975 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
1976 ixgbe_dev_link_status_print(dev);
1977 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1980 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
1981 ixgbe_enable_intr(dev);
1982 rte_intr_enable(&(dev->pci_dev->intr_handle));
1986 * Interrupt handler triggered by NIC for handling
1987 * specific interrupt.
1990 * Pointer to interrupt handle.
1992 * The address of parameter (struct rte_eth_dev *) regsitered before.
1998 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2001 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2002 ixgbe_dev_interrupt_get_status(dev);
2003 ixgbe_dev_interrupt_action(dev);
2007 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2009 struct ixgbe_hw *hw;
2011 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2016 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2018 struct ixgbe_hw *hw;
2020 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2025 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2027 struct ixgbe_hw *hw;
2029 uint32_t rx_buf_size;
2030 uint32_t max_high_water;
2032 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2039 PMD_INIT_FUNC_TRACE();
2041 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2042 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2043 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2046 * At least reserve one Ethernet frame for watermark
2047 * high_water/low_water in kilo bytes for ixgbe
2049 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2050 if ((fc_conf->high_water > max_high_water) ||
2051 (fc_conf->high_water < fc_conf->low_water)) {
2052 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2053 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2057 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2058 hw->fc.pause_time = fc_conf->pause_time;
2059 hw->fc.high_water[0] = fc_conf->high_water;
2060 hw->fc.low_water[0] = fc_conf->low_water;
2061 hw->fc.send_xon = fc_conf->send_xon;
2063 err = ixgbe_fc_enable(hw);
2065 /* Not negotiated is not an error case */
2066 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2068 /* check if we want to forward MAC frames - driver doesn't have native
2069 * capability to do that, so we'll write the registers ourselves */
2071 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2073 /* set or clear MFLCN.PMCF bit depending on configuration */
2074 if (fc_conf->mac_ctrl_frame_fwd != 0)
2075 mflcn |= IXGBE_MFLCN_PMCF;
2077 mflcn &= ~IXGBE_MFLCN_PMCF;
2079 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2080 IXGBE_WRITE_FLUSH(hw);
2085 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2090 * ixgbe_pfc_enable_generic - Enable flow control
2091 * @hw: pointer to hardware structure
2092 * @tc_num: traffic class number
2093 * Enable flow control according to the current settings.
2096 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2099 uint32_t mflcn_reg, fccfg_reg;
2101 uint32_t fcrtl, fcrth;
2105 /* Validate the water mark configuration */
2106 if (!hw->fc.pause_time) {
2107 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2111 /* Low water mark of zero causes XOFF floods */
2112 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2113 /* High/Low water can not be 0 */
2114 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2115 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2116 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2120 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2121 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2122 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2126 /* Negotiate the fc mode to use */
2127 ixgbe_fc_autoneg(hw);
2129 /* Disable any previous flow control settings */
2130 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2131 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2133 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2134 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2136 switch (hw->fc.current_mode) {
2139 * If the count of enabled RX Priority Flow control >1,
2140 * and the TX pause can not be disabled
2143 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2144 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2145 if (reg & IXGBE_FCRTH_FCEN)
2149 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2151 case ixgbe_fc_rx_pause:
2153 * Rx Flow control is enabled and Tx Flow control is
2154 * disabled by software override. Since there really
2155 * isn't a way to advertise that we are capable of RX
2156 * Pause ONLY, we will advertise that we support both
2157 * symmetric and asymmetric Rx PAUSE. Later, we will
2158 * disable the adapter's ability to send PAUSE frames.
2160 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2162 * If the count of enabled RX Priority Flow control >1,
2163 * and the TX pause can not be disabled
2166 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2167 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2168 if (reg & IXGBE_FCRTH_FCEN)
2172 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2174 case ixgbe_fc_tx_pause:
2176 * Tx Flow control is enabled, and Rx Flow control is
2177 * disabled by software override.
2179 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2182 /* Flow control (both Rx and Tx) is enabled by SW override. */
2183 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2184 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2187 DEBUGOUT("Flow control param set incorrectly\n");
2188 ret_val = IXGBE_ERR_CONFIG;
2193 /* Set 802.3x based flow control settings. */
2194 mflcn_reg |= IXGBE_MFLCN_DPF;
2195 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2196 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2198 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2199 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2200 hw->fc.high_water[tc_num]) {
2201 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2202 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2203 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2205 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2207 * In order to prevent Tx hangs when the internal Tx
2208 * switch is enabled we must set the high water mark
2209 * to the maximum FCRTH value. This allows the Tx
2210 * switch to function even under heavy Rx workloads.
2212 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2214 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2216 /* Configure pause time (2 TCs per register) */
2217 reg = hw->fc.pause_time * 0x00010001;
2218 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2219 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2221 /* Configure flow control refresh threshold value */
2222 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2229 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2231 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2234 if(hw->mac.type != ixgbe_mac_82598EB) {
2235 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2241 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2244 uint32_t rx_buf_size;
2245 uint32_t max_high_water;
2247 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2248 struct ixgbe_hw *hw =
2249 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2250 struct ixgbe_dcb_config *dcb_config =
2251 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2253 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2260 PMD_INIT_FUNC_TRACE();
2262 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2263 tc_num = map[pfc_conf->priority];
2264 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2265 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2267 * At least reserve one Ethernet frame for watermark
2268 * high_water/low_water in kilo bytes for ixgbe
2270 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2271 if ((pfc_conf->fc.high_water > max_high_water) ||
2272 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2273 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2274 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2278 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2279 hw->fc.pause_time = pfc_conf->fc.pause_time;
2280 hw->fc.send_xon = pfc_conf->fc.send_xon;
2281 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2282 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2284 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2286 /* Not negotiated is not an error case */
2287 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2290 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2295 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2296 struct rte_eth_rss_reta *reta_conf)
2300 struct ixgbe_hw *hw =
2301 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2303 PMD_INIT_FUNC_TRACE();
2305 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2306 * 128-entries in 32 registers
2308 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2309 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2310 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2312 mask = (uint8_t)((reta_conf->mask_hi >>
2313 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2317 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2319 for (j = 0; j < 4; j++) {
2320 if (mask & (0x1 << j)) {
2322 reta &= ~(0xFF << 8 * j);
2323 reta |= reta_conf->reta[i + j] << 8*j;
2326 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2334 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2335 struct rte_eth_rss_reta *reta_conf)
2339 struct ixgbe_hw *hw =
2340 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342 PMD_INIT_FUNC_TRACE();
2344 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2345 * 128-entries in 32 registers
2347 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2348 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2349 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2351 mask = (uint8_t)((reta_conf->mask_hi >>
2352 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2355 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2356 for (j = 0; j < 4; j++) {
2357 if (mask & (0x1 << j))
2358 reta_conf->reta[i + j] =
2359 (uint8_t)((reta >> 8 * j) & 0xFF);
2368 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2369 uint32_t index, uint32_t pool)
2371 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372 uint32_t enable_addr = 1;
2374 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2378 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2380 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2382 ixgbe_clear_rar(hw, index);
2386 * Virtual Function operations
2389 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2391 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2393 /* Clear interrupt mask to stop from interrupts being generated */
2394 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2396 IXGBE_WRITE_FLUSH(hw);
2400 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2402 struct rte_eth_conf* conf = &dev->data->dev_conf;
2404 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2405 dev->data->port_id);
2408 * VF has no ability to enable/disable HW CRC
2409 * Keep the persistent behavior the same as Host PF
2411 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2412 if (!conf->rxmode.hw_strip_crc) {
2413 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2414 conf->rxmode.hw_strip_crc = 1;
2417 if (conf->rxmode.hw_strip_crc) {
2418 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2419 conf->rxmode.hw_strip_crc = 0;
2427 ixgbevf_dev_start(struct rte_eth_dev *dev)
2429 struct ixgbe_hw *hw =
2430 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2433 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2435 hw->mac.ops.reset_hw(hw);
2437 ixgbevf_dev_tx_init(dev);
2439 /* This can fail when allocating mbufs for descriptor rings */
2440 err = ixgbevf_dev_rx_init(dev);
2442 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2443 ixgbe_dev_clear_queues(dev);
2448 ixgbevf_set_vfta_all(dev,1);
2451 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2452 ETH_VLAN_EXTEND_MASK;
2453 ixgbevf_vlan_offload_set(dev, mask);
2455 ixgbevf_dev_rxtx_start(dev);
2461 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2463 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2467 hw->adapter_stopped = TRUE;
2468 ixgbe_stop_adapter(hw);
2471 * Clear what we set, but we still keep shadow_vfta to
2472 * restore after device starts
2474 ixgbevf_set_vfta_all(dev,0);
2476 ixgbe_dev_clear_queues(dev);
2480 ixgbevf_dev_close(struct rte_eth_dev *dev)
2482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2484 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2488 ixgbevf_dev_stop(dev);
2490 /* reprogram the RAR[0] in case user changed it. */
2491 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2494 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2496 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2497 struct ixgbe_vfta * shadow_vfta =
2498 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2499 int i = 0, j = 0, vfta = 0, mask = 1;
2501 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2502 vfta = shadow_vfta->vfta[i];
2505 for (j = 0; j < 32; j++){
2507 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2516 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2518 struct ixgbe_hw *hw =
2519 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2520 struct ixgbe_vfta * shadow_vfta =
2521 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2522 uint32_t vid_idx = 0;
2523 uint32_t vid_bit = 0;
2526 PMD_INIT_FUNC_TRACE();
2528 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2529 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2531 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2534 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2535 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2537 /* Save what we set and retore it after device reset */
2539 shadow_vfta->vfta[vid_idx] |= vid_bit;
2541 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2547 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2549 struct ixgbe_hw *hw =
2550 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2553 PMD_INIT_FUNC_TRACE();
2555 if(queue >= hw->mac.max_rx_queues)
2558 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2560 ctrl |= IXGBE_RXDCTL_VME;
2562 ctrl &= ~IXGBE_RXDCTL_VME;
2563 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2565 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2569 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2571 struct ixgbe_hw *hw =
2572 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 /* VF function only support hw strip feature, others are not support */
2577 if(mask & ETH_VLAN_STRIP_MASK){
2578 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2580 for(i=0; i < hw->mac.max_rx_queues; i++)
2581 ixgbevf_vlan_strip_queue_set(dev,i,on);
2586 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2590 /* we only need to do this if VMDq is enabled */
2591 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2592 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2593 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2601 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2603 uint32_t vector = 0;
2604 switch (hw->mac.mc_filter_type) {
2605 case 0: /* use bits [47:36] of the address */
2606 vector = ((uc_addr->addr_bytes[4] >> 4) |
2607 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2609 case 1: /* use bits [46:35] of the address */
2610 vector = ((uc_addr->addr_bytes[4] >> 3) |
2611 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2613 case 2: /* use bits [45:34] of the address */
2614 vector = ((uc_addr->addr_bytes[4] >> 2) |
2615 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2617 case 3: /* use bits [43:32] of the address */
2618 vector = ((uc_addr->addr_bytes[4]) |
2619 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2621 default: /* Invalid mc_filter_type */
2625 /* vector can only be 12-bits or boundary will be exceeded */
2631 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2639 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2640 const uint32_t ixgbe_uta_bit_shift = 5;
2641 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2642 const uint32_t bit1 = 0x1;
2644 struct ixgbe_hw *hw =
2645 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646 struct ixgbe_uta_info *uta_info =
2647 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2649 /* The UTA table only exists on 82599 hardware and newer */
2650 if (hw->mac.type < ixgbe_mac_82599EB)
2653 vector = ixgbe_uta_vector(hw,mac_addr);
2654 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2655 uta_shift = vector & ixgbe_uta_bit_mask;
2657 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2661 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2663 uta_info->uta_in_use++;
2664 reg_val |= (bit1 << uta_shift);
2665 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2667 uta_info->uta_in_use--;
2668 reg_val &= ~(bit1 << uta_shift);
2669 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2672 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2674 if (uta_info->uta_in_use > 0)
2675 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2676 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2678 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2684 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2687 struct ixgbe_hw *hw =
2688 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 struct ixgbe_uta_info *uta_info =
2690 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2692 /* The UTA table only exists on 82599 hardware and newer */
2693 if (hw->mac.type < ixgbe_mac_82599EB)
2697 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2698 uta_info->uta_shadow[i] = ~0;
2699 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2702 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2703 uta_info->uta_shadow[i] = 0;
2704 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2711 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2712 uint16_t rx_mask, uint8_t on)
2716 struct ixgbe_hw *hw =
2717 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2718 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2720 if (hw->mac.type == ixgbe_mac_82598EB) {
2721 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2722 " on 82599 hardware and newer\n");
2725 if (ixgbe_vmdq_mode_check(hw) < 0)
2728 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2729 val |= IXGBE_VMOLR_AUPE;
2730 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2731 val |= IXGBE_VMOLR_ROMPE;
2732 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
2733 val |= IXGBE_VMOLR_ROPE;
2734 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
2735 val |= IXGBE_VMOLR_BAM;
2736 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
2737 val |= IXGBE_VMOLR_MPE;
2744 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
2750 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2754 const uint8_t bit1 = 0x1;
2756 struct ixgbe_hw *hw =
2757 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2759 if (ixgbe_vmdq_mode_check(hw) < 0)
2762 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
2763 reg = IXGBE_READ_REG(hw, addr);
2771 IXGBE_WRITE_REG(hw, addr,reg);
2777 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
2781 const uint8_t bit1 = 0x1;
2783 struct ixgbe_hw *hw =
2784 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2786 if (ixgbe_vmdq_mode_check(hw) < 0)
2789 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
2790 reg = IXGBE_READ_REG(hw, addr);
2798 IXGBE_WRITE_REG(hw, addr,reg);
2804 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
2805 uint64_t pool_mask, uint8_t vlan_on)
2809 struct ixgbe_hw *hw =
2810 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 if (ixgbe_vmdq_mode_check(hw) < 0)
2814 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
2815 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
2816 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
2825 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
2826 struct rte_eth_vmdq_mirror_conf *mirror_conf,
2827 uint8_t rule_id, uint8_t on)
2829 uint32_t mr_ctl,vlvf;
2830 uint32_t mp_lsb = 0;
2831 uint32_t mv_msb = 0;
2832 uint32_t mv_lsb = 0;
2833 uint32_t mp_msb = 0;
2836 uint64_t vlan_mask = 0;
2838 const uint8_t pool_mask_offset = 32;
2839 const uint8_t vlan_mask_offset = 32;
2840 const uint8_t dst_pool_offset = 8;
2841 const uint8_t rule_mr_offset = 4;
2842 const uint8_t mirror_rule_mask= 0x0F;
2844 struct ixgbe_mirror_info *mr_info =
2845 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2846 struct ixgbe_hw *hw =
2847 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2849 if (ixgbe_vmdq_mode_check(hw) < 0)
2852 /* Check if vlan mask is valid */
2853 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
2854 if (mirror_conf->vlan.vlan_mask == 0)
2858 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
2859 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2860 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
2861 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
2862 /* search vlan id related pool vlan filter index */
2863 reg_index = ixgbe_find_vlvf_slot(hw,
2864 mirror_conf->vlan.vlan_id[i]);
2867 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
2868 if ((vlvf & IXGBE_VLVF_VIEN) &&
2869 ((vlvf & IXGBE_VLVF_VLANID_MASK)
2870 == mirror_conf->vlan.vlan_id[i]))
2871 vlan_mask |= (1ULL << reg_index);
2878 mv_lsb = vlan_mask & 0xFFFFFFFF;
2879 mv_msb = vlan_mask >> vlan_mask_offset;
2881 mr_info->mr_conf[rule_id].vlan.vlan_mask =
2882 mirror_conf->vlan.vlan_mask;
2883 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
2884 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
2885 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
2886 mirror_conf->vlan.vlan_id[i];
2891 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
2892 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
2893 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
2898 * if enable pool mirror, write related pool mask register,if disable
2899 * pool mirror, clear PFMRVM register
2901 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2903 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
2904 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
2905 mr_info->mr_conf[rule_id].pool_mask =
2906 mirror_conf->pool_mask;
2911 mr_info->mr_conf[rule_id].pool_mask = 0;
2915 /* read mirror control register and recalculate it */
2916 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
2919 mr_ctl |= mirror_conf->rule_type_mask;
2920 mr_ctl &= mirror_rule_mask;
2921 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
2923 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
2925 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
2926 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
2928 /* write mirrror control register */
2929 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2931 /* write pool mirrror control register */
2932 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
2933 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
2934 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
2937 /* write VLAN mirrror control register */
2938 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
2939 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
2940 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
2948 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
2951 uint32_t lsb_val = 0;
2952 uint32_t msb_val = 0;
2953 const uint8_t rule_mr_offset = 4;
2955 struct ixgbe_hw *hw =
2956 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2957 struct ixgbe_mirror_info *mr_info =
2958 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
2960 if (ixgbe_vmdq_mode_check(hw) < 0)
2963 memset(&mr_info->mr_conf[rule_id], 0,
2964 sizeof(struct rte_eth_vmdq_mirror_conf));
2966 /* clear PFVMCTL register */
2967 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
2969 /* clear pool mask register */
2970 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
2971 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
2973 /* clear vlan mask register */
2974 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
2975 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);