4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
100 struct rte_eth_dev *eth_dev);
101 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
102 static int ixgbe_dev_start(struct rte_eth_dev *dev);
103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
104 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
105 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
112 int wait_to_complete);
113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
114 struct rte_eth_stats *stats);
115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
121 struct rte_eth_dev_info *dev_info);
122 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
123 uint16_t vlan_id, int on);
124 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
125 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
126 uint16_t queue, bool on);
127 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
129 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
130 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
131 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
132 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
133 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
135 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
136 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
137 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
138 struct rte_eth_fc_conf *fc_conf);
139 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
140 struct rte_eth_pfc_conf *pfc_conf);
141 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
142 struct rte_eth_rss_reta *reta_conf);
143 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
144 struct rte_eth_rss_reta *reta_conf);
145 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
146 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
147 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
148 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
149 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
151 static void ixgbe_dev_interrupt_delayed_handler(void *param);
152 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
153 uint32_t index, uint32_t pool);
154 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
155 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
157 /* For Virtual Function support */
158 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
159 struct rte_eth_dev *eth_dev);
160 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
161 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
162 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
163 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
164 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
165 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
166 struct rte_eth_stats *stats);
167 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
168 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
169 uint16_t vlan_id, int on);
170 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
171 uint16_t queue, int on);
172 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
173 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
175 /* For Eth VMDQ APIs support */
176 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
177 ether_addr* mac_addr,uint8_t on);
178 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
179 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
180 uint16_t rx_mask, uint8_t on);
181 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
182 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
183 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
184 uint64_t pool_mask,uint8_t vlan_on);
185 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
186 struct rte_eth_vmdq_mirror_conf *mirror_conf,
187 uint8_t rule_id, uint8_t on);
188 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
191 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
192 uint16_t queue_idx, uint16_t tx_rate);
193 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
194 uint16_t tx_rate, uint64_t q_msk);
196 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
197 struct ether_addr *mac_addr,
198 uint32_t index, uint32_t pool);
199 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
200 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
201 struct rte_syn_filter *filter, uint16_t rx_queue);
202 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
203 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
204 struct rte_syn_filter *filter, uint16_t *rx_queue);
205 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
206 struct rte_ethertype_filter *filter, uint16_t rx_queue);
207 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
209 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
210 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
211 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
212 struct rte_5tuple_filter *filter, uint16_t rx_queue);
213 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
215 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
216 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
219 * Define VF Stats MACRO for Non "cleared on read" register
221 #define UPDATE_VF_STAT(reg, last, cur) \
223 u32 latest = IXGBE_READ_REG(hw, reg); \
224 cur += latest - last; \
228 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
230 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
231 u64 new_msb = IXGBE_READ_REG(hw, msb); \
232 u64 latest = ((new_msb << 32) | new_lsb); \
233 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
237 #define IXGBE_SET_HWSTRIP(h, q) do{\
238 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
239 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
240 (h)->bitmap[idx] |= 1 << bit;\
243 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
244 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
245 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
246 (h)->bitmap[idx] &= ~(1 << bit);\
249 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
250 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
251 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
252 (r) = (h)->bitmap[idx] >> bit & 1;\
256 * The set of PCI devices this driver supports
258 static struct rte_pci_id pci_id_ixgbe_map[] = {
260 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
261 #include "rte_pci_dev_ids.h"
263 { .vendor_id = 0, /* sentinel */ },
268 * The set of PCI devices this driver supports (for 82599 VF)
270 static struct rte_pci_id pci_id_ixgbevf_map[] = {
272 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
273 #include "rte_pci_dev_ids.h"
274 { .vendor_id = 0, /* sentinel */ },
278 static struct eth_dev_ops ixgbe_eth_dev_ops = {
279 .dev_configure = ixgbe_dev_configure,
280 .dev_start = ixgbe_dev_start,
281 .dev_stop = ixgbe_dev_stop,
282 .dev_set_link_up = ixgbe_dev_set_link_up,
283 .dev_set_link_down = ixgbe_dev_set_link_down,
284 .dev_close = ixgbe_dev_close,
285 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
286 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
287 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
288 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
289 .link_update = ixgbe_dev_link_update,
290 .stats_get = ixgbe_dev_stats_get,
291 .stats_reset = ixgbe_dev_stats_reset,
292 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
293 .dev_infos_get = ixgbe_dev_info_get,
294 .vlan_filter_set = ixgbe_vlan_filter_set,
295 .vlan_tpid_set = ixgbe_vlan_tpid_set,
296 .vlan_offload_set = ixgbe_vlan_offload_set,
297 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
298 .rx_queue_start = ixgbe_dev_rx_queue_start,
299 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
300 .tx_queue_start = ixgbe_dev_tx_queue_start,
301 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
302 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
303 .rx_queue_release = ixgbe_dev_rx_queue_release,
304 .rx_queue_count = ixgbe_dev_rx_queue_count,
305 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
306 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
307 .tx_queue_release = ixgbe_dev_tx_queue_release,
308 .dev_led_on = ixgbe_dev_led_on,
309 .dev_led_off = ixgbe_dev_led_off,
310 .flow_ctrl_set = ixgbe_flow_ctrl_set,
311 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
312 .mac_addr_add = ixgbe_add_rar,
313 .mac_addr_remove = ixgbe_remove_rar,
314 .uc_hash_table_set = ixgbe_uc_hash_table_set,
315 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
316 .mirror_rule_set = ixgbe_mirror_rule_set,
317 .mirror_rule_reset = ixgbe_mirror_rule_reset,
318 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
319 .set_vf_rx = ixgbe_set_pool_rx,
320 .set_vf_tx = ixgbe_set_pool_tx,
321 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
322 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
323 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
324 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
325 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
326 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
327 .fdir_infos_get = ixgbe_fdir_info_get,
328 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
329 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
330 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
331 .fdir_set_masks = ixgbe_fdir_set_masks,
332 .reta_update = ixgbe_dev_rss_reta_update,
333 .reta_query = ixgbe_dev_rss_reta_query,
334 #ifdef RTE_NIC_BYPASS
335 .bypass_init = ixgbe_bypass_init,
336 .bypass_state_set = ixgbe_bypass_state_store,
337 .bypass_state_show = ixgbe_bypass_state_show,
338 .bypass_event_set = ixgbe_bypass_event_store,
339 .bypass_event_show = ixgbe_bypass_event_show,
340 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
341 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
342 .bypass_ver_show = ixgbe_bypass_ver_show,
343 .bypass_wd_reset = ixgbe_bypass_wd_reset,
344 #endif /* RTE_NIC_BYPASS */
345 .rss_hash_update = ixgbe_dev_rss_hash_update,
346 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
347 .add_syn_filter = ixgbe_add_syn_filter,
348 .remove_syn_filter = ixgbe_remove_syn_filter,
349 .get_syn_filter = ixgbe_get_syn_filter,
350 .add_ethertype_filter = ixgbe_add_ethertype_filter,
351 .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
352 .get_ethertype_filter = ixgbe_get_ethertype_filter,
353 .add_5tuple_filter = ixgbe_add_5tuple_filter,
354 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
355 .get_5tuple_filter = ixgbe_get_5tuple_filter,
359 * dev_ops for virtual function, bare necessities for basic vf
360 * operation have been implemented
362 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
364 .dev_configure = ixgbevf_dev_configure,
365 .dev_start = ixgbevf_dev_start,
366 .dev_stop = ixgbevf_dev_stop,
367 .link_update = ixgbe_dev_link_update,
368 .stats_get = ixgbevf_dev_stats_get,
369 .stats_reset = ixgbevf_dev_stats_reset,
370 .dev_close = ixgbevf_dev_close,
371 .dev_infos_get = ixgbe_dev_info_get,
372 .vlan_filter_set = ixgbevf_vlan_filter_set,
373 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
374 .vlan_offload_set = ixgbevf_vlan_offload_set,
375 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
376 .rx_queue_release = ixgbe_dev_rx_queue_release,
377 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
378 .tx_queue_release = ixgbe_dev_tx_queue_release,
379 .mac_addr_add = ixgbevf_add_mac_addr,
380 .mac_addr_remove = ixgbevf_remove_mac_addr,
384 * Atomically reads the link status information from global
385 * structure rte_eth_dev.
388 * - Pointer to the structure rte_eth_dev to read from.
389 * - Pointer to the buffer to be saved with the link status.
392 * - On success, zero.
393 * - On failure, negative value.
396 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
397 struct rte_eth_link *link)
399 struct rte_eth_link *dst = link;
400 struct rte_eth_link *src = &(dev->data->dev_link);
402 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
403 *(uint64_t *)src) == 0)
410 * Atomically writes the link status information into global
411 * structure rte_eth_dev.
414 * - Pointer to the structure rte_eth_dev to read from.
415 * - Pointer to the buffer to be saved with the link status.
418 * - On success, zero.
419 * - On failure, negative value.
422 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
423 struct rte_eth_link *link)
425 struct rte_eth_link *dst = &(dev->data->dev_link);
426 struct rte_eth_link *src = link;
428 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
429 *(uint64_t *)src) == 0)
436 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
439 ixgbe_is_sfp(struct ixgbe_hw *hw)
441 switch (hw->phy.type) {
442 case ixgbe_phy_sfp_avago:
443 case ixgbe_phy_sfp_ftl:
444 case ixgbe_phy_sfp_intel:
445 case ixgbe_phy_sfp_unknown:
446 case ixgbe_phy_sfp_passive_tyco:
447 case ixgbe_phy_sfp_passive_unknown:
454 static inline int32_t
455 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
460 status = ixgbe_reset_hw(hw);
462 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
463 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
464 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
465 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
466 IXGBE_WRITE_FLUSH(hw);
472 ixgbe_enable_intr(struct rte_eth_dev *dev)
474 struct ixgbe_interrupt *intr =
475 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
476 struct ixgbe_hw *hw =
477 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
479 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
480 IXGBE_WRITE_FLUSH(hw);
484 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
487 ixgbe_disable_intr(struct ixgbe_hw *hw)
489 PMD_INIT_FUNC_TRACE();
491 if (hw->mac.type == ixgbe_mac_82598EB) {
492 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
494 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
495 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
496 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
498 IXGBE_WRITE_FLUSH(hw);
502 * This function resets queue statistics mapping registers.
503 * From Niantic datasheet, Initialization of Statistics section:
504 * "...if software requires the queue counters, the RQSMR and TQSM registers
505 * must be re-programmed following a device reset.
508 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
512 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
513 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
514 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
520 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
525 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
526 #define NB_QMAP_FIELDS_PER_QSM_REG 4
527 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
529 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
530 struct ixgbe_stat_mapping_registers *stat_mappings =
531 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
532 uint32_t qsmr_mask = 0;
533 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
537 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
540 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d\n",
541 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx);
543 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
544 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
545 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded\n");
548 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
550 /* Now clear any previous stat_idx set */
551 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
553 stat_mappings->tqsm[n] &= ~clearing_mask;
555 stat_mappings->rqsmr[n] &= ~clearing_mask;
557 q_map = (uint32_t)stat_idx;
558 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
559 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
561 stat_mappings->tqsm[n] |= qsmr_mask;
563 stat_mappings->rqsmr[n] |= qsmr_mask;
565 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d\n"
567 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX", queue_id, stat_idx,
568 is_rx ? "RQSMR" : "TQSM",n, is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
570 /* Now write the mapping in the appropriate register */
572 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d\n",
573 stat_mappings->rqsmr[n], n);
574 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
577 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d\n",
578 stat_mappings->tqsm[n], n);
579 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
585 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
587 struct ixgbe_stat_mapping_registers *stat_mappings =
588 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
589 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
592 /* write whatever was in stat mapping table to the NIC */
593 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
595 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
598 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
603 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
606 struct ixgbe_dcb_tc_config *tc;
607 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
609 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
610 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
611 for (i = 0; i < dcb_max_tc; i++) {
612 tc = &dcb_config->tc_config[i];
613 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
614 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
615 (uint8_t)(100/dcb_max_tc + (i & 1));
616 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
617 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
618 (uint8_t)(100/dcb_max_tc + (i & 1));
619 tc->pfc = ixgbe_dcb_pfc_disabled;
622 /* Initialize default user to priority mapping, UPx->TC0 */
623 tc = &dcb_config->tc_config[0];
624 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
625 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
626 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
627 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
628 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
630 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
631 dcb_config->pfc_mode_enable = false;
632 dcb_config->vt_mode = true;
633 dcb_config->round_robin_enable = false;
634 /* support all DCB capabilities in 82599 */
635 dcb_config->support.capabilities = 0xFF;
637 /*we only support 4 Tcs for X540*/
638 if (hw->mac.type == ixgbe_mac_X540) {
639 dcb_config->num_tcs.pg_tcs = 4;
640 dcb_config->num_tcs.pfc_tcs = 4;
645 * Ensure that all locks are released before first NVM or PHY access
648 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
653 * Phy lock should not fail in this early stage. If this is the case,
654 * it is due to an improper exit of the application.
655 * So force the release of the faulty lock. Release of common lock
656 * is done automatically by swfw_sync function.
658 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
659 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
660 DEBUGOUT1("SWFW phy%d lock released", hw->bus.func);
662 ixgbe_release_swfw_semaphore(hw, mask);
665 * These ones are more tricky since they are common to all ports; but
666 * swfw_sync retries last long enough (1s) to be almost sure that if
667 * lock can not be taken it is due to an improper lock of the
670 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
671 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
672 DEBUGOUT("SWFW common locks released");
674 ixgbe_release_swfw_semaphore(hw, mask);
678 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
679 * It returns 0 on success.
682 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
683 struct rte_eth_dev *eth_dev)
685 struct rte_pci_device *pci_dev;
686 struct ixgbe_hw *hw =
687 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
688 struct ixgbe_vfta * shadow_vfta =
689 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
690 struct ixgbe_hwstrip *hwstrip =
691 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
692 struct ixgbe_dcb_config *dcb_config =
693 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
698 PMD_INIT_FUNC_TRACE();
700 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
701 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
702 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
704 /* for secondary processes, we don't initialise any further as primary
705 * has already done this work. Only check we don't need a different
707 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
708 if (eth_dev->data->scattered_rx)
709 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
712 pci_dev = eth_dev->pci_dev;
714 /* Vendor and Device ID need to be set before init of shared code */
715 hw->device_id = pci_dev->id.device_id;
716 hw->vendor_id = pci_dev->id.vendor_id;
717 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
718 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
719 hw->allow_unsupported_sfp = 1;
722 /* Initialize the shared code */
723 #ifdef RTE_NIC_BYPASS
724 diag = ixgbe_bypass_init_shared_code(hw);
726 diag = ixgbe_init_shared_code(hw);
727 #endif /* RTE_NIC_BYPASS */
729 if (diag != IXGBE_SUCCESS) {
730 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
734 /* pick up the PCI bus settings for reporting later */
735 ixgbe_get_bus_info(hw);
737 /* Unlock any pending hardware semaphore */
738 ixgbe_swfw_lock_reset(hw);
740 /* Initialize DCB configuration*/
741 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
742 ixgbe_dcb_init(hw,dcb_config);
743 /* Get Hardware Flow Control setting */
744 hw->fc.requested_mode = ixgbe_fc_full;
745 hw->fc.current_mode = ixgbe_fc_full;
746 hw->fc.pause_time = IXGBE_FC_PAUSE;
747 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
748 hw->fc.low_water[i] = IXGBE_FC_LO;
749 hw->fc.high_water[i] = IXGBE_FC_HI;
753 /* Make sure we have a good EEPROM before we read from it */
754 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
755 if (diag != IXGBE_SUCCESS) {
756 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
760 #ifdef RTE_NIC_BYPASS
761 diag = ixgbe_bypass_init_hw(hw);
763 diag = ixgbe_init_hw(hw);
764 #endif /* RTE_NIC_BYPASS */
767 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
768 * is called too soon after the kernel driver unbinding/binding occurs.
769 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
770 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
771 * also called. See ixgbe_identify_phy_82599(). The reason for the
772 * failure is not known, and only occuts when virtualisation features
773 * are disabled in the bios. A delay of 100ms was found to be enough by
774 * trial-and-error, and is doubled to be safe.
776 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
778 diag = ixgbe_init_hw(hw);
781 if (diag == IXGBE_ERR_EEPROM_VERSION) {
782 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
783 "LOM. Please be aware there may be issues associated "
784 "with your hardware.\n If you are experiencing problems "
785 "please contact your Intel or hardware representative "
786 "who provided you with this hardware.\n");
787 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
788 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module\n");
790 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
794 /* disable interrupt */
795 ixgbe_disable_intr(hw);
797 /* reset mappings for queue statistics hw counters*/
798 ixgbe_reset_qstat_mappings(hw);
800 /* Allocate memory for storing MAC addresses */
801 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
802 hw->mac.num_rar_entries, 0);
803 if (eth_dev->data->mac_addrs == NULL) {
805 "Failed to allocate %u bytes needed to store "
807 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
810 /* Copy the permanent MAC address */
811 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
812 ð_dev->data->mac_addrs[0]);
814 /* Allocate memory for storing hash filter MAC addresses */
815 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
816 IXGBE_VMDQ_NUM_UC_MAC, 0);
817 if (eth_dev->data->hash_mac_addrs == NULL) {
819 "Failed to allocate %d bytes needed to store MAC addresses",
820 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
824 /* initialize the vfta */
825 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
827 /* initialize the hw strip bitmap*/
828 memset(hwstrip, 0, sizeof(*hwstrip));
830 /* initialize PF if max_vfs not zero */
831 ixgbe_pf_host_init(eth_dev);
833 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
834 /* let hardware know driver is loaded */
835 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
836 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
837 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
838 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
839 IXGBE_WRITE_FLUSH(hw);
841 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
843 "MAC: %d, PHY: %d, SFP+: %d<n",
844 (int) hw->mac.type, (int) hw->phy.type,
845 (int) hw->phy.sfp_type);
847 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d\n",
848 (int) hw->mac.type, (int) hw->phy.type);
850 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
851 eth_dev->data->port_id, pci_dev->id.vendor_id,
852 pci_dev->id.device_id);
854 rte_intr_callback_register(&(pci_dev->intr_handle),
855 ixgbe_dev_interrupt_handler, (void *)eth_dev);
857 /* enable uio intr after callback register */
858 rte_intr_enable(&(pci_dev->intr_handle));
860 /* enable support intr */
861 ixgbe_enable_intr(eth_dev);
868 * Negotiate mailbox API version with the PF.
869 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
870 * Then we try to negotiate starting with the most recent one.
871 * If all negotiation attempts fail, then we will proceed with
872 * the default one (ixgbe_mbox_api_10).
875 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
879 /* start with highest supported, proceed down */
880 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
886 i != RTE_DIM(sup_ver) &&
887 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
893 generate_random_mac_addr(struct ether_addr *mac_addr)
897 /* Set Organizationally Unique Identifier (OUI) prefix. */
898 mac_addr->addr_bytes[0] = 0x00;
899 mac_addr->addr_bytes[1] = 0x09;
900 mac_addr->addr_bytes[2] = 0xC0;
901 /* Force indication of locally assigned MAC address. */
902 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
903 /* Generate the last 3 bytes of the MAC address with a random number. */
905 memcpy(&mac_addr->addr_bytes[3], &random, 3);
909 * Virtual Function device init
912 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
913 struct rte_eth_dev *eth_dev)
917 struct rte_pci_device *pci_dev;
918 struct ixgbe_hw *hw =
919 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
920 struct ixgbe_vfta * shadow_vfta =
921 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
922 struct ixgbe_hwstrip *hwstrip =
923 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
924 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
926 PMD_INIT_LOG(DEBUG, "eth_ixgbevf_dev_init");
928 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
929 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
930 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
932 /* for secondary processes, we don't initialise any further as primary
933 * has already done this work. Only check we don't need a different
935 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
936 if (eth_dev->data->scattered_rx)
937 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
941 pci_dev = eth_dev->pci_dev;
943 hw->device_id = pci_dev->id.device_id;
944 hw->vendor_id = pci_dev->id.vendor_id;
945 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
947 /* initialize the vfta */
948 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
950 /* initialize the hw strip bitmap*/
951 memset(hwstrip, 0, sizeof(*hwstrip));
953 /* Initialize the shared code */
954 diag = ixgbe_init_shared_code(hw);
955 if (diag != IXGBE_SUCCESS) {
956 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
960 /* init_mailbox_params */
961 hw->mbx.ops.init_params(hw);
963 /* Disable the interrupts for VF */
964 ixgbevf_intr_disable(hw);
966 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
967 diag = hw->mac.ops.reset_hw(hw);
970 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
971 * the underlying PF driver has not assigned a MAC address to the VF.
972 * In this case, assign a random MAC address.
974 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
975 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
979 /* negotiate mailbox API version to use with the PF. */
980 ixgbevf_negotiate_api(hw);
982 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
983 ixgbevf_get_queues(hw, &tcs, &tc);
985 /* Allocate memory for storing MAC addresses */
986 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
987 hw->mac.num_rar_entries, 0);
988 if (eth_dev->data->mac_addrs == NULL) {
990 "Failed to allocate %u bytes needed to store "
992 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
996 /* Generate a random MAC address, if none was assigned by PF. */
997 if (is_zero_ether_addr(perm_addr)) {
998 generate_random_mac_addr(perm_addr);
999 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1001 rte_free(eth_dev->data->mac_addrs);
1002 eth_dev->data->mac_addrs = NULL;
1006 "\tVF MAC address not assigned by Host PF\n"
1007 "\tAssign randomly generated MAC address "
1008 "%02x:%02x:%02x:%02x:%02x:%02x\n",
1009 perm_addr->addr_bytes[0],
1010 perm_addr->addr_bytes[1],
1011 perm_addr->addr_bytes[2],
1012 perm_addr->addr_bytes[3],
1013 perm_addr->addr_bytes[4],
1014 perm_addr->addr_bytes[5]);
1017 /* Copy the permanent MAC address */
1018 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1020 /* reset the hardware with the new settings */
1021 diag = hw->mac.ops.start_hw(hw);
1027 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1031 PMD_INIT_LOG(DEBUG, "\nport %d vendorID=0x%x deviceID=0x%x mac.type=%s\n",
1032 eth_dev->data->port_id, pci_dev->id.vendor_id, pci_dev->id.device_id,
1033 "ixgbe_mac_82599_vf");
1038 static struct eth_driver rte_ixgbe_pmd = {
1040 .name = "rte_ixgbe_pmd",
1041 .id_table = pci_id_ixgbe_map,
1042 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1044 .eth_dev_init = eth_ixgbe_dev_init,
1045 .dev_private_size = sizeof(struct ixgbe_adapter),
1049 * virtual function driver struct
1051 static struct eth_driver rte_ixgbevf_pmd = {
1053 .name = "rte_ixgbevf_pmd",
1054 .id_table = pci_id_ixgbevf_map,
1055 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1057 .eth_dev_init = eth_ixgbevf_dev_init,
1058 .dev_private_size = sizeof(struct ixgbe_adapter),
1062 * Driver initialization routine.
1063 * Invoked once at EAL init time.
1064 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1067 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1069 PMD_INIT_FUNC_TRACE();
1071 rte_eth_driver_register(&rte_ixgbe_pmd);
1076 * VF Driver initialization routine.
1077 * Invoked one at EAL init time.
1078 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1081 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1083 DEBUGFUNC("rte_ixgbevf_pmd_init");
1085 rte_eth_driver_register(&rte_ixgbevf_pmd);
1090 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1092 struct ixgbe_hw *hw =
1093 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1094 struct ixgbe_vfta * shadow_vfta =
1095 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1100 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1101 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1102 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1107 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1109 /* update local VFTA copy */
1110 shadow_vfta->vfta[vid_idx] = vfta;
1116 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1119 ixgbe_vlan_hw_strip_enable(dev, queue);
1121 ixgbe_vlan_hw_strip_disable(dev, queue);
1125 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1127 struct ixgbe_hw *hw =
1128 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1130 /* Only the high 16-bits is valid */
1131 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1135 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1137 struct ixgbe_hw *hw =
1138 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 PMD_INIT_FUNC_TRACE();
1143 /* Filter Table Disable */
1144 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1145 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1147 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1151 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1153 struct ixgbe_hw *hw =
1154 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1155 struct ixgbe_vfta * shadow_vfta =
1156 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1160 PMD_INIT_FUNC_TRACE();
1162 /* Filter Table Enable */
1163 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1164 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1165 vlnctrl |= IXGBE_VLNCTRL_VFE;
1167 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1169 /* write whatever is in local vfta copy */
1170 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1171 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1175 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1177 struct ixgbe_hwstrip *hwstrip =
1178 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1180 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1184 IXGBE_SET_HWSTRIP(hwstrip, queue);
1186 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1190 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1192 struct ixgbe_hw *hw =
1193 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196 PMD_INIT_FUNC_TRACE();
1198 if (hw->mac.type == ixgbe_mac_82598EB) {
1199 /* No queue level support */
1200 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1204 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1205 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1206 ctrl &= ~IXGBE_RXDCTL_VME;
1207 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1209 /* record those setting for HW strip per queue */
1210 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1214 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1216 struct ixgbe_hw *hw =
1217 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1220 PMD_INIT_FUNC_TRACE();
1222 if (hw->mac.type == ixgbe_mac_82598EB) {
1223 /* No queue level supported */
1224 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1228 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1229 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1230 ctrl |= IXGBE_RXDCTL_VME;
1231 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1233 /* record those setting for HW strip per queue */
1234 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1238 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1240 struct ixgbe_hw *hw =
1241 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1245 PMD_INIT_FUNC_TRACE();
1247 if (hw->mac.type == ixgbe_mac_82598EB) {
1248 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1249 ctrl &= ~IXGBE_VLNCTRL_VME;
1250 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1253 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1254 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1255 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1256 ctrl &= ~IXGBE_RXDCTL_VME;
1257 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1259 /* record those setting for HW strip per queue */
1260 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1266 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1268 struct ixgbe_hw *hw =
1269 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1273 PMD_INIT_FUNC_TRACE();
1275 if (hw->mac.type == ixgbe_mac_82598EB) {
1276 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1277 ctrl |= IXGBE_VLNCTRL_VME;
1278 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1281 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1282 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1283 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1284 ctrl |= IXGBE_RXDCTL_VME;
1285 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1287 /* record those setting for HW strip per queue */
1288 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1294 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1296 struct ixgbe_hw *hw =
1297 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1300 PMD_INIT_FUNC_TRACE();
1302 /* DMATXCTRL: Geric Double VLAN Disable */
1303 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1304 ctrl &= ~IXGBE_DMATXCTL_GDV;
1305 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1307 /* CTRL_EXT: Global Double VLAN Disable */
1308 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1309 ctrl &= ~IXGBE_EXTENDED_VLAN;
1310 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1315 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1317 struct ixgbe_hw *hw =
1318 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1321 PMD_INIT_FUNC_TRACE();
1323 /* DMATXCTRL: Geric Double VLAN Enable */
1324 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1325 ctrl |= IXGBE_DMATXCTL_GDV;
1326 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1328 /* CTRL_EXT: Global Double VLAN Enable */
1329 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1330 ctrl |= IXGBE_EXTENDED_VLAN;
1331 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1334 * VET EXT field in the EXVET register = 0x8100 by default
1335 * So no need to change. Same to VT field of DMATXCTL register
1340 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1342 if(mask & ETH_VLAN_STRIP_MASK){
1343 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1344 ixgbe_vlan_hw_strip_enable_all(dev);
1346 ixgbe_vlan_hw_strip_disable_all(dev);
1349 if(mask & ETH_VLAN_FILTER_MASK){
1350 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1351 ixgbe_vlan_hw_filter_enable(dev);
1353 ixgbe_vlan_hw_filter_disable(dev);
1356 if(mask & ETH_VLAN_EXTEND_MASK){
1357 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1358 ixgbe_vlan_hw_extend_enable(dev);
1360 ixgbe_vlan_hw_extend_disable(dev);
1365 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1367 struct ixgbe_hw *hw =
1368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1369 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1370 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1371 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1372 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1376 ixgbe_dev_configure(struct rte_eth_dev *dev)
1378 struct ixgbe_interrupt *intr =
1379 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1381 PMD_INIT_FUNC_TRACE();
1383 /* set flag to update link status after init */
1384 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1390 * Configure device link speed and setup link.
1391 * It returns 0 on success.
1394 ixgbe_dev_start(struct rte_eth_dev *dev)
1396 struct ixgbe_hw *hw =
1397 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398 struct ixgbe_vf_info *vfinfo =
1399 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1400 int err, link_up = 0, negotiate = 0;
1406 PMD_INIT_FUNC_TRACE();
1408 /* IXGBE devices don't support half duplex */
1409 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1410 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1411 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu\n",
1412 dev->data->dev_conf.link_duplex,
1413 dev->data->port_id);
1418 hw->adapter_stopped = FALSE;
1419 ixgbe_stop_adapter(hw);
1421 /* reinitialize adapter
1422 * this calls reset and start */
1423 status = ixgbe_pf_reset_hw(hw);
1426 hw->mac.ops.start_hw(hw);
1428 /* configure PF module if SRIOV enabled */
1429 ixgbe_pf_host_configure(dev);
1431 /* initialize transmission unit */
1432 ixgbe_dev_tx_init(dev);
1434 /* This can fail when allocating mbufs for descriptor rings */
1435 err = ixgbe_dev_rx_init(dev);
1437 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware\n");
1441 ixgbe_dev_rxtx_start(dev);
1443 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1444 err = hw->mac.ops.setup_sfp(hw);
1449 /* Turn on the laser */
1450 ixgbe_enable_tx_laser(hw);
1452 /* Skip link setup if loopback mode is enabled for 82599. */
1453 if (hw->mac.type == ixgbe_mac_82599EB &&
1454 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1455 goto skip_link_setup;
1457 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1460 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1464 switch(dev->data->dev_conf.link_speed) {
1465 case ETH_LINK_SPEED_AUTONEG:
1466 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1467 IXGBE_LINK_SPEED_82599_AUTONEG :
1468 IXGBE_LINK_SPEED_82598_AUTONEG;
1470 case ETH_LINK_SPEED_100:
1472 * Invalid for 82598 but error will be detected by
1473 * ixgbe_setup_link()
1475 speed = IXGBE_LINK_SPEED_100_FULL;
1477 case ETH_LINK_SPEED_1000:
1478 speed = IXGBE_LINK_SPEED_1GB_FULL;
1480 case ETH_LINK_SPEED_10000:
1481 speed = IXGBE_LINK_SPEED_10GB_FULL;
1484 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu\n",
1485 dev->data->dev_conf.link_speed,
1486 dev->data->port_id);
1490 err = ixgbe_setup_link(hw, speed, negotiate, link_up);
1496 /* check if lsc interrupt is enabled */
1497 if (dev->data->dev_conf.intr_conf.lsc != 0)
1498 ixgbe_dev_lsc_interrupt_setup(dev);
1500 /* resume enabled intr since hw reset */
1501 ixgbe_enable_intr(dev);
1503 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1504 ETH_VLAN_EXTEND_MASK;
1505 ixgbe_vlan_offload_set(dev, mask);
1507 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1508 /* Enable vlan filtering for VMDq */
1509 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1512 /* Configure DCB hw */
1513 ixgbe_configure_dcb(dev);
1515 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1516 err = ixgbe_fdir_configure(dev);
1521 /* Restore vf rate limit */
1522 if (vfinfo != NULL) {
1523 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1524 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1525 if (vfinfo[vf].tx_rate[idx] != 0)
1526 ixgbe_set_vf_rate_limit(dev, vf,
1527 vfinfo[vf].tx_rate[idx],
1531 ixgbe_restore_statistics_mapping(dev);
1536 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1537 ixgbe_dev_clear_queues(dev);
1542 * Stop device: disable rx and tx functions to allow for reconfiguring.
1545 ixgbe_dev_stop(struct rte_eth_dev *dev)
1547 struct rte_eth_link link;
1548 struct ixgbe_hw *hw =
1549 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550 struct ixgbe_vf_info *vfinfo =
1551 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1554 PMD_INIT_FUNC_TRACE();
1556 /* disable interrupts */
1557 ixgbe_disable_intr(hw);
1560 ixgbe_pf_reset_hw(hw);
1561 hw->adapter_stopped = FALSE;
1564 ixgbe_stop_adapter(hw);
1566 for (vf = 0; vfinfo != NULL &&
1567 vf < dev->pci_dev->max_vfs; vf++)
1568 vfinfo[vf].clear_to_send = false;
1570 /* Turn off the laser */
1571 ixgbe_disable_tx_laser(hw);
1573 ixgbe_dev_clear_queues(dev);
1575 /* Clear recorded link status */
1576 memset(&link, 0, sizeof(link));
1577 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1581 * Set device link up: enable tx laser.
1584 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1586 struct ixgbe_hw *hw =
1587 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588 if (hw->mac.type == ixgbe_mac_82599EB) {
1589 #ifdef RTE_NIC_BYPASS
1590 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1591 /* Not suported in bypass mode */
1593 "\nSet link up is not supported "
1594 "by device id 0x%x\n",
1599 /* Turn on the laser */
1600 ixgbe_enable_tx_laser(hw);
1604 PMD_INIT_LOG(ERR, "\nSet link up is not supported by device id 0x%x\n",
1610 * Set device link down: disable tx laser.
1613 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1615 struct ixgbe_hw *hw =
1616 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617 if (hw->mac.type == ixgbe_mac_82599EB) {
1618 #ifdef RTE_NIC_BYPASS
1619 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1620 /* Not suported in bypass mode */
1622 "\nSet link down is not supported "
1623 "by device id 0x%x\n",
1628 /* Turn off the laser */
1629 ixgbe_disable_tx_laser(hw);
1634 "\nSet link down is not supported by device id 0x%x\n",
1640 * Reest and stop device.
1643 ixgbe_dev_close(struct rte_eth_dev *dev)
1645 struct ixgbe_hw *hw =
1646 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648 PMD_INIT_FUNC_TRACE();
1650 ixgbe_pf_reset_hw(hw);
1652 ixgbe_dev_stop(dev);
1653 hw->adapter_stopped = 1;
1655 ixgbe_disable_pcie_master(hw);
1657 /* reprogram the RAR[0] in case user changed it. */
1658 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1662 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1665 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1667 struct ixgbe_hw *hw =
1668 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1669 struct ixgbe_hw_stats *hw_stats =
1670 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1671 uint32_t bprc, lxon, lxoff, total;
1672 uint64_t total_missed_rx, total_qbrc, total_qprc;
1675 total_missed_rx = 0;
1679 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1680 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1681 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1682 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1684 for (i = 0; i < 8; i++) {
1686 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1687 /* global total per queue */
1688 hw_stats->mpc[i] += mp;
1689 /* Running comprehensive total for stats display */
1690 total_missed_rx += hw_stats->mpc[i];
1691 if (hw->mac.type == ixgbe_mac_82598EB)
1692 hw_stats->rnbc[i] +=
1693 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1694 hw_stats->pxontxc[i] +=
1695 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1696 hw_stats->pxonrxc[i] +=
1697 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1698 hw_stats->pxofftxc[i] +=
1699 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1700 hw_stats->pxoffrxc[i] +=
1701 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1702 hw_stats->pxon2offc[i] +=
1703 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1705 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1706 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1707 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1708 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1709 hw_stats->qbrc[i] +=
1710 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1711 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1712 hw_stats->qbtc[i] +=
1713 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1714 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1716 total_qprc += hw_stats->qprc[i];
1717 total_qbrc += hw_stats->qbrc[i];
1719 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1720 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1721 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1723 /* Note that gprc counts missed packets */
1724 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1726 if (hw->mac.type != ixgbe_mac_82598EB) {
1727 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1728 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1729 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1730 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1731 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1732 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1733 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1734 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1736 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1737 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1738 /* 82598 only has a counter in the high register */
1739 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1740 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1741 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1745 * Workaround: mprc hardware is incorrectly counting
1746 * broadcasts, so for now we subtract those.
1748 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1749 hw_stats->bprc += bprc;
1750 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1751 if (hw->mac.type == ixgbe_mac_82598EB)
1752 hw_stats->mprc -= bprc;
1754 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1755 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1756 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1757 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1758 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1759 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1761 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1762 hw_stats->lxontxc += lxon;
1763 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1764 hw_stats->lxofftxc += lxoff;
1765 total = lxon + lxoff;
1767 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1768 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1769 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1770 hw_stats->gptc -= total;
1771 hw_stats->mptc -= total;
1772 hw_stats->ptc64 -= total;
1773 hw_stats->gotc -= total * ETHER_MIN_LEN;
1775 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1776 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1777 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1778 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1779 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1780 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1781 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1782 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1783 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1784 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1785 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1786 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1787 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1788 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1789 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1790 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1791 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1792 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1793 /* Only read FCOE on 82599 */
1794 if (hw->mac.type != ixgbe_mac_82598EB) {
1795 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1796 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1797 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1798 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1799 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1805 /* Fill out the rte_eth_stats statistics structure */
1806 stats->ipackets = total_qprc;
1807 stats->ibytes = total_qbrc;
1808 stats->opackets = hw_stats->gptc;
1809 stats->obytes = hw_stats->gotc;
1810 stats->imcasts = hw_stats->mprc;
1812 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1813 stats->q_ipackets[i] = hw_stats->qprc[i];
1814 stats->q_opackets[i] = hw_stats->qptc[i];
1815 stats->q_ibytes[i] = hw_stats->qbrc[i];
1816 stats->q_obytes[i] = hw_stats->qbtc[i];
1817 stats->q_errors[i] = hw_stats->qprdc[i];
1821 stats->ierrors = total_missed_rx + hw_stats->crcerrs +
1826 /* XON/XOFF pause frames */
1827 stats->tx_pause_xon = hw_stats->lxontxc;
1828 stats->rx_pause_xon = hw_stats->lxonrxc;
1829 stats->tx_pause_xoff = hw_stats->lxofftxc;
1830 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1832 /* Flow Director Stats registers */
1833 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1834 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1835 stats->fdirmatch = hw_stats->fdirmatch;
1836 stats->fdirmiss = hw_stats->fdirmiss;
1840 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1842 struct ixgbe_hw_stats *stats =
1843 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1845 /* HW registers are cleared on read */
1846 ixgbe_dev_stats_get(dev, NULL);
1848 /* Reset software totals */
1849 memset(stats, 0, sizeof(*stats));
1853 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1856 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1857 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1859 /* Good Rx packet, include VF loopback */
1860 UPDATE_VF_STAT(IXGBE_VFGPRC,
1861 hw_stats->last_vfgprc, hw_stats->vfgprc);
1863 /* Good Rx octets, include VF loopback */
1864 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1865 hw_stats->last_vfgorc, hw_stats->vfgorc);
1867 /* Good Tx packet, include VF loopback */
1868 UPDATE_VF_STAT(IXGBE_VFGPTC,
1869 hw_stats->last_vfgptc, hw_stats->vfgptc);
1871 /* Good Tx octets, include VF loopback */
1872 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1873 hw_stats->last_vfgotc, hw_stats->vfgotc);
1875 /* Rx Multicst Packet */
1876 UPDATE_VF_STAT(IXGBE_VFMPRC,
1877 hw_stats->last_vfmprc, hw_stats->vfmprc);
1882 memset(stats, 0, sizeof(*stats));
1883 stats->ipackets = hw_stats->vfgprc;
1884 stats->ibytes = hw_stats->vfgorc;
1885 stats->opackets = hw_stats->vfgptc;
1886 stats->obytes = hw_stats->vfgotc;
1887 stats->imcasts = hw_stats->vfmprc;
1891 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1893 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1894 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1896 /* Sync HW register to the last stats */
1897 ixgbevf_dev_stats_get(dev, NULL);
1899 /* reset HW current stats*/
1900 hw_stats->vfgprc = 0;
1901 hw_stats->vfgorc = 0;
1902 hw_stats->vfgptc = 0;
1903 hw_stats->vfgotc = 0;
1904 hw_stats->vfmprc = 0;
1909 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1911 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1914 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1915 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1916 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1917 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1918 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1919 dev_info->max_vfs = dev->pci_dev->max_vfs;
1920 if (hw->mac.type == ixgbe_mac_82598EB)
1921 dev_info->max_vmdq_pools = ETH_16_POOLS;
1923 dev_info->max_vmdq_pools = ETH_64_POOLS;
1924 dev_info->rx_offload_capa =
1925 DEV_RX_OFFLOAD_VLAN_STRIP |
1926 DEV_RX_OFFLOAD_IPV4_CKSUM |
1927 DEV_RX_OFFLOAD_UDP_CKSUM |
1928 DEV_RX_OFFLOAD_TCP_CKSUM;
1929 dev_info->tx_offload_capa =
1930 DEV_TX_OFFLOAD_VLAN_INSERT |
1931 DEV_TX_OFFLOAD_IPV4_CKSUM |
1932 DEV_TX_OFFLOAD_UDP_CKSUM |
1933 DEV_TX_OFFLOAD_TCP_CKSUM |
1934 DEV_TX_OFFLOAD_SCTP_CKSUM;
1937 /* return 0 means link status changed, -1 means not changed */
1939 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1941 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 struct rte_eth_link link, old;
1943 ixgbe_link_speed link_speed;
1947 link.link_status = 0;
1948 link.link_speed = 0;
1949 link.link_duplex = 0;
1950 memset(&old, 0, sizeof(old));
1951 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1953 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1954 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1955 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1957 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1959 link.link_speed = ETH_LINK_SPEED_100;
1960 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1961 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1962 if (link.link_status == old.link_status)
1968 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1969 if (link.link_status == old.link_status)
1973 link.link_status = 1;
1974 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1976 switch (link_speed) {
1978 case IXGBE_LINK_SPEED_UNKNOWN:
1979 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1980 link.link_speed = ETH_LINK_SPEED_100;
1983 case IXGBE_LINK_SPEED_100_FULL:
1984 link.link_speed = ETH_LINK_SPEED_100;
1987 case IXGBE_LINK_SPEED_1GB_FULL:
1988 link.link_speed = ETH_LINK_SPEED_1000;
1991 case IXGBE_LINK_SPEED_10GB_FULL:
1992 link.link_speed = ETH_LINK_SPEED_10000;
1995 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1997 if (link.link_status == old.link_status)
2004 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2006 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2010 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2011 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2015 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2021 fctrl &= (~IXGBE_FCTRL_UPE);
2022 if (dev->data->all_multicast == 1)
2023 fctrl |= IXGBE_FCTRL_MPE;
2025 fctrl &= (~IXGBE_FCTRL_MPE);
2026 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2030 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2032 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2036 fctrl |= IXGBE_FCTRL_MPE;
2037 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2041 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046 if (dev->data->promiscuous == 1)
2047 return; /* must remain in all_multicast mode */
2049 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2050 fctrl &= (~IXGBE_FCTRL_MPE);
2051 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2055 * It clears the interrupt causes and enables the interrupt.
2056 * It will be called once only during nic initialized.
2059 * Pointer to struct rte_eth_dev.
2062 * - On success, zero.
2063 * - On failure, a negative value.
2066 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2068 struct ixgbe_interrupt *intr =
2069 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2071 ixgbe_dev_link_status_print(dev);
2072 intr->mask |= IXGBE_EICR_LSC;
2078 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2081 * Pointer to struct rte_eth_dev.
2084 * - On success, zero.
2085 * - On failure, a negative value.
2088 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2092 struct ixgbe_interrupt *intr =
2093 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2095 /* clear all cause mask */
2096 ixgbe_disable_intr(hw);
2098 /* read-on-clear nic registers here */
2099 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2100 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2103 if (eicr & IXGBE_EICR_LSC) {
2104 /* set flag for async link update */
2105 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2108 if (eicr & IXGBE_EICR_MAILBOX)
2109 intr->flags |= IXGBE_FLAG_MAILBOX;
2115 * It gets and then prints the link status.
2118 * Pointer to struct rte_eth_dev.
2121 * - On success, zero.
2122 * - On failure, a negative value.
2125 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2127 struct rte_eth_link link;
2129 memset(&link, 0, sizeof(link));
2130 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2131 if (link.link_status) {
2132 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2133 (int)(dev->data->port_id),
2134 (unsigned)link.link_speed,
2135 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2136 "full-duplex" : "half-duplex");
2138 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2139 (int)(dev->data->port_id));
2141 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2142 dev->pci_dev->addr.domain,
2143 dev->pci_dev->addr.bus,
2144 dev->pci_dev->addr.devid,
2145 dev->pci_dev->addr.function);
2149 * It executes link_update after knowing an interrupt occurred.
2152 * Pointer to struct rte_eth_dev.
2155 * - On success, zero.
2156 * - On failure, a negative value.
2159 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2161 struct ixgbe_interrupt *intr =
2162 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2164 struct rte_eth_link link;
2165 int intr_enable_delay = false;
2167 PMD_DRV_LOG(DEBUG, "intr action type %d\n", intr->flags);
2169 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2170 ixgbe_pf_mbx_process(dev);
2171 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2174 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2175 /* get the link status before link update, for predicting later */
2176 memset(&link, 0, sizeof(link));
2177 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2179 ixgbe_dev_link_update(dev, 0);
2182 if (!link.link_status)
2183 /* handle it 1 sec later, wait it being stable */
2184 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2185 /* likely to down */
2187 /* handle it 4 sec later, wait it being stable */
2188 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2190 ixgbe_dev_link_status_print(dev);
2192 intr_enable_delay = true;
2195 if (intr_enable_delay) {
2196 if (rte_eal_alarm_set(timeout * 1000,
2197 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2198 PMD_DRV_LOG(ERR, "Error setting alarm");
2200 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2201 ixgbe_enable_intr(dev);
2202 rte_intr_enable(&(dev->pci_dev->intr_handle));
2210 * Interrupt handler which shall be registered for alarm callback for delayed
2211 * handling specific interrupt to wait for the stable nic state. As the
2212 * NIC interrupt state is not stable for ixgbe after link is just down,
2213 * it needs to wait 4 seconds to get the stable status.
2216 * Pointer to interrupt handle.
2218 * The address of parameter (struct rte_eth_dev *) regsitered before.
2224 ixgbe_dev_interrupt_delayed_handler(void *param)
2226 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2227 struct ixgbe_interrupt *intr =
2228 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2229 struct ixgbe_hw *hw =
2230 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2233 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2234 if (eicr & IXGBE_EICR_MAILBOX)
2235 ixgbe_pf_mbx_process(dev);
2237 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2238 ixgbe_dev_link_update(dev, 0);
2239 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2240 ixgbe_dev_link_status_print(dev);
2241 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2244 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]\n", eicr);
2245 ixgbe_enable_intr(dev);
2246 rte_intr_enable(&(dev->pci_dev->intr_handle));
2250 * Interrupt handler triggered by NIC for handling
2251 * specific interrupt.
2254 * Pointer to interrupt handle.
2256 * The address of parameter (struct rte_eth_dev *) regsitered before.
2262 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2265 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2266 ixgbe_dev_interrupt_get_status(dev);
2267 ixgbe_dev_interrupt_action(dev);
2271 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2273 struct ixgbe_hw *hw;
2275 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2280 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2282 struct ixgbe_hw *hw;
2284 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2289 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2291 struct ixgbe_hw *hw;
2293 uint32_t rx_buf_size;
2294 uint32_t max_high_water;
2296 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2303 PMD_INIT_FUNC_TRACE();
2305 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2307 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2310 * At least reserve one Ethernet frame for watermark
2311 * high_water/low_water in kilo bytes for ixgbe
2313 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2314 if ((fc_conf->high_water > max_high_water) ||
2315 (fc_conf->high_water < fc_conf->low_water)) {
2316 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2317 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2321 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2322 hw->fc.pause_time = fc_conf->pause_time;
2323 hw->fc.high_water[0] = fc_conf->high_water;
2324 hw->fc.low_water[0] = fc_conf->low_water;
2325 hw->fc.send_xon = fc_conf->send_xon;
2327 err = ixgbe_fc_enable(hw);
2329 /* Not negotiated is not an error case */
2330 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2332 /* check if we want to forward MAC frames - driver doesn't have native
2333 * capability to do that, so we'll write the registers ourselves */
2335 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2337 /* set or clear MFLCN.PMCF bit depending on configuration */
2338 if (fc_conf->mac_ctrl_frame_fwd != 0)
2339 mflcn |= IXGBE_MFLCN_PMCF;
2341 mflcn &= ~IXGBE_MFLCN_PMCF;
2343 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2344 IXGBE_WRITE_FLUSH(hw);
2349 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x \n", err);
2354 * ixgbe_pfc_enable_generic - Enable flow control
2355 * @hw: pointer to hardware structure
2356 * @tc_num: traffic class number
2357 * Enable flow control according to the current settings.
2360 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2363 uint32_t mflcn_reg, fccfg_reg;
2365 uint32_t fcrtl, fcrth;
2369 /* Validate the water mark configuration */
2370 if (!hw->fc.pause_time) {
2371 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2375 /* Low water mark of zero causes XOFF floods */
2376 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2377 /* High/Low water can not be 0 */
2378 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2379 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2380 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2384 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2385 PMD_INIT_LOG(ERR,"Invalid water mark configuration\n");
2386 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2390 /* Negotiate the fc mode to use */
2391 ixgbe_fc_autoneg(hw);
2393 /* Disable any previous flow control settings */
2394 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2395 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2397 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2398 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2400 switch (hw->fc.current_mode) {
2403 * If the count of enabled RX Priority Flow control >1,
2404 * and the TX pause can not be disabled
2407 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2408 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2409 if (reg & IXGBE_FCRTH_FCEN)
2413 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2415 case ixgbe_fc_rx_pause:
2417 * Rx Flow control is enabled and Tx Flow control is
2418 * disabled by software override. Since there really
2419 * isn't a way to advertise that we are capable of RX
2420 * Pause ONLY, we will advertise that we support both
2421 * symmetric and asymmetric Rx PAUSE. Later, we will
2422 * disable the adapter's ability to send PAUSE frames.
2424 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2426 * If the count of enabled RX Priority Flow control >1,
2427 * and the TX pause can not be disabled
2430 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2431 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2432 if (reg & IXGBE_FCRTH_FCEN)
2436 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2438 case ixgbe_fc_tx_pause:
2440 * Tx Flow control is enabled, and Rx Flow control is
2441 * disabled by software override.
2443 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2446 /* Flow control (both Rx and Tx) is enabled by SW override. */
2447 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2448 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2451 DEBUGOUT("Flow control param set incorrectly\n");
2452 ret_val = IXGBE_ERR_CONFIG;
2457 /* Set 802.3x based flow control settings. */
2458 mflcn_reg |= IXGBE_MFLCN_DPF;
2459 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2460 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2462 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2463 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2464 hw->fc.high_water[tc_num]) {
2465 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2466 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2467 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2469 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2471 * In order to prevent Tx hangs when the internal Tx
2472 * switch is enabled we must set the high water mark
2473 * to the maximum FCRTH value. This allows the Tx
2474 * switch to function even under heavy Rx workloads.
2476 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2478 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2480 /* Configure pause time (2 TCs per register) */
2481 reg = hw->fc.pause_time * 0x00010001;
2482 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2483 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2485 /* Configure flow control refresh threshold value */
2486 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2493 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2495 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2496 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2498 if(hw->mac.type != ixgbe_mac_82598EB) {
2499 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2505 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2508 uint32_t rx_buf_size;
2509 uint32_t max_high_water;
2511 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2512 struct ixgbe_hw *hw =
2513 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2514 struct ixgbe_dcb_config *dcb_config =
2515 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2517 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2524 PMD_INIT_FUNC_TRACE();
2526 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2527 tc_num = map[pfc_conf->priority];
2528 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2529 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
2531 * At least reserve one Ethernet frame for watermark
2532 * high_water/low_water in kilo bytes for ixgbe
2534 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2535 if ((pfc_conf->fc.high_water > max_high_water) ||
2536 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2537 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB\n");
2538 PMD_INIT_LOG(ERR, "High_water must <= 0x%x\n", max_high_water);
2542 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2543 hw->fc.pause_time = pfc_conf->fc.pause_time;
2544 hw->fc.send_xon = pfc_conf->fc.send_xon;
2545 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2546 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2548 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2550 /* Not negotiated is not an error case */
2551 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2554 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x \n", err);
2559 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2560 struct rte_eth_rss_reta *reta_conf)
2564 struct ixgbe_hw *hw =
2565 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2567 PMD_INIT_FUNC_TRACE();
2569 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2570 * 128-entries in 32 registers
2572 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2573 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2574 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2576 mask = (uint8_t)((reta_conf->mask_hi >>
2577 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2581 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2583 for (j = 0; j < 4; j++) {
2584 if (mask & (0x1 << j)) {
2586 reta &= ~(0xFF << 8 * j);
2587 reta |= reta_conf->reta[i + j] << 8*j;
2590 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2598 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2599 struct rte_eth_rss_reta *reta_conf)
2603 struct ixgbe_hw *hw =
2604 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606 PMD_INIT_FUNC_TRACE();
2608 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2609 * 128-entries in 32 registers
2611 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2612 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2613 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2615 mask = (uint8_t)((reta_conf->mask_hi >>
2616 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2619 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2620 for (j = 0; j < 4; j++) {
2621 if (mask & (0x1 << j))
2622 reta_conf->reta[i + j] =
2623 (uint8_t)((reta >> 8 * j) & 0xFF);
2632 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2633 uint32_t index, uint32_t pool)
2635 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2636 uint32_t enable_addr = 1;
2638 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2642 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2646 ixgbe_clear_rar(hw, index);
2650 * Virtual Function operations
2653 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2655 PMD_INIT_LOG(DEBUG, "ixgbevf_intr_disable");
2657 /* Clear interrupt mask to stop from interrupts being generated */
2658 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2660 IXGBE_WRITE_FLUSH(hw);
2664 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2666 struct rte_eth_conf* conf = &dev->data->dev_conf;
2668 PMD_INIT_LOG(DEBUG, "\nConfigured Virtual Function port id: %d\n",
2669 dev->data->port_id);
2672 * VF has no ability to enable/disable HW CRC
2673 * Keep the persistent behavior the same as Host PF
2675 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2676 if (!conf->rxmode.hw_strip_crc) {
2677 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip\n");
2678 conf->rxmode.hw_strip_crc = 1;
2681 if (conf->rxmode.hw_strip_crc) {
2682 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip\n");
2683 conf->rxmode.hw_strip_crc = 0;
2691 ixgbevf_dev_start(struct rte_eth_dev *dev)
2693 struct ixgbe_hw *hw =
2694 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2697 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_start");
2699 hw->mac.ops.reset_hw(hw);
2701 /* negotiate mailbox API version to use with the PF. */
2702 ixgbevf_negotiate_api(hw);
2704 ixgbevf_dev_tx_init(dev);
2706 /* This can fail when allocating mbufs for descriptor rings */
2707 err = ixgbevf_dev_rx_init(dev);
2709 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)\n", err);
2710 ixgbe_dev_clear_queues(dev);
2715 ixgbevf_set_vfta_all(dev,1);
2718 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2719 ETH_VLAN_EXTEND_MASK;
2720 ixgbevf_vlan_offload_set(dev, mask);
2722 ixgbevf_dev_rxtx_start(dev);
2728 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2730 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_stop");
2734 hw->adapter_stopped = TRUE;
2735 ixgbe_stop_adapter(hw);
2738 * Clear what we set, but we still keep shadow_vfta to
2739 * restore after device starts
2741 ixgbevf_set_vfta_all(dev,0);
2743 ixgbe_dev_clear_queues(dev);
2747 ixgbevf_dev_close(struct rte_eth_dev *dev)
2749 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751 PMD_INIT_LOG(DEBUG, "ixgbevf_dev_close");
2755 ixgbevf_dev_stop(dev);
2757 /* reprogram the RAR[0] in case user changed it. */
2758 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2761 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2763 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2764 struct ixgbe_vfta * shadow_vfta =
2765 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2766 int i = 0, j = 0, vfta = 0, mask = 1;
2768 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2769 vfta = shadow_vfta->vfta[i];
2772 for (j = 0; j < 32; j++){
2774 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2783 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2785 struct ixgbe_hw *hw =
2786 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787 struct ixgbe_vfta * shadow_vfta =
2788 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2789 uint32_t vid_idx = 0;
2790 uint32_t vid_bit = 0;
2793 PMD_INIT_FUNC_TRACE();
2795 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2796 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2798 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2801 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2802 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2804 /* Save what we set and retore it after device reset */
2806 shadow_vfta->vfta[vid_idx] |= vid_bit;
2808 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2814 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2816 struct ixgbe_hw *hw =
2817 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820 PMD_INIT_FUNC_TRACE();
2822 if(queue >= hw->mac.max_rx_queues)
2825 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2827 ctrl |= IXGBE_RXDCTL_VME;
2829 ctrl &= ~IXGBE_RXDCTL_VME;
2830 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2832 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2836 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2838 struct ixgbe_hw *hw =
2839 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843 /* VF function only support hw strip feature, others are not support */
2844 if(mask & ETH_VLAN_STRIP_MASK){
2845 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2847 for(i=0; i < hw->mac.max_rx_queues; i++)
2848 ixgbevf_vlan_strip_queue_set(dev,i,on);
2853 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2857 /* we only need to do this if VMDq is enabled */
2858 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2859 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2860 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting\n");
2868 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2870 uint32_t vector = 0;
2871 switch (hw->mac.mc_filter_type) {
2872 case 0: /* use bits [47:36] of the address */
2873 vector = ((uc_addr->addr_bytes[4] >> 4) |
2874 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2876 case 1: /* use bits [46:35] of the address */
2877 vector = ((uc_addr->addr_bytes[4] >> 3) |
2878 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2880 case 2: /* use bits [45:34] of the address */
2881 vector = ((uc_addr->addr_bytes[4] >> 2) |
2882 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2884 case 3: /* use bits [43:32] of the address */
2885 vector = ((uc_addr->addr_bytes[4]) |
2886 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2888 default: /* Invalid mc_filter_type */
2892 /* vector can only be 12-bits or boundary will be exceeded */
2898 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
2906 const uint32_t ixgbe_uta_idx_mask = 0x7F;
2907 const uint32_t ixgbe_uta_bit_shift = 5;
2908 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
2909 const uint32_t bit1 = 0x1;
2911 struct ixgbe_hw *hw =
2912 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913 struct ixgbe_uta_info *uta_info =
2914 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2916 /* The UTA table only exists on 82599 hardware and newer */
2917 if (hw->mac.type < ixgbe_mac_82599EB)
2920 vector = ixgbe_uta_vector(hw,mac_addr);
2921 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
2922 uta_shift = vector & ixgbe_uta_bit_mask;
2924 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
2928 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
2930 uta_info->uta_in_use++;
2931 reg_val |= (bit1 << uta_shift);
2932 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
2934 uta_info->uta_in_use--;
2935 reg_val &= ~(bit1 << uta_shift);
2936 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
2939 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
2941 if (uta_info->uta_in_use > 0)
2942 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2943 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2945 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
2951 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
2954 struct ixgbe_hw *hw =
2955 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956 struct ixgbe_uta_info *uta_info =
2957 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
2959 /* The UTA table only exists on 82599 hardware and newer */
2960 if (hw->mac.type < ixgbe_mac_82599EB)
2964 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2965 uta_info->uta_shadow[i] = ~0;
2966 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2969 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
2970 uta_info->uta_shadow[i] = 0;
2971 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
2978 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
2979 uint16_t rx_mask, uint8_t on)
2983 struct ixgbe_hw *hw =
2984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2985 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
2987 if (hw->mac.type == ixgbe_mac_82598EB) {
2988 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
2989 " on 82599 hardware and newer\n");
2992 if (ixgbe_vmdq_mode_check(hw) < 0)
2995 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
2996 val |= IXGBE_VMOLR_AUPE;
2997 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
2998 val |= IXGBE_VMOLR_ROMPE;
2999 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3000 val |= IXGBE_VMOLR_ROPE;
3001 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3002 val |= IXGBE_VMOLR_BAM;
3003 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3004 val |= IXGBE_VMOLR_MPE;
3011 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3017 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3021 const uint8_t bit1 = 0x1;
3023 struct ixgbe_hw *hw =
3024 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3026 if (ixgbe_vmdq_mode_check(hw) < 0)
3029 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3030 reg = IXGBE_READ_REG(hw, addr);
3038 IXGBE_WRITE_REG(hw, addr,reg);
3044 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3048 const uint8_t bit1 = 0x1;
3050 struct ixgbe_hw *hw =
3051 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3053 if (ixgbe_vmdq_mode_check(hw) < 0)
3056 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3057 reg = IXGBE_READ_REG(hw, addr);
3065 IXGBE_WRITE_REG(hw, addr,reg);
3071 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3072 uint64_t pool_mask, uint8_t vlan_on)
3076 struct ixgbe_hw *hw =
3077 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079 if (ixgbe_vmdq_mode_check(hw) < 0)
3081 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3082 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3083 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3092 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3093 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3094 uint8_t rule_id, uint8_t on)
3096 uint32_t mr_ctl,vlvf;
3097 uint32_t mp_lsb = 0;
3098 uint32_t mv_msb = 0;
3099 uint32_t mv_lsb = 0;
3100 uint32_t mp_msb = 0;
3103 uint64_t vlan_mask = 0;
3105 const uint8_t pool_mask_offset = 32;
3106 const uint8_t vlan_mask_offset = 32;
3107 const uint8_t dst_pool_offset = 8;
3108 const uint8_t rule_mr_offset = 4;
3109 const uint8_t mirror_rule_mask= 0x0F;
3111 struct ixgbe_mirror_info *mr_info =
3112 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3113 struct ixgbe_hw *hw =
3114 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3116 if (ixgbe_vmdq_mode_check(hw) < 0)
3119 /* Check if vlan mask is valid */
3120 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3121 if (mirror_conf->vlan.vlan_mask == 0)
3125 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3126 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3127 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3128 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3129 /* search vlan id related pool vlan filter index */
3130 reg_index = ixgbe_find_vlvf_slot(hw,
3131 mirror_conf->vlan.vlan_id[i]);
3134 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3135 if ((vlvf & IXGBE_VLVF_VIEN) &&
3136 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3137 == mirror_conf->vlan.vlan_id[i]))
3138 vlan_mask |= (1ULL << reg_index);
3145 mv_lsb = vlan_mask & 0xFFFFFFFF;
3146 mv_msb = vlan_mask >> vlan_mask_offset;
3148 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3149 mirror_conf->vlan.vlan_mask;
3150 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3151 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3152 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3153 mirror_conf->vlan.vlan_id[i];
3158 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3159 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3160 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3165 * if enable pool mirror, write related pool mask register,if disable
3166 * pool mirror, clear PFMRVM register
3168 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3170 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3171 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3172 mr_info->mr_conf[rule_id].pool_mask =
3173 mirror_conf->pool_mask;
3178 mr_info->mr_conf[rule_id].pool_mask = 0;
3182 /* read mirror control register and recalculate it */
3183 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3186 mr_ctl |= mirror_conf->rule_type_mask;
3187 mr_ctl &= mirror_rule_mask;
3188 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3190 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3192 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3193 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3195 /* write mirrror control register */
3196 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3198 /* write pool mirrror control register */
3199 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3200 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3201 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3204 /* write VLAN mirrror control register */
3205 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3206 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3207 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3215 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3218 uint32_t lsb_val = 0;
3219 uint32_t msb_val = 0;
3220 const uint8_t rule_mr_offset = 4;
3222 struct ixgbe_hw *hw =
3223 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3224 struct ixgbe_mirror_info *mr_info =
3225 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3227 if (ixgbe_vmdq_mode_check(hw) < 0)
3230 memset(&mr_info->mr_conf[rule_id], 0,
3231 sizeof(struct rte_eth_vmdq_mirror_conf));
3233 /* clear PFVMCTL register */
3234 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3236 /* clear pool mask register */
3237 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3238 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3240 /* clear vlan mask register */
3241 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3242 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3247 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3248 uint16_t queue_idx, uint16_t tx_rate)
3250 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3251 uint32_t rf_dec, rf_int;
3253 uint16_t link_speed = dev->data->dev_link.link_speed;
3255 if (queue_idx >= hw->mac.max_tx_queues)
3259 /* Calculate the rate factor values to set */
3260 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3261 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3262 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3264 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3265 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3266 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3267 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3273 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3274 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3277 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3278 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3279 IXGBE_MAX_JUMBO_FRAME_SIZE))
3280 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3281 IXGBE_MMW_SIZE_JUMBO_FRAME);
3283 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3284 IXGBE_MMW_SIZE_DEFAULT);
3286 /* Set RTTBCNRC of queue X */
3287 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3288 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3289 IXGBE_WRITE_FLUSH(hw);
3294 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3295 uint16_t tx_rate, uint64_t q_msk)
3297 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298 struct ixgbe_vf_info *vfinfo =
3299 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3300 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3301 uint32_t queue_stride =
3302 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3303 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3304 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3305 uint16_t total_rate = 0;
3307 if (queue_end >= hw->mac.max_tx_queues)
3310 if (vfinfo != NULL) {
3311 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3314 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3316 total_rate += vfinfo[vf_idx].tx_rate[idx];
3321 /* Store tx_rate for this vf. */
3322 for (idx = 0; idx < nb_q_per_pool; idx++) {
3323 if (((uint64_t)0x1 << idx) & q_msk) {
3324 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3325 vfinfo[vf].tx_rate[idx] = tx_rate;
3326 total_rate += tx_rate;
3330 if (total_rate > dev->data->dev_link.link_speed) {
3332 * Reset stored TX rate of the VF if it causes exceed
3335 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3339 /* Set RTTBCNRC of each queue/pool for vf X */
3340 for (; queue_idx <= queue_end; queue_idx++) {
3342 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3350 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3351 __attribute__((unused)) uint32_t index,
3352 __attribute__((unused)) uint32_t pool)
3354 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3359 * operation. Trap this case to avoid exhausting the [very limited]
3360 * set of PF resources used to store VF MAC addresses.
3362 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3364 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3367 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3371 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3373 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3375 struct ether_addr *mac_addr;
3380 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3381 * not support the deletion of a given MAC address.
3382 * Instead, it imposes to delete all MAC addresses, then to add again
3383 * all MAC addresses with the exception of the one to be deleted.
3385 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3388 * Add again all MAC addresses, with the exception of the deleted one
3389 * and of the permanent MAC address.
3391 for (i = 0, mac_addr = dev->data->mac_addrs;
3392 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3393 /* Skip the deleted MAC address */
3396 /* Skip NULL MAC addresses */
3397 if (is_zero_ether_addr(mac_addr))
3399 /* Skip the permanent MAC address */
3400 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3402 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3405 "Adding again MAC address "
3406 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3408 mac_addr->addr_bytes[0],
3409 mac_addr->addr_bytes[1],
3410 mac_addr->addr_bytes[2],
3411 mac_addr->addr_bytes[3],
3412 mac_addr->addr_bytes[4],
3413 mac_addr->addr_bytes[5],
3422 * dev: Pointer to struct rte_eth_dev.
3423 * filter: ponter to the filter that will be added.
3424 * rx_queue: the queue id the filter assigned to.
3427 * - On success, zero.
3428 * - On failure, a negative value.
3431 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3432 struct rte_syn_filter *filter, uint16_t rx_queue)
3434 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3437 if (hw->mac.type != ixgbe_mac_82599EB)
3440 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3443 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3445 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3448 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3449 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3451 if (filter->hig_pri)
3452 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3454 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3456 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3464 * dev: Pointer to struct rte_eth_dev.
3467 * - On success, zero.
3468 * - On failure, a negative value.
3471 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3473 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476 if (hw->mac.type != ixgbe_mac_82599EB)
3479 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3481 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3483 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3488 * get the syn filter's info
3491 * dev: Pointer to struct rte_eth_dev.
3492 * filter: ponter to the filter that returns.
3493 * *rx_queue: pointer to the queue id the filter assigned to.
3496 * - On success, zero.
3497 * - On failure, a negative value.
3500 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3501 struct rte_syn_filter *filter, uint16_t *rx_queue)
3504 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3507 if (hw->mac.type != ixgbe_mac_82599EB)
3510 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3511 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3512 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3513 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3520 * add an ethertype filter
3523 * dev: Pointer to struct rte_eth_dev.
3524 * index: the index the filter allocates.
3525 * filter: ponter to the filter that will be added.
3526 * rx_queue: the queue id the filter assigned to.
3529 * - On success, zero.
3530 * - On failure, a negative value.
3533 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3534 uint16_t index, struct rte_ethertype_filter *filter,
3537 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538 uint32_t etqf, etqs = 0;
3540 if (hw->mac.type != ixgbe_mac_82599EB)
3543 if (index >= IXGBE_MAX_ETQF_FILTERS ||
3544 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3547 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3548 if (etqf & IXGBE_ETQF_FILTER_EN)
3549 return -EINVAL; /* filter index is in use. */
3552 etqf |= IXGBE_ETQF_FILTER_EN;
3553 etqf |= (uint32_t)filter->ethertype;
3555 if (filter->priority_en) {
3556 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3558 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3559 etqf |= IXGBE_ETQF_UP_EN;
3561 etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3562 etqs |= IXGBE_ETQS_QUEUE_EN;
3564 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3565 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3570 * remove an ethertype filter
3573 * dev: Pointer to struct rte_eth_dev.
3574 * index: the index the filter allocates.
3577 * - On success, zero.
3578 * - On failure, a negative value.
3581 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3584 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586 if (hw->mac.type != ixgbe_mac_82599EB)
3589 if (index >= IXGBE_MAX_ETQF_FILTERS)
3592 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3593 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3599 * get an ethertype filter
3602 * dev: Pointer to struct rte_eth_dev.
3603 * index: the index the filter allocates.
3604 * filter: ponter to the filter that will be gotten.
3605 * *rx_queue: the ponited of the queue id the filter assigned to.
3608 * - On success, zero.
3609 * - On failure, a negative value.
3612 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3613 uint16_t index, struct rte_ethertype_filter *filter,
3616 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617 uint32_t etqf, etqs;
3619 if (hw->mac.type != ixgbe_mac_82599EB)
3622 if (index >= IXGBE_MAX_ETQF_FILTERS)
3625 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3626 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3627 if (etqf & IXGBE_ETQF_FILTER_EN) {
3628 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3629 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3630 if (filter->priority_en)
3631 filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3632 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3638 static inline enum ixgbe_5tuple_protocol
3639 convert_protocol_type(uint8_t protocol_value)
3641 if (protocol_value == IPPROTO_TCP)
3642 return IXGBE_FILTER_PROTOCOL_TCP;
3643 else if (protocol_value == IPPROTO_UDP)
3644 return IXGBE_FILTER_PROTOCOL_UDP;
3645 else if (protocol_value == IPPROTO_SCTP)
3646 return IXGBE_FILTER_PROTOCOL_SCTP;
3648 return IXGBE_FILTER_PROTOCOL_NONE;
3651 static inline uint8_t
3652 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3654 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3656 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3658 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3659 return IPPROTO_SCTP;
3665 * add a 5tuple filter
3668 * dev: Pointer to struct rte_eth_dev.
3669 * index: the index the filter allocates.
3670 * filter: ponter to the filter that will be added.
3671 * rx_queue: the queue id the filter assigned to.
3674 * - On success, zero.
3675 * - On failure, a negative value.
3678 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3679 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3681 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682 uint32_t ftqf, sdpqf = 0;
3683 uint32_t l34timir = 0;
3684 uint8_t mask = 0xff;
3686 if (hw->mac.type != ixgbe_mac_82599EB)
3689 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3690 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3691 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3692 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3693 return -EINVAL; /* filter index is out of range. */
3695 if (filter->tcp_flags) {
3696 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3700 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3701 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3702 return -EINVAL; /* filter index is in use. */
3705 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3706 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3708 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3709 IXGBE_FTQF_PROTOCOL_MASK);
3710 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3711 IXGBE_FTQF_PRIORITY_SHIFT);
3712 if (filter->src_ip_mask == 0) /* 0 means compare. */
3713 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3714 if (filter->dst_ip_mask == 0)
3715 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3716 if (filter->src_port_mask == 0)
3717 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3718 if (filter->dst_port_mask == 0)
3719 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3720 if (filter->protocol_mask == 0)
3721 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3722 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3723 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3724 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3726 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3727 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3728 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3729 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3731 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3732 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3733 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3738 * remove a 5tuple filter
3741 * dev: Pointer to struct rte_eth_dev.
3742 * index: the index the filter allocates.
3745 * - On success, zero.
3746 * - On failure, a negative value.
3749 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3752 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3754 if (hw->mac.type != ixgbe_mac_82599EB)
3757 if (index >= IXGBE_MAX_FTQF_FILTERS)
3758 return -EINVAL; /* filter index is out of range. */
3760 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3761 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3762 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3763 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3764 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3769 * get a 5tuple filter
3772 * dev: Pointer to struct rte_eth_dev.
3773 * index: the index the filter allocates
3774 * filter: ponter to the filter that returns.
3775 * *rx_queue: pointer of the queue id the filter assigned to.
3778 * - On success, zero.
3779 * - On failure, a negative value.
3782 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3783 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3785 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786 uint32_t sdpqf, ftqf, l34timir;
3788 enum ixgbe_5tuple_protocol proto;
3790 if (hw->mac.type != ixgbe_mac_82599EB)
3793 if (index >= IXGBE_MAX_FTQF_FILTERS)
3794 return -EINVAL; /* filter index is out of range. */
3796 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3797 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3798 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3799 filter->protocol = revert_protocol_type(proto);
3800 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3801 IXGBE_FTQF_PRIORITY_MASK;
3802 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3803 IXGBE_FTQF_5TUPLE_MASK_MASK);
3804 filter->src_ip_mask =
3805 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3806 filter->dst_ip_mask =
3807 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3808 filter->src_port_mask =
3809 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3810 filter->dst_port_mask =
3811 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3812 filter->protocol_mask =
3813 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3815 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3816 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3817 IXGBE_SDPQF_DSTPORT_SHIFT;
3818 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3819 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3820 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3822 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3823 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3824 IXGBE_L34T_IMIR_QUEUE_SHIFT;
3830 static struct rte_driver rte_ixgbe_driver = {
3832 .init = rte_ixgbe_pmd_init,
3835 static struct rte_driver rte_ixgbevf_driver = {
3837 .init = rte_ixgbevf_pmd_init,
3840 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3841 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);