4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
65 #include "ixgbe_logs.h"
66 #include "ixgbe/ixgbe_api.h"
67 #include "ixgbe/ixgbe_vf.h"
68 #include "ixgbe/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
73 * High threshold controlling when to start sending XOFF frames. Must be at
74 * least 8 bytes less than receive packet buffer size. This value is in units
77 #define IXGBE_FC_HI 0x80
80 * Low threshold controlling when to start sending XON frames. This value is
81 * in units of 1024 bytes.
83 #define IXGBE_FC_LO 0x40
85 /* Timer value included in XOFF frames. */
86 #define IXGBE_FC_PAUSE 0x680
88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
89 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
90 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
92 #define IXGBE_MMW_SIZE_DEFAULT 0x4
93 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
95 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
97 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
99 static int eth_ixgbe_dev_init(struct eth_driver *eth_drv,
100 struct rte_eth_dev *eth_dev);
101 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
102 static int ixgbe_dev_start(struct rte_eth_dev *dev);
103 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
104 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
105 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
106 static void ixgbe_dev_close(struct rte_eth_dev *dev);
107 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
108 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
109 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
110 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
111 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
112 int wait_to_complete);
113 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
114 struct rte_eth_stats *stats);
115 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
116 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
120 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
121 struct rte_eth_dev_info *dev_info);
123 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
125 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
126 uint16_t vlan_id, int on);
127 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
128 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
129 uint16_t queue, bool on);
130 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
132 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
133 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
134 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
135 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
136 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
138 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
139 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
140 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
141 struct rte_eth_fc_conf *fc_conf);
142 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
143 struct rte_eth_fc_conf *fc_conf);
144 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
145 struct rte_eth_pfc_conf *pfc_conf);
146 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta *reta_conf);
148 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
149 struct rte_eth_rss_reta *reta_conf);
150 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
151 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
152 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
153 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
154 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
156 static void ixgbe_dev_interrupt_delayed_handler(void *param);
157 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
158 uint32_t index, uint32_t pool);
159 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
160 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
162 /* For Virtual Function support */
163 static int eth_ixgbevf_dev_init(struct eth_driver *eth_drv,
164 struct rte_eth_dev *eth_dev);
165 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
166 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
167 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
168 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
169 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
170 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
171 struct rte_eth_stats *stats);
172 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
173 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
174 uint16_t vlan_id, int on);
175 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
176 uint16_t queue, int on);
177 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
178 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
180 /* For Eth VMDQ APIs support */
181 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
182 ether_addr* mac_addr,uint8_t on);
183 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
184 static int ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
185 uint16_t rx_mask, uint8_t on);
186 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
187 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
188 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
189 uint64_t pool_mask,uint8_t vlan_on);
190 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
191 struct rte_eth_vmdq_mirror_conf *mirror_conf,
192 uint8_t rule_id, uint8_t on);
193 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
196 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
197 uint16_t queue_idx, uint16_t tx_rate);
198 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
199 uint16_t tx_rate, uint64_t q_msk);
201 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
202 struct ether_addr *mac_addr,
203 uint32_t index, uint32_t pool);
204 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
205 static int ixgbe_add_syn_filter(struct rte_eth_dev *dev,
206 struct rte_syn_filter *filter, uint16_t rx_queue);
207 static int ixgbe_remove_syn_filter(struct rte_eth_dev *dev);
208 static int ixgbe_get_syn_filter(struct rte_eth_dev *dev,
209 struct rte_syn_filter *filter, uint16_t *rx_queue);
210 static int ixgbe_add_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
211 struct rte_ethertype_filter *filter, uint16_t rx_queue);
212 static int ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
214 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev, uint16_t index,
215 struct rte_ethertype_filter *filter, uint16_t *rx_queue);
216 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
217 struct rte_5tuple_filter *filter, uint16_t rx_queue);
218 static int ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
220 static int ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
221 struct rte_5tuple_filter *filter, uint16_t *rx_queue);
223 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
226 * Define VF Stats MACRO for Non "cleared on read" register
228 #define UPDATE_VF_STAT(reg, last, cur) \
230 u32 latest = IXGBE_READ_REG(hw, reg); \
231 cur += latest - last; \
235 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
237 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
238 u64 new_msb = IXGBE_READ_REG(hw, msb); \
239 u64 latest = ((new_msb << 32) | new_lsb); \
240 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
244 #define IXGBE_SET_HWSTRIP(h, q) do{\
245 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
246 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
247 (h)->bitmap[idx] |= 1 << bit;\
250 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
251 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
252 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
253 (h)->bitmap[idx] &= ~(1 << bit);\
256 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
257 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
258 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
259 (r) = (h)->bitmap[idx] >> bit & 1;\
263 * The set of PCI devices this driver supports
265 static struct rte_pci_id pci_id_ixgbe_map[] = {
267 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
268 #include "rte_pci_dev_ids.h"
270 { .vendor_id = 0, /* sentinel */ },
275 * The set of PCI devices this driver supports (for 82599 VF)
277 static struct rte_pci_id pci_id_ixgbevf_map[] = {
279 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
280 #include "rte_pci_dev_ids.h"
281 { .vendor_id = 0, /* sentinel */ },
285 static struct eth_dev_ops ixgbe_eth_dev_ops = {
286 .dev_configure = ixgbe_dev_configure,
287 .dev_start = ixgbe_dev_start,
288 .dev_stop = ixgbe_dev_stop,
289 .dev_set_link_up = ixgbe_dev_set_link_up,
290 .dev_set_link_down = ixgbe_dev_set_link_down,
291 .dev_close = ixgbe_dev_close,
292 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
293 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
294 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
295 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
296 .link_update = ixgbe_dev_link_update,
297 .stats_get = ixgbe_dev_stats_get,
298 .stats_reset = ixgbe_dev_stats_reset,
299 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
300 .dev_infos_get = ixgbe_dev_info_get,
301 .mtu_set = ixgbe_dev_mtu_set,
302 .vlan_filter_set = ixgbe_vlan_filter_set,
303 .vlan_tpid_set = ixgbe_vlan_tpid_set,
304 .vlan_offload_set = ixgbe_vlan_offload_set,
305 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
306 .rx_queue_start = ixgbe_dev_rx_queue_start,
307 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
308 .tx_queue_start = ixgbe_dev_tx_queue_start,
309 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
310 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
311 .rx_queue_release = ixgbe_dev_rx_queue_release,
312 .rx_queue_count = ixgbe_dev_rx_queue_count,
313 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
314 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
315 .tx_queue_release = ixgbe_dev_tx_queue_release,
316 .dev_led_on = ixgbe_dev_led_on,
317 .dev_led_off = ixgbe_dev_led_off,
318 .flow_ctrl_get = ixgbe_flow_ctrl_get,
319 .flow_ctrl_set = ixgbe_flow_ctrl_set,
320 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
321 .mac_addr_add = ixgbe_add_rar,
322 .mac_addr_remove = ixgbe_remove_rar,
323 .uc_hash_table_set = ixgbe_uc_hash_table_set,
324 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
325 .mirror_rule_set = ixgbe_mirror_rule_set,
326 .mirror_rule_reset = ixgbe_mirror_rule_reset,
327 .set_vf_rx_mode = ixgbe_set_pool_rx_mode,
328 .set_vf_rx = ixgbe_set_pool_rx,
329 .set_vf_tx = ixgbe_set_pool_tx,
330 .set_vf_vlan_filter = ixgbe_set_pool_vlan_filter,
331 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
332 .set_vf_rate_limit = ixgbe_set_vf_rate_limit,
333 .fdir_add_signature_filter = ixgbe_fdir_add_signature_filter,
334 .fdir_update_signature_filter = ixgbe_fdir_update_signature_filter,
335 .fdir_remove_signature_filter = ixgbe_fdir_remove_signature_filter,
336 .fdir_infos_get = ixgbe_fdir_info_get,
337 .fdir_add_perfect_filter = ixgbe_fdir_add_perfect_filter,
338 .fdir_update_perfect_filter = ixgbe_fdir_update_perfect_filter,
339 .fdir_remove_perfect_filter = ixgbe_fdir_remove_perfect_filter,
340 .fdir_set_masks = ixgbe_fdir_set_masks,
341 .reta_update = ixgbe_dev_rss_reta_update,
342 .reta_query = ixgbe_dev_rss_reta_query,
343 #ifdef RTE_NIC_BYPASS
344 .bypass_init = ixgbe_bypass_init,
345 .bypass_state_set = ixgbe_bypass_state_store,
346 .bypass_state_show = ixgbe_bypass_state_show,
347 .bypass_event_set = ixgbe_bypass_event_store,
348 .bypass_event_show = ixgbe_bypass_event_show,
349 .bypass_wd_timeout_set = ixgbe_bypass_wd_timeout_store,
350 .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
351 .bypass_ver_show = ixgbe_bypass_ver_show,
352 .bypass_wd_reset = ixgbe_bypass_wd_reset,
353 #endif /* RTE_NIC_BYPASS */
354 .rss_hash_update = ixgbe_dev_rss_hash_update,
355 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
356 .add_syn_filter = ixgbe_add_syn_filter,
357 .remove_syn_filter = ixgbe_remove_syn_filter,
358 .get_syn_filter = ixgbe_get_syn_filter,
359 .add_ethertype_filter = ixgbe_add_ethertype_filter,
360 .remove_ethertype_filter = ixgbe_remove_ethertype_filter,
361 .get_ethertype_filter = ixgbe_get_ethertype_filter,
362 .add_5tuple_filter = ixgbe_add_5tuple_filter,
363 .remove_5tuple_filter = ixgbe_remove_5tuple_filter,
364 .get_5tuple_filter = ixgbe_get_5tuple_filter,
368 * dev_ops for virtual function, bare necessities for basic vf
369 * operation have been implemented
371 static struct eth_dev_ops ixgbevf_eth_dev_ops = {
373 .dev_configure = ixgbevf_dev_configure,
374 .dev_start = ixgbevf_dev_start,
375 .dev_stop = ixgbevf_dev_stop,
376 .link_update = ixgbe_dev_link_update,
377 .stats_get = ixgbevf_dev_stats_get,
378 .stats_reset = ixgbevf_dev_stats_reset,
379 .dev_close = ixgbevf_dev_close,
380 .dev_infos_get = ixgbe_dev_info_get,
381 .mtu_set = ixgbevf_dev_set_mtu,
382 .vlan_filter_set = ixgbevf_vlan_filter_set,
383 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
384 .vlan_offload_set = ixgbevf_vlan_offload_set,
385 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
386 .rx_queue_release = ixgbe_dev_rx_queue_release,
387 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
388 .tx_queue_release = ixgbe_dev_tx_queue_release,
389 .mac_addr_add = ixgbevf_add_mac_addr,
390 .mac_addr_remove = ixgbevf_remove_mac_addr,
394 * Atomically reads the link status information from global
395 * structure rte_eth_dev.
398 * - Pointer to the structure rte_eth_dev to read from.
399 * - Pointer to the buffer to be saved with the link status.
402 * - On success, zero.
403 * - On failure, negative value.
406 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
407 struct rte_eth_link *link)
409 struct rte_eth_link *dst = link;
410 struct rte_eth_link *src = &(dev->data->dev_link);
412 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
413 *(uint64_t *)src) == 0)
420 * Atomically writes the link status information into global
421 * structure rte_eth_dev.
424 * - Pointer to the structure rte_eth_dev to read from.
425 * - Pointer to the buffer to be saved with the link status.
428 * - On success, zero.
429 * - On failure, negative value.
432 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
433 struct rte_eth_link *link)
435 struct rte_eth_link *dst = &(dev->data->dev_link);
436 struct rte_eth_link *src = link;
438 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
439 *(uint64_t *)src) == 0)
446 * This function is the same as ixgbe_is_sfp() in ixgbe/ixgbe.h.
449 ixgbe_is_sfp(struct ixgbe_hw *hw)
451 switch (hw->phy.type) {
452 case ixgbe_phy_sfp_avago:
453 case ixgbe_phy_sfp_ftl:
454 case ixgbe_phy_sfp_intel:
455 case ixgbe_phy_sfp_unknown:
456 case ixgbe_phy_sfp_passive_tyco:
457 case ixgbe_phy_sfp_passive_unknown:
464 static inline int32_t
465 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
470 status = ixgbe_reset_hw(hw);
472 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
473 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
474 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
475 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
476 IXGBE_WRITE_FLUSH(hw);
482 ixgbe_enable_intr(struct rte_eth_dev *dev)
484 struct ixgbe_interrupt *intr =
485 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
486 struct ixgbe_hw *hw =
487 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
489 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
490 IXGBE_WRITE_FLUSH(hw);
494 * This function is based on ixgbe_disable_intr() in ixgbe/ixgbe.h.
497 ixgbe_disable_intr(struct ixgbe_hw *hw)
499 PMD_INIT_FUNC_TRACE();
501 if (hw->mac.type == ixgbe_mac_82598EB) {
502 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
504 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
505 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
506 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
508 IXGBE_WRITE_FLUSH(hw);
512 * This function resets queue statistics mapping registers.
513 * From Niantic datasheet, Initialization of Statistics section:
514 * "...if software requires the queue counters, the RQSMR and TQSM registers
515 * must be re-programmed following a device reset.
518 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
522 for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
523 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
524 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
530 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
535 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
536 #define NB_QMAP_FIELDS_PER_QSM_REG 4
537 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
539 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
540 struct ixgbe_stat_mapping_registers *stat_mappings =
541 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
542 uint32_t qsmr_mask = 0;
543 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
547 if ((hw->mac.type != ixgbe_mac_82599EB) && (hw->mac.type != ixgbe_mac_X540))
550 PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
551 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
554 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
555 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
556 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
559 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
561 /* Now clear any previous stat_idx set */
562 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
564 stat_mappings->tqsm[n] &= ~clearing_mask;
566 stat_mappings->rqsmr[n] &= ~clearing_mask;
568 q_map = (uint32_t)stat_idx;
569 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
570 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
572 stat_mappings->tqsm[n] |= qsmr_mask;
574 stat_mappings->rqsmr[n] |= qsmr_mask;
576 PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
577 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
579 PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
580 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
582 /* Now write the mapping in the appropriate register */
584 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
585 stat_mappings->rqsmr[n], n);
586 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
589 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
590 stat_mappings->tqsm[n], n);
591 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
597 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
599 struct ixgbe_stat_mapping_registers *stat_mappings =
600 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
601 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
604 /* write whatever was in stat mapping table to the NIC */
605 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
607 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
610 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
615 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
618 struct ixgbe_dcb_tc_config *tc;
619 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
621 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
622 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
623 for (i = 0; i < dcb_max_tc; i++) {
624 tc = &dcb_config->tc_config[i];
625 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
626 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
627 (uint8_t)(100/dcb_max_tc + (i & 1));
628 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
629 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
630 (uint8_t)(100/dcb_max_tc + (i & 1));
631 tc->pfc = ixgbe_dcb_pfc_disabled;
634 /* Initialize default user to priority mapping, UPx->TC0 */
635 tc = &dcb_config->tc_config[0];
636 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
637 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
638 for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
639 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
640 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
642 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
643 dcb_config->pfc_mode_enable = false;
644 dcb_config->vt_mode = true;
645 dcb_config->round_robin_enable = false;
646 /* support all DCB capabilities in 82599 */
647 dcb_config->support.capabilities = 0xFF;
649 /*we only support 4 Tcs for X540*/
650 if (hw->mac.type == ixgbe_mac_X540) {
651 dcb_config->num_tcs.pg_tcs = 4;
652 dcb_config->num_tcs.pfc_tcs = 4;
657 * Ensure that all locks are released before first NVM or PHY access
660 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
665 * Phy lock should not fail in this early stage. If this is the case,
666 * it is due to an improper exit of the application.
667 * So force the release of the faulty lock. Release of common lock
668 * is done automatically by swfw_sync function.
670 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
671 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
672 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
674 ixgbe_release_swfw_semaphore(hw, mask);
677 * These ones are more tricky since they are common to all ports; but
678 * swfw_sync retries last long enough (1s) to be almost sure that if
679 * lock can not be taken it is due to an improper lock of the
682 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
683 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
684 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
686 ixgbe_release_swfw_semaphore(hw, mask);
690 * This function is based on code in ixgbe_attach() in ixgbe/ixgbe.c.
691 * It returns 0 on success.
694 eth_ixgbe_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
695 struct rte_eth_dev *eth_dev)
697 struct rte_pci_device *pci_dev;
698 struct ixgbe_hw *hw =
699 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
700 struct ixgbe_vfta * shadow_vfta =
701 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
702 struct ixgbe_hwstrip *hwstrip =
703 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
704 struct ixgbe_dcb_config *dcb_config =
705 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
710 PMD_INIT_FUNC_TRACE();
712 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
713 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
714 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
716 /* for secondary processes, we don't initialise any further as primary
717 * has already done this work. Only check we don't need a different
719 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
720 if (eth_dev->data->scattered_rx)
721 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
724 pci_dev = eth_dev->pci_dev;
726 /* Vendor and Device ID need to be set before init of shared code */
727 hw->device_id = pci_dev->id.device_id;
728 hw->vendor_id = pci_dev->id.vendor_id;
729 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
730 #ifdef RTE_LIBRTE_IXGBE_ALLOW_UNSUPPORTED_SFP
731 hw->allow_unsupported_sfp = 1;
734 /* Initialize the shared code (base driver) */
735 #ifdef RTE_NIC_BYPASS
736 diag = ixgbe_bypass_init_shared_code(hw);
738 diag = ixgbe_init_shared_code(hw);
739 #endif /* RTE_NIC_BYPASS */
741 if (diag != IXGBE_SUCCESS) {
742 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
746 /* pick up the PCI bus settings for reporting later */
747 ixgbe_get_bus_info(hw);
749 /* Unlock any pending hardware semaphore */
750 ixgbe_swfw_lock_reset(hw);
752 /* Initialize DCB configuration*/
753 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
754 ixgbe_dcb_init(hw,dcb_config);
755 /* Get Hardware Flow Control setting */
756 hw->fc.requested_mode = ixgbe_fc_full;
757 hw->fc.current_mode = ixgbe_fc_full;
758 hw->fc.pause_time = IXGBE_FC_PAUSE;
759 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
760 hw->fc.low_water[i] = IXGBE_FC_LO;
761 hw->fc.high_water[i] = IXGBE_FC_HI;
765 /* Make sure we have a good EEPROM before we read from it */
766 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
767 if (diag != IXGBE_SUCCESS) {
768 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
772 #ifdef RTE_NIC_BYPASS
773 diag = ixgbe_bypass_init_hw(hw);
775 diag = ixgbe_init_hw(hw);
776 #endif /* RTE_NIC_BYPASS */
779 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
780 * is called too soon after the kernel driver unbinding/binding occurs.
781 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
782 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
783 * also called. See ixgbe_identify_phy_82599(). The reason for the
784 * failure is not known, and only occuts when virtualisation features
785 * are disabled in the bios. A delay of 100ms was found to be enough by
786 * trial-and-error, and is doubled to be safe.
788 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
790 diag = ixgbe_init_hw(hw);
793 if (diag == IXGBE_ERR_EEPROM_VERSION) {
794 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
795 "LOM. Please be aware there may be issues associated "
796 "with your hardware.");
797 PMD_INIT_LOG(ERR, "If you are experiencing problems "
798 "please contact your Intel or hardware representative "
799 "who provided you with this hardware.");
800 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
801 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
803 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
807 /* disable interrupt */
808 ixgbe_disable_intr(hw);
810 /* reset mappings for queue statistics hw counters*/
811 ixgbe_reset_qstat_mappings(hw);
813 /* Allocate memory for storing MAC addresses */
814 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
815 hw->mac.num_rar_entries, 0);
816 if (eth_dev->data->mac_addrs == NULL) {
818 "Failed to allocate %u bytes needed to store "
820 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
823 /* Copy the permanent MAC address */
824 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
825 ð_dev->data->mac_addrs[0]);
827 /* Allocate memory for storing hash filter MAC addresses */
828 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
829 IXGBE_VMDQ_NUM_UC_MAC, 0);
830 if (eth_dev->data->hash_mac_addrs == NULL) {
832 "Failed to allocate %d bytes needed to store MAC addresses",
833 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
837 /* initialize the vfta */
838 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
840 /* initialize the hw strip bitmap*/
841 memset(hwstrip, 0, sizeof(*hwstrip));
843 /* initialize PF if max_vfs not zero */
844 ixgbe_pf_host_init(eth_dev);
846 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
847 /* let hardware know driver is loaded */
848 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
849 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
850 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
851 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
852 IXGBE_WRITE_FLUSH(hw);
854 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
855 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
856 (int) hw->mac.type, (int) hw->phy.type,
857 (int) hw->phy.sfp_type);
859 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
860 (int) hw->mac.type, (int) hw->phy.type);
862 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
863 eth_dev->data->port_id, pci_dev->id.vendor_id,
864 pci_dev->id.device_id);
866 rte_intr_callback_register(&(pci_dev->intr_handle),
867 ixgbe_dev_interrupt_handler, (void *)eth_dev);
869 /* enable uio intr after callback register */
870 rte_intr_enable(&(pci_dev->intr_handle));
872 /* enable support intr */
873 ixgbe_enable_intr(eth_dev);
880 * Negotiate mailbox API version with the PF.
881 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
882 * Then we try to negotiate starting with the most recent one.
883 * If all negotiation attempts fail, then we will proceed with
884 * the default one (ixgbe_mbox_api_10).
887 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
891 /* start with highest supported, proceed down */
892 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
898 i != RTE_DIM(sup_ver) &&
899 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
905 generate_random_mac_addr(struct ether_addr *mac_addr)
909 /* Set Organizationally Unique Identifier (OUI) prefix. */
910 mac_addr->addr_bytes[0] = 0x00;
911 mac_addr->addr_bytes[1] = 0x09;
912 mac_addr->addr_bytes[2] = 0xC0;
913 /* Force indication of locally assigned MAC address. */
914 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
915 /* Generate the last 3 bytes of the MAC address with a random number. */
917 memcpy(&mac_addr->addr_bytes[3], &random, 3);
921 * Virtual Function device init
924 eth_ixgbevf_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
925 struct rte_eth_dev *eth_dev)
929 struct rte_pci_device *pci_dev;
930 struct ixgbe_hw *hw =
931 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
932 struct ixgbe_vfta * shadow_vfta =
933 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
934 struct ixgbe_hwstrip *hwstrip =
935 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
936 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
938 PMD_INIT_FUNC_TRACE();
940 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
941 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
942 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
944 /* for secondary processes, we don't initialise any further as primary
945 * has already done this work. Only check we don't need a different
947 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
948 if (eth_dev->data->scattered_rx)
949 eth_dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
953 pci_dev = eth_dev->pci_dev;
955 hw->device_id = pci_dev->id.device_id;
956 hw->vendor_id = pci_dev->id.vendor_id;
957 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
959 /* initialize the vfta */
960 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
962 /* initialize the hw strip bitmap*/
963 memset(hwstrip, 0, sizeof(*hwstrip));
965 /* Initialize the shared code (base driver) */
966 diag = ixgbe_init_shared_code(hw);
967 if (diag != IXGBE_SUCCESS) {
968 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
972 /* init_mailbox_params */
973 hw->mbx.ops.init_params(hw);
975 /* Disable the interrupts for VF */
976 ixgbevf_intr_disable(hw);
978 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
979 diag = hw->mac.ops.reset_hw(hw);
982 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
983 * the underlying PF driver has not assigned a MAC address to the VF.
984 * In this case, assign a random MAC address.
986 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
987 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
991 /* negotiate mailbox API version to use with the PF. */
992 ixgbevf_negotiate_api(hw);
994 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
995 ixgbevf_get_queues(hw, &tcs, &tc);
997 /* Allocate memory for storing MAC addresses */
998 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
999 hw->mac.num_rar_entries, 0);
1000 if (eth_dev->data->mac_addrs == NULL) {
1002 "Failed to allocate %u bytes needed to store "
1004 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1008 /* Generate a random MAC address, if none was assigned by PF. */
1009 if (is_zero_ether_addr(perm_addr)) {
1010 generate_random_mac_addr(perm_addr);
1011 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1013 rte_free(eth_dev->data->mac_addrs);
1014 eth_dev->data->mac_addrs = NULL;
1017 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1018 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1019 "%02x:%02x:%02x:%02x:%02x:%02x",
1020 perm_addr->addr_bytes[0],
1021 perm_addr->addr_bytes[1],
1022 perm_addr->addr_bytes[2],
1023 perm_addr->addr_bytes[3],
1024 perm_addr->addr_bytes[4],
1025 perm_addr->addr_bytes[5]);
1028 /* Copy the permanent MAC address */
1029 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1031 /* reset the hardware with the new settings */
1032 diag = hw->mac.ops.start_hw(hw);
1038 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1042 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1043 eth_dev->data->port_id, pci_dev->id.vendor_id,
1044 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1049 static struct eth_driver rte_ixgbe_pmd = {
1051 .name = "rte_ixgbe_pmd",
1052 .id_table = pci_id_ixgbe_map,
1053 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1055 .eth_dev_init = eth_ixgbe_dev_init,
1056 .dev_private_size = sizeof(struct ixgbe_adapter),
1060 * virtual function driver struct
1062 static struct eth_driver rte_ixgbevf_pmd = {
1064 .name = "rte_ixgbevf_pmd",
1065 .id_table = pci_id_ixgbevf_map,
1066 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1068 .eth_dev_init = eth_ixgbevf_dev_init,
1069 .dev_private_size = sizeof(struct ixgbe_adapter),
1073 * Driver initialization routine.
1074 * Invoked once at EAL init time.
1075 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1078 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1080 PMD_INIT_FUNC_TRACE();
1082 rte_eth_driver_register(&rte_ixgbe_pmd);
1087 * VF Driver initialization routine.
1088 * Invoked one at EAL init time.
1089 * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1092 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1094 PMD_INIT_FUNC_TRACE();
1096 rte_eth_driver_register(&rte_ixgbevf_pmd);
1101 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1103 struct ixgbe_hw *hw =
1104 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct ixgbe_vfta * shadow_vfta =
1106 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1111 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1112 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1113 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1118 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1120 /* update local VFTA copy */
1121 shadow_vfta->vfta[vid_idx] = vfta;
1127 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1130 ixgbe_vlan_hw_strip_enable(dev, queue);
1132 ixgbe_vlan_hw_strip_disable(dev, queue);
1136 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1138 struct ixgbe_hw *hw =
1139 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1141 /* Only the high 16-bits is valid */
1142 IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1146 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1148 struct ixgbe_hw *hw =
1149 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152 PMD_INIT_FUNC_TRACE();
1154 /* Filter Table Disable */
1155 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1156 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1158 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1162 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1164 struct ixgbe_hw *hw =
1165 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1166 struct ixgbe_vfta * shadow_vfta =
1167 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1171 PMD_INIT_FUNC_TRACE();
1173 /* Filter Table Enable */
1174 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1175 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1176 vlnctrl |= IXGBE_VLNCTRL_VFE;
1178 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1180 /* write whatever is in local vfta copy */
1181 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1182 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1186 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1188 struct ixgbe_hwstrip *hwstrip =
1189 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1191 if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1195 IXGBE_SET_HWSTRIP(hwstrip, queue);
1197 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1201 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1203 struct ixgbe_hw *hw =
1204 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1207 PMD_INIT_FUNC_TRACE();
1209 if (hw->mac.type == ixgbe_mac_82598EB) {
1210 /* No queue level support */
1211 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1215 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1216 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1217 ctrl &= ~IXGBE_RXDCTL_VME;
1218 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1220 /* record those setting for HW strip per queue */
1221 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1225 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1227 struct ixgbe_hw *hw =
1228 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231 PMD_INIT_FUNC_TRACE();
1233 if (hw->mac.type == ixgbe_mac_82598EB) {
1234 /* No queue level supported */
1235 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1239 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1240 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1241 ctrl |= IXGBE_RXDCTL_VME;
1242 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1244 /* record those setting for HW strip per queue */
1245 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1249 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1251 struct ixgbe_hw *hw =
1252 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1256 PMD_INIT_FUNC_TRACE();
1258 if (hw->mac.type == ixgbe_mac_82598EB) {
1259 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1260 ctrl &= ~IXGBE_VLNCTRL_VME;
1261 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1264 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1265 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1266 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1267 ctrl &= ~IXGBE_RXDCTL_VME;
1268 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1270 /* record those setting for HW strip per queue */
1271 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1277 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1279 struct ixgbe_hw *hw =
1280 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1284 PMD_INIT_FUNC_TRACE();
1286 if (hw->mac.type == ixgbe_mac_82598EB) {
1287 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1288 ctrl |= IXGBE_VLNCTRL_VME;
1289 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1292 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1293 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1294 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1295 ctrl |= IXGBE_RXDCTL_VME;
1296 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1298 /* record those setting for HW strip per queue */
1299 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1305 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1307 struct ixgbe_hw *hw =
1308 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1311 PMD_INIT_FUNC_TRACE();
1313 /* DMATXCTRL: Geric Double VLAN Disable */
1314 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1315 ctrl &= ~IXGBE_DMATXCTL_GDV;
1316 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1318 /* CTRL_EXT: Global Double VLAN Disable */
1319 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1320 ctrl &= ~IXGBE_EXTENDED_VLAN;
1321 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1326 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1328 struct ixgbe_hw *hw =
1329 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332 PMD_INIT_FUNC_TRACE();
1334 /* DMATXCTRL: Geric Double VLAN Enable */
1335 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1336 ctrl |= IXGBE_DMATXCTL_GDV;
1337 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1339 /* CTRL_EXT: Global Double VLAN Enable */
1340 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1341 ctrl |= IXGBE_EXTENDED_VLAN;
1342 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1345 * VET EXT field in the EXVET register = 0x8100 by default
1346 * So no need to change. Same to VT field of DMATXCTL register
1351 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1353 if(mask & ETH_VLAN_STRIP_MASK){
1354 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1355 ixgbe_vlan_hw_strip_enable_all(dev);
1357 ixgbe_vlan_hw_strip_disable_all(dev);
1360 if(mask & ETH_VLAN_FILTER_MASK){
1361 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1362 ixgbe_vlan_hw_filter_enable(dev);
1364 ixgbe_vlan_hw_filter_disable(dev);
1367 if(mask & ETH_VLAN_EXTEND_MASK){
1368 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1369 ixgbe_vlan_hw_extend_enable(dev);
1371 ixgbe_vlan_hw_extend_disable(dev);
1376 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1378 struct ixgbe_hw *hw =
1379 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1381 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1382 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1383 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1387 ixgbe_dev_configure(struct rte_eth_dev *dev)
1389 struct ixgbe_interrupt *intr =
1390 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1392 PMD_INIT_FUNC_TRACE();
1394 /* set flag to update link status after init */
1395 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1401 * Configure device link speed and setup link.
1402 * It returns 0 on success.
1405 ixgbe_dev_start(struct rte_eth_dev *dev)
1407 struct ixgbe_hw *hw =
1408 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409 struct ixgbe_vf_info *vfinfo =
1410 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1411 int err, link_up = 0, negotiate = 0;
1417 PMD_INIT_FUNC_TRACE();
1419 /* IXGBE devices don't support half duplex */
1420 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1421 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1422 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1423 dev->data->dev_conf.link_duplex,
1424 dev->data->port_id);
1429 hw->adapter_stopped = FALSE;
1430 ixgbe_stop_adapter(hw);
1432 /* reinitialize adapter
1433 * this calls reset and start */
1434 status = ixgbe_pf_reset_hw(hw);
1437 hw->mac.ops.start_hw(hw);
1439 /* configure PF module if SRIOV enabled */
1440 ixgbe_pf_host_configure(dev);
1442 /* initialize transmission unit */
1443 ixgbe_dev_tx_init(dev);
1445 /* This can fail when allocating mbufs for descriptor rings */
1446 err = ixgbe_dev_rx_init(dev);
1448 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1452 ixgbe_dev_rxtx_start(dev);
1454 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1455 err = hw->mac.ops.setup_sfp(hw);
1460 /* Turn on the laser */
1461 ixgbe_enable_tx_laser(hw);
1463 /* Skip link setup if loopback mode is enabled for 82599. */
1464 if (hw->mac.type == ixgbe_mac_82599EB &&
1465 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1466 goto skip_link_setup;
1468 err = ixgbe_check_link(hw, &speed, &link_up, 0);
1471 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1475 switch(dev->data->dev_conf.link_speed) {
1476 case ETH_LINK_SPEED_AUTONEG:
1477 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1478 IXGBE_LINK_SPEED_82599_AUTONEG :
1479 IXGBE_LINK_SPEED_82598_AUTONEG;
1481 case ETH_LINK_SPEED_100:
1483 * Invalid for 82598 but error will be detected by
1484 * ixgbe_setup_link()
1486 speed = IXGBE_LINK_SPEED_100_FULL;
1488 case ETH_LINK_SPEED_1000:
1489 speed = IXGBE_LINK_SPEED_1GB_FULL;
1491 case ETH_LINK_SPEED_10000:
1492 speed = IXGBE_LINK_SPEED_10GB_FULL;
1495 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1496 dev->data->dev_conf.link_speed,
1497 dev->data->port_id);
1501 err = ixgbe_setup_link(hw, speed, link_up);
1507 /* check if lsc interrupt is enabled */
1508 if (dev->data->dev_conf.intr_conf.lsc != 0)
1509 ixgbe_dev_lsc_interrupt_setup(dev);
1511 /* resume enabled intr since hw reset */
1512 ixgbe_enable_intr(dev);
1514 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1515 ETH_VLAN_EXTEND_MASK;
1516 ixgbe_vlan_offload_set(dev, mask);
1518 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1519 /* Enable vlan filtering for VMDq */
1520 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1523 /* Configure DCB hw */
1524 ixgbe_configure_dcb(dev);
1526 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1527 err = ixgbe_fdir_configure(dev);
1532 /* Restore vf rate limit */
1533 if (vfinfo != NULL) {
1534 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1535 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1536 if (vfinfo[vf].tx_rate[idx] != 0)
1537 ixgbe_set_vf_rate_limit(dev, vf,
1538 vfinfo[vf].tx_rate[idx],
1542 ixgbe_restore_statistics_mapping(dev);
1547 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1548 ixgbe_dev_clear_queues(dev);
1553 * Stop device: disable rx and tx functions to allow for reconfiguring.
1556 ixgbe_dev_stop(struct rte_eth_dev *dev)
1558 struct rte_eth_link link;
1559 struct ixgbe_hw *hw =
1560 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561 struct ixgbe_vf_info *vfinfo =
1562 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1565 PMD_INIT_FUNC_TRACE();
1567 /* disable interrupts */
1568 ixgbe_disable_intr(hw);
1571 ixgbe_pf_reset_hw(hw);
1572 hw->adapter_stopped = FALSE;
1575 ixgbe_stop_adapter(hw);
1577 for (vf = 0; vfinfo != NULL &&
1578 vf < dev->pci_dev->max_vfs; vf++)
1579 vfinfo[vf].clear_to_send = false;
1581 /* Turn off the laser */
1582 ixgbe_disable_tx_laser(hw);
1584 ixgbe_dev_clear_queues(dev);
1586 /* Clear recorded link status */
1587 memset(&link, 0, sizeof(link));
1588 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1592 * Set device link up: enable tx laser.
1595 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1597 struct ixgbe_hw *hw =
1598 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 if (hw->mac.type == ixgbe_mac_82599EB) {
1600 #ifdef RTE_NIC_BYPASS
1601 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1602 /* Not suported in bypass mode */
1603 PMD_INIT_LOG(ERR, "Set link up is not supported "
1604 "by device id 0x%x", hw->device_id);
1608 /* Turn on the laser */
1609 ixgbe_enable_tx_laser(hw);
1613 PMD_INIT_LOG(ERR, "Set link up is not supported by device id 0x%x",
1619 * Set device link down: disable tx laser.
1622 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1624 struct ixgbe_hw *hw =
1625 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626 if (hw->mac.type == ixgbe_mac_82599EB) {
1627 #ifdef RTE_NIC_BYPASS
1628 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1629 /* Not suported in bypass mode */
1630 PMD_INIT_LOG(ERR, "Set link down is not supported "
1631 "by device id 0x%x", hw->device_id);
1635 /* Turn off the laser */
1636 ixgbe_disable_tx_laser(hw);
1640 PMD_INIT_LOG(ERR, "Set link down is not supported by device id 0x%x",
1646 * Reest and stop device.
1649 ixgbe_dev_close(struct rte_eth_dev *dev)
1651 struct ixgbe_hw *hw =
1652 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 PMD_INIT_FUNC_TRACE();
1656 ixgbe_pf_reset_hw(hw);
1658 ixgbe_dev_stop(dev);
1659 hw->adapter_stopped = 1;
1661 ixgbe_disable_pcie_master(hw);
1663 /* reprogram the RAR[0] in case user changed it. */
1664 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1668 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
1671 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1673 struct ixgbe_hw *hw =
1674 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675 struct ixgbe_hw_stats *hw_stats =
1676 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1677 uint32_t bprc, lxon, lxoff, total;
1678 uint64_t total_missed_rx, total_qbrc, total_qprc;
1681 total_missed_rx = 0;
1685 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1686 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1687 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1688 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1690 for (i = 0; i < 8; i++) {
1692 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1693 /* global total per queue */
1694 hw_stats->mpc[i] += mp;
1695 /* Running comprehensive total for stats display */
1696 total_missed_rx += hw_stats->mpc[i];
1697 if (hw->mac.type == ixgbe_mac_82598EB)
1698 hw_stats->rnbc[i] +=
1699 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1700 hw_stats->pxontxc[i] +=
1701 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1702 hw_stats->pxonrxc[i] +=
1703 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1704 hw_stats->pxofftxc[i] +=
1705 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1706 hw_stats->pxoffrxc[i] +=
1707 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1708 hw_stats->pxon2offc[i] +=
1709 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1711 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1712 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1713 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1714 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1715 hw_stats->qbrc[i] +=
1716 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1717 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1718 hw_stats->qbtc[i] +=
1719 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1720 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1722 total_qprc += hw_stats->qprc[i];
1723 total_qbrc += hw_stats->qbrc[i];
1725 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1726 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1727 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1729 /* Note that gprc counts missed packets */
1730 hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1732 if (hw->mac.type != ixgbe_mac_82598EB) {
1733 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1734 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1735 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1736 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1737 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1738 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1739 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1740 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1742 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1743 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1744 /* 82598 only has a counter in the high register */
1745 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1746 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1747 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1751 * Workaround: mprc hardware is incorrectly counting
1752 * broadcasts, so for now we subtract those.
1754 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1755 hw_stats->bprc += bprc;
1756 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1757 if (hw->mac.type == ixgbe_mac_82598EB)
1758 hw_stats->mprc -= bprc;
1760 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1761 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1762 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1763 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1764 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1765 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1767 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1768 hw_stats->lxontxc += lxon;
1769 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1770 hw_stats->lxofftxc += lxoff;
1771 total = lxon + lxoff;
1773 hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1774 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1775 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1776 hw_stats->gptc -= total;
1777 hw_stats->mptc -= total;
1778 hw_stats->ptc64 -= total;
1779 hw_stats->gotc -= total * ETHER_MIN_LEN;
1781 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1782 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1783 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1784 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1785 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1786 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1787 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1788 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1789 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1790 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1791 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1792 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1793 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1794 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1795 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1796 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1797 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1798 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1799 /* Only read FCOE on 82599 */
1800 if (hw->mac.type != ixgbe_mac_82598EB) {
1801 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1802 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1803 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1804 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1805 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1811 /* Fill out the rte_eth_stats statistics structure */
1812 stats->ipackets = total_qprc;
1813 stats->ibytes = total_qbrc;
1814 stats->opackets = hw_stats->gptc;
1815 stats->obytes = hw_stats->gotc;
1816 stats->imcasts = hw_stats->mprc;
1818 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1819 stats->q_ipackets[i] = hw_stats->qprc[i];
1820 stats->q_opackets[i] = hw_stats->qptc[i];
1821 stats->q_ibytes[i] = hw_stats->qbrc[i];
1822 stats->q_obytes[i] = hw_stats->qbtc[i];
1823 stats->q_errors[i] = hw_stats->qprdc[i];
1827 stats->ibadcrc = hw_stats->crcerrs;
1828 stats->ibadlen = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1829 stats->imissed = total_missed_rx;
1830 stats->ierrors = stats->ibadcrc +
1833 hw_stats->illerrc + hw_stats->errbc;
1838 /* XON/XOFF pause frames */
1839 stats->tx_pause_xon = hw_stats->lxontxc;
1840 stats->rx_pause_xon = hw_stats->lxonrxc;
1841 stats->tx_pause_xoff = hw_stats->lxofftxc;
1842 stats->rx_pause_xoff = hw_stats->lxoffrxc;
1844 /* Flow Director Stats registers */
1845 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1846 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1847 stats->fdirmatch = hw_stats->fdirmatch;
1848 stats->fdirmiss = hw_stats->fdirmiss;
1852 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1854 struct ixgbe_hw_stats *stats =
1855 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1857 /* HW registers are cleared on read */
1858 ixgbe_dev_stats_get(dev, NULL);
1860 /* Reset software totals */
1861 memset(stats, 0, sizeof(*stats));
1865 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1867 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1869 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1871 /* Good Rx packet, include VF loopback */
1872 UPDATE_VF_STAT(IXGBE_VFGPRC,
1873 hw_stats->last_vfgprc, hw_stats->vfgprc);
1875 /* Good Rx octets, include VF loopback */
1876 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1877 hw_stats->last_vfgorc, hw_stats->vfgorc);
1879 /* Good Tx packet, include VF loopback */
1880 UPDATE_VF_STAT(IXGBE_VFGPTC,
1881 hw_stats->last_vfgptc, hw_stats->vfgptc);
1883 /* Good Tx octets, include VF loopback */
1884 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1885 hw_stats->last_vfgotc, hw_stats->vfgotc);
1887 /* Rx Multicst Packet */
1888 UPDATE_VF_STAT(IXGBE_VFMPRC,
1889 hw_stats->last_vfmprc, hw_stats->vfmprc);
1894 memset(stats, 0, sizeof(*stats));
1895 stats->ipackets = hw_stats->vfgprc;
1896 stats->ibytes = hw_stats->vfgorc;
1897 stats->opackets = hw_stats->vfgptc;
1898 stats->obytes = hw_stats->vfgotc;
1899 stats->imcasts = hw_stats->vfmprc;
1903 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
1905 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1906 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1908 /* Sync HW register to the last stats */
1909 ixgbevf_dev_stats_get(dev, NULL);
1911 /* reset HW current stats*/
1912 hw_stats->vfgprc = 0;
1913 hw_stats->vfgorc = 0;
1914 hw_stats->vfgptc = 0;
1915 hw_stats->vfgotc = 0;
1916 hw_stats->vfmprc = 0;
1921 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1923 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1925 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
1926 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
1927 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
1928 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
1929 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
1930 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
1931 dev_info->max_vfs = dev->pci_dev->max_vfs;
1932 if (hw->mac.type == ixgbe_mac_82598EB)
1933 dev_info->max_vmdq_pools = ETH_16_POOLS;
1935 dev_info->max_vmdq_pools = ETH_64_POOLS;
1936 dev_info->rx_offload_capa =
1937 DEV_RX_OFFLOAD_VLAN_STRIP |
1938 DEV_RX_OFFLOAD_IPV4_CKSUM |
1939 DEV_RX_OFFLOAD_UDP_CKSUM |
1940 DEV_RX_OFFLOAD_TCP_CKSUM;
1941 dev_info->tx_offload_capa =
1942 DEV_TX_OFFLOAD_VLAN_INSERT |
1943 DEV_TX_OFFLOAD_IPV4_CKSUM |
1944 DEV_TX_OFFLOAD_UDP_CKSUM |
1945 DEV_TX_OFFLOAD_TCP_CKSUM |
1946 DEV_TX_OFFLOAD_SCTP_CKSUM;
1949 /* return 0 means link status changed, -1 means not changed */
1951 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1954 struct rte_eth_link link, old;
1955 ixgbe_link_speed link_speed;
1959 link.link_status = 0;
1960 link.link_speed = 0;
1961 link.link_duplex = 0;
1962 memset(&old, 0, sizeof(old));
1963 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
1965 /* check if it needs to wait to complete, if lsc interrupt is enabled */
1966 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
1967 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
1969 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
1971 link.link_speed = ETH_LINK_SPEED_100;
1972 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1973 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1974 if (link.link_status == old.link_status)
1980 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1981 if (link.link_status == old.link_status)
1985 link.link_status = 1;
1986 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1988 switch (link_speed) {
1990 case IXGBE_LINK_SPEED_UNKNOWN:
1991 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1992 link.link_speed = ETH_LINK_SPEED_100;
1995 case IXGBE_LINK_SPEED_100_FULL:
1996 link.link_speed = ETH_LINK_SPEED_100;
1999 case IXGBE_LINK_SPEED_1GB_FULL:
2000 link.link_speed = ETH_LINK_SPEED_1000;
2003 case IXGBE_LINK_SPEED_10GB_FULL:
2004 link.link_speed = ETH_LINK_SPEED_10000;
2007 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2009 if (link.link_status == old.link_status)
2016 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2018 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2021 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2022 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2023 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2027 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2029 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2032 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2033 fctrl &= (~IXGBE_FCTRL_UPE);
2034 if (dev->data->all_multicast == 1)
2035 fctrl |= IXGBE_FCTRL_MPE;
2037 fctrl &= (~IXGBE_FCTRL_MPE);
2038 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2042 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2044 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2047 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2048 fctrl |= IXGBE_FCTRL_MPE;
2049 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2053 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2055 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058 if (dev->data->promiscuous == 1)
2059 return; /* must remain in all_multicast mode */
2061 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2062 fctrl &= (~IXGBE_FCTRL_MPE);
2063 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2067 * It clears the interrupt causes and enables the interrupt.
2068 * It will be called once only during nic initialized.
2071 * Pointer to struct rte_eth_dev.
2074 * - On success, zero.
2075 * - On failure, a negative value.
2078 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2080 struct ixgbe_interrupt *intr =
2081 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2083 ixgbe_dev_link_status_print(dev);
2084 intr->mask |= IXGBE_EICR_LSC;
2090 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2093 * Pointer to struct rte_eth_dev.
2096 * - On success, zero.
2097 * - On failure, a negative value.
2100 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2103 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2104 struct ixgbe_interrupt *intr =
2105 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2107 /* clear all cause mask */
2108 ixgbe_disable_intr(hw);
2110 /* read-on-clear nic registers here */
2111 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2112 PMD_DRV_LOG(INFO, "eicr %x", eicr);
2115 if (eicr & IXGBE_EICR_LSC) {
2116 /* set flag for async link update */
2117 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2120 if (eicr & IXGBE_EICR_MAILBOX)
2121 intr->flags |= IXGBE_FLAG_MAILBOX;
2127 * It gets and then prints the link status.
2130 * Pointer to struct rte_eth_dev.
2133 * - On success, zero.
2134 * - On failure, a negative value.
2137 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2139 struct rte_eth_link link;
2141 memset(&link, 0, sizeof(link));
2142 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2143 if (link.link_status) {
2144 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2145 (int)(dev->data->port_id),
2146 (unsigned)link.link_speed,
2147 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2148 "full-duplex" : "half-duplex");
2150 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2151 (int)(dev->data->port_id));
2153 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2154 dev->pci_dev->addr.domain,
2155 dev->pci_dev->addr.bus,
2156 dev->pci_dev->addr.devid,
2157 dev->pci_dev->addr.function);
2161 * It executes link_update after knowing an interrupt occurred.
2164 * Pointer to struct rte_eth_dev.
2167 * - On success, zero.
2168 * - On failure, a negative value.
2171 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2173 struct ixgbe_interrupt *intr =
2174 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2176 struct rte_eth_link link;
2177 int intr_enable_delay = false;
2179 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2181 if (intr->flags & IXGBE_FLAG_MAILBOX) {
2182 ixgbe_pf_mbx_process(dev);
2183 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2186 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2187 /* get the link status before link update, for predicting later */
2188 memset(&link, 0, sizeof(link));
2189 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2191 ixgbe_dev_link_update(dev, 0);
2194 if (!link.link_status)
2195 /* handle it 1 sec later, wait it being stable */
2196 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2197 /* likely to down */
2199 /* handle it 4 sec later, wait it being stable */
2200 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2202 ixgbe_dev_link_status_print(dev);
2204 intr_enable_delay = true;
2207 if (intr_enable_delay) {
2208 if (rte_eal_alarm_set(timeout * 1000,
2209 ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2210 PMD_DRV_LOG(ERR, "Error setting alarm");
2212 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2213 ixgbe_enable_intr(dev);
2214 rte_intr_enable(&(dev->pci_dev->intr_handle));
2222 * Interrupt handler which shall be registered for alarm callback for delayed
2223 * handling specific interrupt to wait for the stable nic state. As the
2224 * NIC interrupt state is not stable for ixgbe after link is just down,
2225 * it needs to wait 4 seconds to get the stable status.
2228 * Pointer to interrupt handle.
2230 * The address of parameter (struct rte_eth_dev *) regsitered before.
2236 ixgbe_dev_interrupt_delayed_handler(void *param)
2238 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2239 struct ixgbe_interrupt *intr =
2240 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2241 struct ixgbe_hw *hw =
2242 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2246 if (eicr & IXGBE_EICR_MAILBOX)
2247 ixgbe_pf_mbx_process(dev);
2249 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2250 ixgbe_dev_link_update(dev, 0);
2251 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2252 ixgbe_dev_link_status_print(dev);
2253 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2256 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2257 ixgbe_enable_intr(dev);
2258 rte_intr_enable(&(dev->pci_dev->intr_handle));
2262 * Interrupt handler triggered by NIC for handling
2263 * specific interrupt.
2266 * Pointer to interrupt handle.
2268 * The address of parameter (struct rte_eth_dev *) regsitered before.
2274 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2277 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2278 ixgbe_dev_interrupt_get_status(dev);
2279 ixgbe_dev_interrupt_action(dev);
2283 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2285 struct ixgbe_hw *hw;
2287 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2288 return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2292 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2294 struct ixgbe_hw *hw;
2296 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297 return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2301 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2303 struct ixgbe_hw *hw;
2309 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2311 fc_conf->pause_time = hw->fc.pause_time;
2312 fc_conf->high_water = hw->fc.high_water[0];
2313 fc_conf->low_water = hw->fc.low_water[0];
2314 fc_conf->send_xon = hw->fc.send_xon;
2315 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2318 * Return rx_pause status according to actual setting of
2321 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2322 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2328 * Return tx_pause status according to actual setting of
2331 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2332 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2337 if (rx_pause && tx_pause)
2338 fc_conf->mode = RTE_FC_FULL;
2340 fc_conf->mode = RTE_FC_RX_PAUSE;
2342 fc_conf->mode = RTE_FC_TX_PAUSE;
2344 fc_conf->mode = RTE_FC_NONE;
2350 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2352 struct ixgbe_hw *hw;
2354 uint32_t rx_buf_size;
2355 uint32_t max_high_water;
2357 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2364 PMD_INIT_FUNC_TRACE();
2366 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2367 if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2369 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2370 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2373 * At least reserve one Ethernet frame for watermark
2374 * high_water/low_water in kilo bytes for ixgbe
2376 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2377 if ((fc_conf->high_water > max_high_water) ||
2378 (fc_conf->high_water < fc_conf->low_water)) {
2379 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2380 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2384 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2385 hw->fc.pause_time = fc_conf->pause_time;
2386 hw->fc.high_water[0] = fc_conf->high_water;
2387 hw->fc.low_water[0] = fc_conf->low_water;
2388 hw->fc.send_xon = fc_conf->send_xon;
2390 err = ixgbe_fc_enable(hw);
2392 /* Not negotiated is not an error case */
2393 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2395 /* check if we want to forward MAC frames - driver doesn't have native
2396 * capability to do that, so we'll write the registers ourselves */
2398 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2400 /* set or clear MFLCN.PMCF bit depending on configuration */
2401 if (fc_conf->mac_ctrl_frame_fwd != 0)
2402 mflcn |= IXGBE_MFLCN_PMCF;
2404 mflcn &= ~IXGBE_MFLCN_PMCF;
2406 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2407 IXGBE_WRITE_FLUSH(hw);
2412 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2417 * ixgbe_pfc_enable_generic - Enable flow control
2418 * @hw: pointer to hardware structure
2419 * @tc_num: traffic class number
2420 * Enable flow control according to the current settings.
2423 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2426 uint32_t mflcn_reg, fccfg_reg;
2428 uint32_t fcrtl, fcrth;
2432 /* Validate the water mark configuration */
2433 if (!hw->fc.pause_time) {
2434 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2438 /* Low water mark of zero causes XOFF floods */
2439 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2440 /* High/Low water can not be 0 */
2441 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2442 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2443 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2447 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2448 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2449 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2453 /* Negotiate the fc mode to use */
2454 ixgbe_fc_autoneg(hw);
2456 /* Disable any previous flow control settings */
2457 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2458 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2460 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2461 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2463 switch (hw->fc.current_mode) {
2466 * If the count of enabled RX Priority Flow control >1,
2467 * and the TX pause can not be disabled
2470 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2471 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2472 if (reg & IXGBE_FCRTH_FCEN)
2476 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2478 case ixgbe_fc_rx_pause:
2480 * Rx Flow control is enabled and Tx Flow control is
2481 * disabled by software override. Since there really
2482 * isn't a way to advertise that we are capable of RX
2483 * Pause ONLY, we will advertise that we support both
2484 * symmetric and asymmetric Rx PAUSE. Later, we will
2485 * disable the adapter's ability to send PAUSE frames.
2487 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2489 * If the count of enabled RX Priority Flow control >1,
2490 * and the TX pause can not be disabled
2493 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2494 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2495 if (reg & IXGBE_FCRTH_FCEN)
2499 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2501 case ixgbe_fc_tx_pause:
2503 * Tx Flow control is enabled, and Rx Flow control is
2504 * disabled by software override.
2506 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2509 /* Flow control (both Rx and Tx) is enabled by SW override. */
2510 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2511 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2514 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2515 ret_val = IXGBE_ERR_CONFIG;
2520 /* Set 802.3x based flow control settings. */
2521 mflcn_reg |= IXGBE_MFLCN_DPF;
2522 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2523 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2525 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2526 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2527 hw->fc.high_water[tc_num]) {
2528 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2529 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2530 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2532 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2534 * In order to prevent Tx hangs when the internal Tx
2535 * switch is enabled we must set the high water mark
2536 * to the maximum FCRTH value. This allows the Tx
2537 * switch to function even under heavy Rx workloads.
2539 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2541 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2543 /* Configure pause time (2 TCs per register) */
2544 reg = hw->fc.pause_time * 0x00010001;
2545 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2546 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2548 /* Configure flow control refresh threshold value */
2549 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2556 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2558 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2561 if(hw->mac.type != ixgbe_mac_82598EB) {
2562 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2568 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2571 uint32_t rx_buf_size;
2572 uint32_t max_high_water;
2574 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2575 struct ixgbe_hw *hw =
2576 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2577 struct ixgbe_dcb_config *dcb_config =
2578 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2580 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2587 PMD_INIT_FUNC_TRACE();
2589 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2590 tc_num = map[pfc_conf->priority];
2591 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2592 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2594 * At least reserve one Ethernet frame for watermark
2595 * high_water/low_water in kilo bytes for ixgbe
2597 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2598 if ((pfc_conf->fc.high_water > max_high_water) ||
2599 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2600 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2601 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2605 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2606 hw->fc.pause_time = pfc_conf->fc.pause_time;
2607 hw->fc.send_xon = pfc_conf->fc.send_xon;
2608 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
2609 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2611 err = ixgbe_dcb_pfc_enable(dev,tc_num);
2613 /* Not negotiated is not an error case */
2614 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2617 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2622 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2623 struct rte_eth_rss_reta *reta_conf)
2627 struct ixgbe_hw *hw =
2628 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2630 PMD_INIT_FUNC_TRACE();
2632 * Update Redirection Table RETA[n],n=0...31,The redirection table has
2633 * 128-entries in 32 registers
2635 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2636 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2637 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2639 mask = (uint8_t)((reta_conf->mask_hi >>
2640 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2644 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2646 for (j = 0; j < 4; j++) {
2647 if (mask & (0x1 << j)) {
2649 reta &= ~(0xFF << 8 * j);
2650 reta |= reta_conf->reta[i + j] << 8*j;
2653 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),reta);
2661 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2662 struct rte_eth_rss_reta *reta_conf)
2666 struct ixgbe_hw *hw =
2667 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2669 PMD_INIT_FUNC_TRACE();
2671 * Read Redirection Table RETA[n],n=0...31,The redirection table has
2672 * 128-entries in 32 registers
2674 for(i = 0; i < ETH_RSS_RETA_NUM_ENTRIES; i += 4) {
2675 if (i < ETH_RSS_RETA_NUM_ENTRIES/2)
2676 mask = (uint8_t)((reta_conf->mask_lo >> i) & 0xF);
2678 mask = (uint8_t)((reta_conf->mask_hi >>
2679 (i - ETH_RSS_RETA_NUM_ENTRIES/2)) & 0xF);
2682 reta = IXGBE_READ_REG(hw,IXGBE_RETA(i >> 2));
2683 for (j = 0; j < 4; j++) {
2684 if (mask & (0x1 << j))
2685 reta_conf->reta[i + j] =
2686 (uint8_t)((reta >> 8 * j) & 0xFF);
2695 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2696 uint32_t index, uint32_t pool)
2698 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2699 uint32_t enable_addr = 1;
2701 ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2705 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2707 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2709 ixgbe_clear_rar(hw, index);
2713 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2717 struct ixgbe_hw *hw;
2718 struct rte_eth_dev_info dev_info;
2719 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2721 ixgbe_dev_info_get(dev, &dev_info);
2723 /* check that mtu is within the allowed range */
2724 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2727 /* refuse mtu that requires the support of scattered packets when this
2728 * feature has not been enabled before. */
2729 if (!dev->data->scattered_rx &&
2730 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2731 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2734 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2737 /* switch to jumbo mode if needed */
2738 if (frame_size > ETHER_MAX_LEN) {
2739 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2740 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2742 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2743 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2745 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2747 /* update max frame size */
2748 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2750 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2751 maxfrs &= 0x0000FFFF;
2752 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2753 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2759 * Virtual Function operations
2762 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2764 PMD_INIT_FUNC_TRACE();
2766 /* Clear interrupt mask to stop from interrupts being generated */
2767 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2769 IXGBE_WRITE_FLUSH(hw);
2773 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2775 struct rte_eth_conf* conf = &dev->data->dev_conf;
2777 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2778 dev->data->port_id);
2781 * VF has no ability to enable/disable HW CRC
2782 * Keep the persistent behavior the same as Host PF
2784 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2785 if (!conf->rxmode.hw_strip_crc) {
2786 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2787 conf->rxmode.hw_strip_crc = 1;
2790 if (conf->rxmode.hw_strip_crc) {
2791 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2792 conf->rxmode.hw_strip_crc = 0;
2800 ixgbevf_dev_start(struct rte_eth_dev *dev)
2802 struct ixgbe_hw *hw =
2803 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2806 PMD_INIT_FUNC_TRACE();
2808 hw->mac.ops.reset_hw(hw);
2810 /* negotiate mailbox API version to use with the PF. */
2811 ixgbevf_negotiate_api(hw);
2813 ixgbevf_dev_tx_init(dev);
2815 /* This can fail when allocating mbufs for descriptor rings */
2816 err = ixgbevf_dev_rx_init(dev);
2818 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
2819 ixgbe_dev_clear_queues(dev);
2824 ixgbevf_set_vfta_all(dev,1);
2827 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2828 ETH_VLAN_EXTEND_MASK;
2829 ixgbevf_vlan_offload_set(dev, mask);
2831 ixgbevf_dev_rxtx_start(dev);
2837 ixgbevf_dev_stop(struct rte_eth_dev *dev)
2839 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841 PMD_INIT_FUNC_TRACE();
2843 hw->adapter_stopped = TRUE;
2844 ixgbe_stop_adapter(hw);
2847 * Clear what we set, but we still keep shadow_vfta to
2848 * restore after device starts
2850 ixgbevf_set_vfta_all(dev,0);
2852 ixgbe_dev_clear_queues(dev);
2856 ixgbevf_dev_close(struct rte_eth_dev *dev)
2858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2860 PMD_INIT_FUNC_TRACE();
2864 ixgbevf_dev_stop(dev);
2866 /* reprogram the RAR[0] in case user changed it. */
2867 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2870 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
2872 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873 struct ixgbe_vfta * shadow_vfta =
2874 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2875 int i = 0, j = 0, vfta = 0, mask = 1;
2877 for (i = 0; i < IXGBE_VFTA_SIZE; i++){
2878 vfta = shadow_vfta->vfta[i];
2881 for (j = 0; j < 32; j++){
2883 ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
2892 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2894 struct ixgbe_hw *hw =
2895 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896 struct ixgbe_vfta * shadow_vfta =
2897 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
2898 uint32_t vid_idx = 0;
2899 uint32_t vid_bit = 0;
2902 PMD_INIT_FUNC_TRACE();
2904 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
2905 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
2907 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
2910 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
2911 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
2913 /* Save what we set and retore it after device reset */
2915 shadow_vfta->vfta[vid_idx] |= vid_bit;
2917 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
2923 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
2925 struct ixgbe_hw *hw =
2926 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929 PMD_INIT_FUNC_TRACE();
2931 if(queue >= hw->mac.max_rx_queues)
2934 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2936 ctrl |= IXGBE_RXDCTL_VME;
2938 ctrl &= ~IXGBE_RXDCTL_VME;
2939 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2941 ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
2945 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2947 struct ixgbe_hw *hw =
2948 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952 /* VF function only support hw strip feature, others are not support */
2953 if(mask & ETH_VLAN_STRIP_MASK){
2954 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
2956 for(i=0; i < hw->mac.max_rx_queues; i++)
2957 ixgbevf_vlan_strip_queue_set(dev,i,on);
2962 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
2966 /* we only need to do this if VMDq is enabled */
2967 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2968 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
2969 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
2977 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
2979 uint32_t vector = 0;
2980 switch (hw->mac.mc_filter_type) {
2981 case 0: /* use bits [47:36] of the address */
2982 vector = ((uc_addr->addr_bytes[4] >> 4) |
2983 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
2985 case 1: /* use bits [46:35] of the address */
2986 vector = ((uc_addr->addr_bytes[4] >> 3) |
2987 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
2989 case 2: /* use bits [45:34] of the address */
2990 vector = ((uc_addr->addr_bytes[4] >> 2) |
2991 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
2993 case 3: /* use bits [43:32] of the address */
2994 vector = ((uc_addr->addr_bytes[4]) |
2995 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
2997 default: /* Invalid mc_filter_type */
3001 /* vector can only be 12-bits or boundary will be exceeded */
3007 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3015 const uint32_t ixgbe_uta_idx_mask = 0x7F;
3016 const uint32_t ixgbe_uta_bit_shift = 5;
3017 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3018 const uint32_t bit1 = 0x1;
3020 struct ixgbe_hw *hw =
3021 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022 struct ixgbe_uta_info *uta_info =
3023 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3025 /* The UTA table only exists on 82599 hardware and newer */
3026 if (hw->mac.type < ixgbe_mac_82599EB)
3029 vector = ixgbe_uta_vector(hw,mac_addr);
3030 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3031 uta_shift = vector & ixgbe_uta_bit_mask;
3033 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3037 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3039 uta_info->uta_in_use++;
3040 reg_val |= (bit1 << uta_shift);
3041 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3043 uta_info->uta_in_use--;
3044 reg_val &= ~(bit1 << uta_shift);
3045 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3048 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3050 if (uta_info->uta_in_use > 0)
3051 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3052 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3054 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3060 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3063 struct ixgbe_hw *hw =
3064 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065 struct ixgbe_uta_info *uta_info =
3066 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3068 /* The UTA table only exists on 82599 hardware and newer */
3069 if (hw->mac.type < ixgbe_mac_82599EB)
3073 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3074 uta_info->uta_shadow[i] = ~0;
3075 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3078 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3079 uta_info->uta_shadow[i] = 0;
3080 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3087 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3088 uint16_t rx_mask, uint8_t on)
3092 struct ixgbe_hw *hw =
3093 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094 uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3096 if (hw->mac.type == ixgbe_mac_82598EB) {
3097 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3098 " on 82599 hardware and newer");
3101 if (ixgbe_vmdq_mode_check(hw) < 0)
3104 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG )
3105 val |= IXGBE_VMOLR_AUPE;
3106 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC )
3107 val |= IXGBE_VMOLR_ROMPE;
3108 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3109 val |= IXGBE_VMOLR_ROPE;
3110 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3111 val |= IXGBE_VMOLR_BAM;
3112 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3113 val |= IXGBE_VMOLR_MPE;
3120 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3126 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3130 const uint8_t bit1 = 0x1;
3132 struct ixgbe_hw *hw =
3133 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3135 if (ixgbe_vmdq_mode_check(hw) < 0)
3138 addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3139 reg = IXGBE_READ_REG(hw, addr);
3147 IXGBE_WRITE_REG(hw, addr,reg);
3153 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3157 const uint8_t bit1 = 0x1;
3159 struct ixgbe_hw *hw =
3160 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3162 if (ixgbe_vmdq_mode_check(hw) < 0)
3165 addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3166 reg = IXGBE_READ_REG(hw, addr);
3174 IXGBE_WRITE_REG(hw, addr,reg);
3180 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3181 uint64_t pool_mask, uint8_t vlan_on)
3185 struct ixgbe_hw *hw =
3186 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188 if (ixgbe_vmdq_mode_check(hw) < 0)
3190 for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3191 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3192 ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3201 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3202 struct rte_eth_vmdq_mirror_conf *mirror_conf,
3203 uint8_t rule_id, uint8_t on)
3205 uint32_t mr_ctl,vlvf;
3206 uint32_t mp_lsb = 0;
3207 uint32_t mv_msb = 0;
3208 uint32_t mv_lsb = 0;
3209 uint32_t mp_msb = 0;
3212 uint64_t vlan_mask = 0;
3214 const uint8_t pool_mask_offset = 32;
3215 const uint8_t vlan_mask_offset = 32;
3216 const uint8_t dst_pool_offset = 8;
3217 const uint8_t rule_mr_offset = 4;
3218 const uint8_t mirror_rule_mask= 0x0F;
3220 struct ixgbe_mirror_info *mr_info =
3221 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3222 struct ixgbe_hw *hw =
3223 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3225 if (ixgbe_vmdq_mode_check(hw) < 0)
3228 /* Check if vlan mask is valid */
3229 if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3230 if (mirror_conf->vlan.vlan_mask == 0)
3234 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3235 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3236 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3237 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3238 /* search vlan id related pool vlan filter index */
3239 reg_index = ixgbe_find_vlvf_slot(hw,
3240 mirror_conf->vlan.vlan_id[i]);
3243 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3244 if ((vlvf & IXGBE_VLVF_VIEN) &&
3245 ((vlvf & IXGBE_VLVF_VLANID_MASK)
3246 == mirror_conf->vlan.vlan_id[i]))
3247 vlan_mask |= (1ULL << reg_index);
3254 mv_lsb = vlan_mask & 0xFFFFFFFF;
3255 mv_msb = vlan_mask >> vlan_mask_offset;
3257 mr_info->mr_conf[rule_id].vlan.vlan_mask =
3258 mirror_conf->vlan.vlan_mask;
3259 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3260 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3261 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3262 mirror_conf->vlan.vlan_id[i];
3267 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3268 for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3269 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3274 * if enable pool mirror, write related pool mask register,if disable
3275 * pool mirror, clear PFMRVM register
3277 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3279 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3280 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3281 mr_info->mr_conf[rule_id].pool_mask =
3282 mirror_conf->pool_mask;
3287 mr_info->mr_conf[rule_id].pool_mask = 0;
3291 /* read mirror control register and recalculate it */
3292 mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3295 mr_ctl |= mirror_conf->rule_type_mask;
3296 mr_ctl &= mirror_rule_mask;
3297 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3299 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3301 mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3302 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3304 /* write mirrror control register */
3305 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3307 /* write pool mirrror control register */
3308 if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3309 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3310 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3313 /* write VLAN mirrror control register */
3314 if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3315 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3316 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3324 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3327 uint32_t lsb_val = 0;
3328 uint32_t msb_val = 0;
3329 const uint8_t rule_mr_offset = 4;
3331 struct ixgbe_hw *hw =
3332 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3333 struct ixgbe_mirror_info *mr_info =
3334 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3336 if (ixgbe_vmdq_mode_check(hw) < 0)
3339 memset(&mr_info->mr_conf[rule_id], 0,
3340 sizeof(struct rte_eth_vmdq_mirror_conf));
3342 /* clear PFVMCTL register */
3343 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3345 /* clear pool mask register */
3346 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3347 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3349 /* clear vlan mask register */
3350 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3351 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3356 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3357 uint16_t queue_idx, uint16_t tx_rate)
3359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360 uint32_t rf_dec, rf_int;
3362 uint16_t link_speed = dev->data->dev_link.link_speed;
3364 if (queue_idx >= hw->mac.max_tx_queues)
3368 /* Calculate the rate factor values to set */
3369 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3370 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3371 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3373 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3374 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3375 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3376 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3382 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3383 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3386 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3387 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3388 IXGBE_MAX_JUMBO_FRAME_SIZE))
3389 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3390 IXGBE_MMW_SIZE_JUMBO_FRAME);
3392 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3393 IXGBE_MMW_SIZE_DEFAULT);
3395 /* Set RTTBCNRC of queue X */
3396 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3397 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3398 IXGBE_WRITE_FLUSH(hw);
3403 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3404 uint16_t tx_rate, uint64_t q_msk)
3406 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407 struct ixgbe_vf_info *vfinfo =
3408 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3409 uint8_t nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3410 uint32_t queue_stride =
3411 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3412 uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3413 uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3414 uint16_t total_rate = 0;
3416 if (queue_end >= hw->mac.max_tx_queues)
3419 if (vfinfo != NULL) {
3420 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3423 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3425 total_rate += vfinfo[vf_idx].tx_rate[idx];
3430 /* Store tx_rate for this vf. */
3431 for (idx = 0; idx < nb_q_per_pool; idx++) {
3432 if (((uint64_t)0x1 << idx) & q_msk) {
3433 if (vfinfo[vf].tx_rate[idx] != tx_rate)
3434 vfinfo[vf].tx_rate[idx] = tx_rate;
3435 total_rate += tx_rate;
3439 if (total_rate > dev->data->dev_link.link_speed) {
3441 * Reset stored TX rate of the VF if it causes exceed
3444 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3448 /* Set RTTBCNRC of each queue/pool for vf X */
3449 for (; queue_idx <= queue_end; queue_idx++) {
3451 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3459 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3460 __attribute__((unused)) uint32_t index,
3461 __attribute__((unused)) uint32_t pool)
3463 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467 * On a 82599 VF, adding again the same MAC addr is not an idempotent
3468 * operation. Trap this case to avoid exhausting the [very limited]
3469 * set of PF resources used to store VF MAC addresses.
3471 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3473 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3476 PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3480 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3482 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3484 struct ether_addr *mac_addr;
3489 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3490 * not support the deletion of a given MAC address.
3491 * Instead, it imposes to delete all MAC addresses, then to add again
3492 * all MAC addresses with the exception of the one to be deleted.
3494 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3497 * Add again all MAC addresses, with the exception of the deleted one
3498 * and of the permanent MAC address.
3500 for (i = 0, mac_addr = dev->data->mac_addrs;
3501 i < hw->mac.num_rar_entries; i++, mac_addr++) {
3502 /* Skip the deleted MAC address */
3505 /* Skip NULL MAC addresses */
3506 if (is_zero_ether_addr(mac_addr))
3508 /* Skip the permanent MAC address */
3509 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3511 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3514 "Adding again MAC address "
3515 "%02x:%02x:%02x:%02x:%02x:%02x failed "
3517 mac_addr->addr_bytes[0],
3518 mac_addr->addr_bytes[1],
3519 mac_addr->addr_bytes[2],
3520 mac_addr->addr_bytes[3],
3521 mac_addr->addr_bytes[4],
3522 mac_addr->addr_bytes[5],
3531 * dev: Pointer to struct rte_eth_dev.
3532 * filter: ponter to the filter that will be added.
3533 * rx_queue: the queue id the filter assigned to.
3536 * - On success, zero.
3537 * - On failure, a negative value.
3540 ixgbe_add_syn_filter(struct rte_eth_dev *dev,
3541 struct rte_syn_filter *filter, uint16_t rx_queue)
3543 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3546 if (hw->mac.type != ixgbe_mac_82599EB)
3549 if (rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3552 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3554 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3557 synqf = (uint32_t)(((rx_queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3558 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3560 if (filter->hig_pri)
3561 synqf |= IXGBE_SYN_FILTER_SYNQFP;
3563 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3565 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3573 * dev: Pointer to struct rte_eth_dev.
3576 * - On success, zero.
3577 * - On failure, a negative value.
3580 ixgbe_remove_syn_filter(struct rte_eth_dev *dev)
3582 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585 if (hw->mac.type != ixgbe_mac_82599EB)
3588 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3590 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3592 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3597 * get the syn filter's info
3600 * dev: Pointer to struct rte_eth_dev.
3601 * filter: ponter to the filter that returns.
3602 * *rx_queue: pointer to the queue id the filter assigned to.
3605 * - On success, zero.
3606 * - On failure, a negative value.
3609 ixgbe_get_syn_filter(struct rte_eth_dev *dev,
3610 struct rte_syn_filter *filter, uint16_t *rx_queue)
3613 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3616 if (hw->mac.type != ixgbe_mac_82599EB)
3619 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3620 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3621 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3622 *rx_queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3629 * add an ethertype filter
3632 * dev: Pointer to struct rte_eth_dev.
3633 * index: the index the filter allocates.
3634 * filter: ponter to the filter that will be added.
3635 * rx_queue: the queue id the filter assigned to.
3638 * - On success, zero.
3639 * - On failure, a negative value.
3642 ixgbe_add_ethertype_filter(struct rte_eth_dev *dev,
3643 uint16_t index, struct rte_ethertype_filter *filter,
3646 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3647 uint32_t etqf, etqs = 0;
3649 if (hw->mac.type != ixgbe_mac_82599EB)
3652 if (index >= IXGBE_MAX_ETQF_FILTERS ||
3653 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM)
3656 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3657 if (etqf & IXGBE_ETQF_FILTER_EN)
3658 return -EINVAL; /* filter index is in use. */
3661 etqf |= IXGBE_ETQF_FILTER_EN;
3662 etqf |= (uint32_t)filter->ethertype;
3664 if (filter->priority_en) {
3665 if (filter->priority > IXGBE_ETQF_MAX_PRI)
3667 etqf |= (uint32_t)((filter->priority << IXGBE_ETQF_SHIFT) & IXGBE_ETQF_UP);
3668 etqf |= IXGBE_ETQF_UP_EN;
3670 etqs |= (uint32_t)((rx_queue << IXGBE_ETQS_RX_QUEUE_SHIFT) & IXGBE_ETQS_RX_QUEUE);
3671 etqs |= IXGBE_ETQS_QUEUE_EN;
3673 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), etqf);
3674 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), etqs);
3679 * remove an ethertype filter
3682 * dev: Pointer to struct rte_eth_dev.
3683 * index: the index the filter allocates.
3686 * - On success, zero.
3687 * - On failure, a negative value.
3690 ixgbe_remove_ethertype_filter(struct rte_eth_dev *dev,
3693 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3695 if (hw->mac.type != ixgbe_mac_82599EB)
3698 if (index >= IXGBE_MAX_ETQF_FILTERS)
3701 IXGBE_WRITE_REG(hw, IXGBE_ETQF(index), 0);
3702 IXGBE_WRITE_REG(hw, IXGBE_ETQS(index), 0);
3708 * get an ethertype filter
3711 * dev: Pointer to struct rte_eth_dev.
3712 * index: the index the filter allocates.
3713 * filter: ponter to the filter that will be gotten.
3714 * *rx_queue: the ponited of the queue id the filter assigned to.
3717 * - On success, zero.
3718 * - On failure, a negative value.
3721 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
3722 uint16_t index, struct rte_ethertype_filter *filter,
3725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3726 uint32_t etqf, etqs;
3728 if (hw->mac.type != ixgbe_mac_82599EB)
3731 if (index >= IXGBE_MAX_ETQF_FILTERS)
3734 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(index));
3735 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(index));
3736 if (etqf & IXGBE_ETQF_FILTER_EN) {
3737 filter->ethertype = etqf & IXGBE_ETQF_ETHERTYPE;
3738 filter->priority_en = (etqf & IXGBE_ETQF_UP_EN) ? 1 : 0;
3739 if (filter->priority_en)
3740 filter->priority = (etqf & IXGBE_ETQF_UP) >> 16;
3741 *rx_queue = (etqs & IXGBE_ETQS_RX_QUEUE) >> IXGBE_ETQS_RX_QUEUE_SHIFT;
3747 static inline enum ixgbe_5tuple_protocol
3748 convert_protocol_type(uint8_t protocol_value)
3750 if (protocol_value == IPPROTO_TCP)
3751 return IXGBE_FILTER_PROTOCOL_TCP;
3752 else if (protocol_value == IPPROTO_UDP)
3753 return IXGBE_FILTER_PROTOCOL_UDP;
3754 else if (protocol_value == IPPROTO_SCTP)
3755 return IXGBE_FILTER_PROTOCOL_SCTP;
3757 return IXGBE_FILTER_PROTOCOL_NONE;
3760 static inline uint8_t
3761 revert_protocol_type(enum ixgbe_5tuple_protocol protocol)
3763 if (protocol == IXGBE_FILTER_PROTOCOL_TCP)
3765 else if (protocol == IXGBE_FILTER_PROTOCOL_UDP)
3767 else if (protocol == IXGBE_FILTER_PROTOCOL_SCTP)
3768 return IPPROTO_SCTP;
3774 * add a 5tuple filter
3777 * dev: Pointer to struct rte_eth_dev.
3778 * index: the index the filter allocates.
3779 * filter: ponter to the filter that will be added.
3780 * rx_queue: the queue id the filter assigned to.
3783 * - On success, zero.
3784 * - On failure, a negative value.
3787 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3788 struct rte_5tuple_filter *filter, uint16_t rx_queue)
3790 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791 uint32_t ftqf, sdpqf = 0;
3792 uint32_t l34timir = 0;
3793 uint8_t mask = 0xff;
3795 if (hw->mac.type != ixgbe_mac_82599EB)
3798 if (index >= IXGBE_MAX_FTQF_FILTERS ||
3799 rx_queue >= IXGBE_MAX_RX_QUEUE_NUM ||
3800 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
3801 filter->priority < IXGBE_5TUPLE_MIN_PRI)
3802 return -EINVAL; /* filter index is out of range. */
3804 if (filter->tcp_flags) {
3805 PMD_INIT_LOG(INFO, "82599EB not tcp flags in 5tuple");
3809 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3810 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE)
3811 return -EINVAL; /* filter index is in use. */
3814 sdpqf = (uint32_t)(filter->dst_port << IXGBE_SDPQF_DSTPORT_SHIFT);
3815 sdpqf = sdpqf | (filter->src_port & IXGBE_SDPQF_SRCPORT);
3817 ftqf |= (uint32_t)(convert_protocol_type(filter->protocol) &
3818 IXGBE_FTQF_PROTOCOL_MASK);
3819 ftqf |= (uint32_t)((filter->priority & IXGBE_FTQF_PRIORITY_MASK) <<
3820 IXGBE_FTQF_PRIORITY_SHIFT);
3821 if (filter->src_ip_mask == 0) /* 0 means compare. */
3822 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3823 if (filter->dst_ip_mask == 0)
3824 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3825 if (filter->src_port_mask == 0)
3826 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3827 if (filter->dst_port_mask == 0)
3828 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3829 if (filter->protocol_mask == 0)
3830 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3831 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3832 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3833 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3835 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), filter->dst_ip);
3836 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), filter->src_ip);
3837 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), sdpqf);
3838 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), ftqf);
3840 l34timir |= IXGBE_L34T_IMIR_RESERVE;
3841 l34timir |= (uint32_t)(rx_queue << IXGBE_L34T_IMIR_QUEUE_SHIFT);
3842 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), l34timir);
3847 * remove a 5tuple filter
3850 * dev: Pointer to struct rte_eth_dev.
3851 * index: the index the filter allocates.
3854 * - On success, zero.
3855 * - On failure, a negative value.
3858 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863 if (hw->mac.type != ixgbe_mac_82599EB)
3866 if (index >= IXGBE_MAX_FTQF_FILTERS)
3867 return -EINVAL; /* filter index is out of range. */
3869 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3870 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3871 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3872 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3873 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3878 * get a 5tuple filter
3881 * dev: Pointer to struct rte_eth_dev.
3882 * index: the index the filter allocates
3883 * filter: ponter to the filter that returns.
3884 * *rx_queue: pointer of the queue id the filter assigned to.
3887 * - On success, zero.
3888 * - On failure, a negative value.
3891 ixgbe_get_5tuple_filter(struct rte_eth_dev *dev, uint16_t index,
3892 struct rte_5tuple_filter *filter, uint16_t *rx_queue)
3894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3895 uint32_t sdpqf, ftqf, l34timir;
3897 enum ixgbe_5tuple_protocol proto;
3899 if (hw->mac.type != ixgbe_mac_82599EB)
3902 if (index >= IXGBE_MAX_FTQF_FILTERS)
3903 return -EINVAL; /* filter index is out of range. */
3905 ftqf = IXGBE_READ_REG(hw, IXGBE_FTQF(index));
3906 if (ftqf & IXGBE_FTQF_QUEUE_ENABLE) {
3907 proto = (enum ixgbe_5tuple_protocol)(ftqf & IXGBE_FTQF_PROTOCOL_MASK);
3908 filter->protocol = revert_protocol_type(proto);
3909 filter->priority = (ftqf >> IXGBE_FTQF_PRIORITY_SHIFT) &
3910 IXGBE_FTQF_PRIORITY_MASK;
3911 mask = (uint8_t)((ftqf >> IXGBE_FTQF_5TUPLE_MASK_SHIFT) &
3912 IXGBE_FTQF_5TUPLE_MASK_MASK);
3913 filter->src_ip_mask =
3914 (mask & IXGBE_FTQF_SOURCE_ADDR_MASK) ? 1 : 0;
3915 filter->dst_ip_mask =
3916 (mask & IXGBE_FTQF_DEST_ADDR_MASK) ? 1 : 0;
3917 filter->src_port_mask =
3918 (mask & IXGBE_FTQF_SOURCE_PORT_MASK) ? 1 : 0;
3919 filter->dst_port_mask =
3920 (mask & IXGBE_FTQF_DEST_PORT_MASK) ? 1 : 0;
3921 filter->protocol_mask =
3922 (mask & IXGBE_FTQF_PROTOCOL_COMP_MASK) ? 1 : 0;
3924 sdpqf = IXGBE_READ_REG(hw, IXGBE_SDPQF(index));
3925 filter->dst_port = (sdpqf & IXGBE_SDPQF_DSTPORT) >>
3926 IXGBE_SDPQF_DSTPORT_SHIFT;
3927 filter->src_port = sdpqf & IXGBE_SDPQF_SRCPORT;
3928 filter->dst_ip = IXGBE_READ_REG(hw, IXGBE_DAQF(index));
3929 filter->src_ip = IXGBE_READ_REG(hw, IXGBE_SAQF(index));
3931 l34timir = IXGBE_READ_REG(hw, IXGBE_L34T_IMIR(index));
3932 *rx_queue = (l34timir & IXGBE_L34T_IMIR_QUEUE) >>
3933 IXGBE_L34T_IMIR_QUEUE_SHIFT;
3940 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3942 struct ixgbe_hw *hw;
3943 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3945 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3950 /* refuse mtu that requires the support of scattered packets when this
3951 * feature has not been enabled before. */
3952 if (!dev->data->scattered_rx &&
3953 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3954 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3958 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3959 * request of the version 2.0 of the mailbox API.
3960 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3961 * of the mailbox API.
3962 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3963 * prior to 3.11.33 which contains the following change:
3964 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3966 ixgbevf_rlpml_set_vf(hw, max_frame);
3968 /* update max frame size */
3969 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3973 static struct rte_driver rte_ixgbe_driver = {
3975 .init = rte_ixgbe_pmd_init,
3978 static struct rte_driver rte_ixgbevf_driver = {
3980 .init = rte_ixgbevf_pmd_init,
3983 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
3984 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);