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39 #include <sys/queue.h>
41 #include <rte_interrupts.h>
43 #include <rte_debug.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
48 #include "ixgbe_logs.h"
49 #include "ixgbe/ixgbe_api.h"
50 #include "ixgbe/ixgbe_common.h"
51 #include "ixgbe_ethdev.h"
53 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
54 #define FDIRCTRL_PBALLOC_MASK 0x03
56 /* For calculating memory required for FDIR filters */
57 #define PBALLOC_SIZE_SHIFT 15
59 /* Number of bits used to mask bucket hash for different pballoc sizes */
60 #define PERFECT_BUCKET_64KB_HASH_MASK 0x07FF /* 11 bits */
61 #define PERFECT_BUCKET_128KB_HASH_MASK 0x0FFF /* 12 bits */
62 #define PERFECT_BUCKET_256KB_HASH_MASK 0x1FFF /* 13 bits */
63 #define SIG_BUCKET_64KB_HASH_MASK 0x1FFF /* 13 bits */
64 #define SIG_BUCKET_128KB_HASH_MASK 0x3FFF /* 14 bits */
65 #define SIG_BUCKET_256KB_HASH_MASK 0x7FFF /* 15 bits */
68 * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
69 * It adds extra configuration of fdirctrl that is common for all filter types.
71 * Initialize Flow Director control registers
72 * @hw: pointer to hardware structure
73 * @fdirctrl: value to write to flow director control register
75 static void fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
79 PMD_INIT_FUNC_TRACE();
81 /* Prime the keys for hashing */
82 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
83 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
86 * Continue setup of fdirctrl register bits:
87 * Set the maximum length per hash bucket to 0xA filters
88 * Send interrupt when 64 filters are left
90 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
91 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
94 * Poll init-done after we write the register. Estimated times:
95 * 10G: PBALLOC = 11b, timing is 60us
96 * 1G: PBALLOC = 11b, timing is 600us
97 * 100M: PBALLOC = 11b, timing is 6ms
99 * Multiple these timings by 4 if under full Rx load
101 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
102 * 1 msec per poll time. If we're at line rate and drop to 100M, then
103 * this might not finish in our poll time, but we can live with that
106 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
107 IXGBE_WRITE_FLUSH(hw);
108 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
109 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
110 IXGBE_FDIRCTRL_INIT_DONE)
115 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
116 PMD_INIT_LOG(WARNING, "Flow Director poll time exceeded!\n");
120 * Set appropriate bits in fdirctrl for: variable reporting levels, moving
121 * flexbytes matching field, and drop queue (only for perfect matching mode).
124 configure_fdir_flags(struct rte_fdir_conf *conf, uint32_t *fdirctrl)
128 switch (conf->pballoc) {
129 case RTE_FDIR_PBALLOC_64K:
130 /* 8k - 1 signature filters */
131 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
133 case RTE_FDIR_PBALLOC_128K:
134 /* 16k - 1 signature filters */
135 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
137 case RTE_FDIR_PBALLOC_256K:
138 /* 32k - 1 signature filters */
139 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
143 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
147 /* status flags: write hash & swindex in the rx descriptor */
148 switch (conf->status) {
149 case RTE_FDIR_NO_REPORT_STATUS:
150 /* do nothing, default mode */
152 case RTE_FDIR_REPORT_STATUS:
153 /* report status when the packet matches a fdir rule */
154 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
156 case RTE_FDIR_REPORT_STATUS_ALWAYS:
157 /* always report status */
158 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
162 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
166 *fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
168 if (conf->mode == RTE_FDIR_MODE_PERFECT) {
169 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
170 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
177 ixgbe_fdir_configure(struct rte_eth_dev *dev)
179 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
181 uint32_t fdirctrl, pbsize;
184 PMD_INIT_FUNC_TRACE();
186 if (hw->mac.type != ixgbe_mac_82599EB)
189 err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
194 * Before enabling Flow Director, the Rx Packet Buffer size
195 * must be reduced. The new value is the current size minus
196 * flow director memory usage size.
198 pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
199 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
200 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
203 * The defaults in the HW for RX PB 1-7 are not zero and so should be
204 * intialized to zero for non DCB mode otherwise actual total RX PB
205 * would be bigger than programmed and filter space would run into
208 for (i = 1; i < 8; i++)
209 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
211 fdir_enable_82599(hw, fdirctrl);
216 * The below function is taken from the FreeBSD IXGBE drivers release
217 * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
218 * before returning, as the signature hash can use 16bits.
220 * The newer driver has optimised functions for calculating bucket and
221 * signature hashes. However they don't support IPv6 type packets for signature
222 * filters so are not used here.
224 * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
227 * Compute the hashes for SW ATR
228 * @stream: input bitstream to compute the hash on
229 * @key: 32-bit hash key
232 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
236 * The algorithm is as follows:
237 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
238 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
239 * and A[n] x B[n] is bitwise AND between same length strings
241 * K[n] is 16 bits, defined as:
242 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
243 * for n modulo 32 < 15, K[n] =
244 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
246 * S[n] is 16 bits, defined as:
247 * for n >= 15, S[n] = S[n:n - 15]
248 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
250 * To simplify for programming, the algorithm is implemented
251 * in software this way:
253 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
255 * for (i = 0; i < 352; i+=32)
256 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
258 * lo_hash_dword[15:0] ^= Stream[15:0];
259 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
260 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
262 * hi_hash_dword[31:0] ^= Stream[351:320];
265 * hash[15:0] ^= Stream[15:0];
267 * for (i = 0; i < 16; i++) {
269 * hash[15:0] ^= lo_hash_dword[(i+15):i];
271 * hash[15:0] ^= hi_hash_dword[(i+15):i];
275 __be32 common_hash_dword = 0;
276 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
280 /* record the flow_vm_vlan bits as they are a key part to the hash */
281 flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
283 /* generate common hash dword */
284 for (i = 10; i; i -= 2)
285 common_hash_dword ^= atr_input->dword_stream[i] ^
286 atr_input->dword_stream[i - 1];
288 hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
290 /* low dword is word swapped version of common */
291 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
293 /* apply flow ID/VM pool/VLAN ID bits to hash words */
294 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
296 /* Process bits 0 and 16 */
297 if (key & 0x0001) hash_result ^= lo_hash_dword;
298 if (key & 0x00010000) hash_result ^= hi_hash_dword;
301 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
302 * delay this because bit 0 of the stream should not be processed
303 * so we do not add the vlan until after bit 0 was processed
305 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
308 /* process the remaining 30 bits in the key 2 bits at a time */
309 for (i = 15; i; i-- ) {
310 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
311 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
318 * Calculate the hash value needed for signature-match filters. In the FreeBSD
319 * driver, this is done by the optimised function
320 * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
321 * doesn't support calculating a hash for an IPv6 filter.
324 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
325 enum rte_fdir_pballoc_type pballoc)
327 uint32_t bucket_hash, sig_hash;
329 if (pballoc == RTE_FDIR_PBALLOC_256K)
330 bucket_hash = ixgbe_atr_compute_hash_82599(input,
331 IXGBE_ATR_BUCKET_HASH_KEY) &
332 SIG_BUCKET_256KB_HASH_MASK;
333 else if (pballoc == RTE_FDIR_PBALLOC_128K)
334 bucket_hash = ixgbe_atr_compute_hash_82599(input,
335 IXGBE_ATR_BUCKET_HASH_KEY) &
336 SIG_BUCKET_128KB_HASH_MASK;
338 bucket_hash = ixgbe_atr_compute_hash_82599(input,
339 IXGBE_ATR_BUCKET_HASH_KEY) &
340 SIG_BUCKET_64KB_HASH_MASK;
342 sig_hash = ixgbe_atr_compute_hash_82599(input,
343 IXGBE_ATR_SIGNATURE_HASH_KEY);
345 return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
349 * This function is based on ixgbe_atr_add_signature_filter_82599() in
350 * ixgbe/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
351 * setting extra fields in the FDIRCMD register, and removes the code that was
352 * verifying the flow_type field. According to the documentation, a flow type of
353 * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
356 * Adds a signature hash filter
357 * @hw: pointer to hardware structure
358 * @input: unique input dword
359 * @queue: queue index to direct traffic to
360 * @fdircmd: any extra flags to set in fdircmd register
361 * @fdirhash: pre-calculated hash value for the filter
364 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
365 union ixgbe_atr_input *input, u8 queue, u32 fdircmd,
370 PMD_INIT_FUNC_TRACE();
372 /* configure FDIRCMD register */
373 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
374 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
375 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
376 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
379 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
380 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
382 fdirhashcmd = (u64)fdircmd << 32;
383 fdirhashcmd |= fdirhash;
384 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
386 PMD_INIT_LOG(DEBUG, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
390 * Convert DPDK rte_fdir_filter struct to ixgbe_atr_input union that is used
391 * by the IXGBE driver code.
394 fdir_filter_to_atr_input(struct rte_fdir_filter *fdir_filter,
395 union ixgbe_atr_input *input)
397 if ((fdir_filter->l4type == RTE_FDIR_L4TYPE_SCTP ||
398 fdir_filter->l4type == RTE_FDIR_L4TYPE_NONE) &&
399 (fdir_filter->port_src || fdir_filter->port_dst)) {
400 PMD_INIT_LOG(ERR, "Invalid fdir_filter");
404 memset(input, 0, sizeof(*input));
406 input->formatted.vlan_id = fdir_filter->vlan_id;
407 input->formatted.src_port = fdir_filter->port_src;
408 input->formatted.dst_port = fdir_filter->port_dst;
409 input->formatted.flex_bytes = fdir_filter->flex_bytes;
411 switch (fdir_filter->l4type) {
412 case RTE_FDIR_L4TYPE_TCP:
413 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
415 case RTE_FDIR_L4TYPE_UDP:
416 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
418 case RTE_FDIR_L4TYPE_SCTP:
419 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
421 case RTE_FDIR_L4TYPE_NONE:
422 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
425 PMD_INIT_LOG(ERR, " Error on l4type input");
429 if (fdir_filter->iptype == RTE_FDIR_IPTYPE_IPV6) {
430 input->formatted.flow_type |= IXGBE_ATR_L4TYPE_IPV6_MASK;
432 input->formatted.src_ip[0] = fdir_filter->ip_src.ipv6_addr[0];
433 input->formatted.src_ip[1] = fdir_filter->ip_src.ipv6_addr[1];
434 input->formatted.src_ip[2] = fdir_filter->ip_src.ipv6_addr[2];
435 input->formatted.src_ip[3] = fdir_filter->ip_src.ipv6_addr[3];
437 input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv6_addr[0];
438 input->formatted.dst_ip[1] = fdir_filter->ip_dst.ipv6_addr[1];
439 input->formatted.dst_ip[2] = fdir_filter->ip_dst.ipv6_addr[2];
440 input->formatted.dst_ip[3] = fdir_filter->ip_dst.ipv6_addr[3];
443 input->formatted.src_ip[0] = fdir_filter->ip_src.ipv4_addr;
444 input->formatted.dst_ip[0] = fdir_filter->ip_dst.ipv4_addr;
451 * Adds or updates a signature filter.
453 * dev: ethernet device to add filter to
454 * fdir_filter: filter details
455 * queue: queue index to direct traffic to
456 * update: 0 to add a new filter, otherwise update existing.
459 fdir_add_update_signature_filter(struct rte_eth_dev *dev,
460 struct rte_fdir_filter *fdir_filter, uint8_t queue, int update)
462 struct ixgbe_hw *hw= IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
463 uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
465 union ixgbe_atr_input input;
468 if (hw->mac.type != ixgbe_mac_82599EB)
471 err = fdir_filter_to_atr_input(fdir_filter, &input);
475 fdirhash = atr_compute_sig_hash_82599(&input,
476 dev->data->dev_conf.fdir_conf.pballoc);
477 fdir_add_signature_filter_82599(hw, &input, queue, fdircmd_flags,
483 ixgbe_fdir_add_signature_filter(struct rte_eth_dev *dev,
484 struct rte_fdir_filter *fdir_filter, uint8_t queue)
486 PMD_INIT_FUNC_TRACE();
487 return fdir_add_update_signature_filter(dev, fdir_filter, queue, 0);
491 ixgbe_fdir_update_signature_filter(struct rte_eth_dev *dev,
492 struct rte_fdir_filter *fdir_filter, uint8_t queue)
494 PMD_INIT_FUNC_TRACE();
495 return fdir_add_update_signature_filter(dev, fdir_filter, queue, 1);
499 * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
500 * ixgbe/ixgbe_82599.c. It is modified to take in the hash as a parameter so
501 * that it can be used for removing signature and perfect filters.
504 fdir_erase_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input,
511 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
513 /* flush hash to HW */
514 IXGBE_WRITE_FLUSH(hw);
516 /* Query if filter is present */
517 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
519 for (retry_count = 10; retry_count; retry_count--) {
520 /* allow 10us for query to process */
522 /* verify query completed successfully */
523 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
524 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
529 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter");
533 /* if filter exists in hardware then remove it */
534 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
535 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
536 IXGBE_WRITE_FLUSH(hw);
537 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
538 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
545 ixgbe_fdir_remove_signature_filter(struct rte_eth_dev *dev,
546 struct rte_fdir_filter *fdir_filter)
548 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
549 union ixgbe_atr_input input;
552 PMD_INIT_FUNC_TRACE();
554 if (hw->mac.type != ixgbe_mac_82599EB)
557 err = fdir_filter_to_atr_input(fdir_filter, &input);
561 return fdir_erase_filter_82599(hw, &input,
562 atr_compute_sig_hash_82599(&input,
563 dev->data->dev_conf.fdir_conf.pballoc));
567 * This is based on ixgbe_get_fdirtcpm_82599(), in ixgbe/ixgbe_82599.c. It no
568 * longer does the byte reordering
570 * generate a tcp port from atr_input_masks
571 * @input_mask: mask to be bit swapped
573 * The source and destination port masks for flow director are bit swapped
574 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
575 * generate a correctly swapped value we need to bit swap the mask and that
576 * is what is accomplished by this function.
579 get_fdirtcpm_82599(struct rte_fdir_masks *input_mask)
581 u32 mask = input_mask->dst_port_mask;
582 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
583 mask |= input_mask->src_port_mask;
584 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
585 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
586 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
587 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
591 * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses
592 * the bytes, and then reverses them again. So here it does nothing.
594 #define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG
597 * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
598 * but makes use of the rte_fdir_masks structure to see which bits to set.
601 fdir_set_input_mask_82599(struct ixgbe_hw *hw,
602 struct rte_fdir_masks *input_mask)
604 /* mask VM pool and IPv6 since it is currently not supported */
605 u32 fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
608 PMD_INIT_FUNC_TRACE();
611 * Program the relevant mask registers. If src/dst_port or src/dst_addr
612 * are zero, then assume a full mask for that field. Also assume that
613 * a VLAN of 0 is unspecified, so mask that out as well. L4type
614 * cannot be masked out in this implementation.
616 * This also assumes IPv4 only. IPv6 masking isn't supported at this
619 if (input_mask->only_ip_flow) {
620 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
621 fdirm |= IXGBE_FDIRM_L4P;
622 if (input_mask->dst_port_mask || input_mask->src_port_mask) {
623 PMD_INIT_LOG(ERR, " Error on src/dst port mask\n");
628 if (!input_mask->vlan_id)
630 fdirm |= IXGBE_FDIRM_VLANID;
632 if (!input_mask->vlan_prio)
633 /* mask VLAN priority */
634 fdirm |= IXGBE_FDIRM_VLANP;
636 if (!input_mask->flexbytes)
637 /* Mask Flex Bytes */
638 fdirm |= IXGBE_FDIRM_FLEX;
640 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
642 /* store the TCP/UDP port masks, bit reversed from port layout */
643 fdirtcpm = get_fdirtcpm_82599(input_mask);
645 /* write both the same so that UDP and TCP use the same mask */
646 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
647 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
649 /* store source and destination IP masks (big-enian) */
650 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
651 IXGBE_NTOHL(~input_mask->src_ipv4_mask));
652 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
653 IXGBE_NTOHL(~input_mask->dst_ipv4_mask));
655 return IXGBE_SUCCESS;
659 ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks)
664 PMD_INIT_FUNC_TRACE();
666 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
668 if (hw->mac.type != ixgbe_mac_82599EB)
671 err = ixgbe_reinit_fdir_tables_82599(hw);
673 PMD_INIT_LOG(ERR, "reinit of fdir tables failed");
677 return fdir_set_input_mask_82599(hw, fdir_masks);
681 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
682 enum rte_fdir_pballoc_type pballoc)
684 if (pballoc == RTE_FDIR_PBALLOC_256K)
685 return ixgbe_atr_compute_hash_82599(input,
686 IXGBE_ATR_BUCKET_HASH_KEY) &
687 PERFECT_BUCKET_256KB_HASH_MASK;
688 else if (pballoc == RTE_FDIR_PBALLOC_128K)
689 return ixgbe_atr_compute_hash_82599(input,
690 IXGBE_ATR_BUCKET_HASH_KEY) &
691 PERFECT_BUCKET_128KB_HASH_MASK;
693 return ixgbe_atr_compute_hash_82599(input,
694 IXGBE_ATR_BUCKET_HASH_KEY) &
695 PERFECT_BUCKET_64KB_HASH_MASK;
699 * This is based on ixgbe_fdir_write_perfect_filter_82599() in
700 * ixgbe/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
701 * added, and IPv6 support also added. The hash value is also pre-calculated
702 * as the pballoc value is needed to do it.
705 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, union ixgbe_atr_input *input,
706 uint16_t soft_id, uint8_t queue, uint32_t fdircmd,
709 u32 fdirport, fdirvlan;
711 /* record the source address (big-endian) */
712 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
713 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), input->formatted.src_ip[0]);
714 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), input->formatted.src_ip[1]);
715 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.src_ip[2]);
716 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[3]);
719 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
722 /* record the first 32 bits of the destination address (big-endian) */
723 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
725 /* record source and destination port (little-endian)*/
726 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
727 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
728 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
729 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
731 /* record vlan (little-endian) and flex_bytes(big-endian) */
732 fdirvlan = input->formatted.flex_bytes;
733 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
734 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
735 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
737 /* configure FDIRHASH register */
738 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
739 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
742 * flush all previous writes to make certain registers are
743 * programmed prior to issuing the command
745 IXGBE_WRITE_FLUSH(hw);
747 /* configure FDIRCMD register */
748 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
749 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
750 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
751 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
752 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
754 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
758 * Adds or updates a perfect filter.
760 * dev: ethernet device to add filter to
761 * fdir_filter: filter details
762 * soft_id: software index for the filters
763 * queue: queue index to direct traffic to
764 * drop: non-zero if packets should be sent to the drop queue
765 * update: 0 to add a new filter, otherwise update existing.
768 fdir_add_update_perfect_filter(struct rte_eth_dev *dev,
769 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
770 uint8_t queue, int drop, int update)
772 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
773 uint32_t fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
775 union ixgbe_atr_input input;
778 if (hw->mac.type != ixgbe_mac_82599EB)
781 err = fdir_filter_to_atr_input(fdir_filter, &input);
786 queue = dev->data->dev_conf.fdir_conf.drop_queue;
787 fdircmd_flags |= IXGBE_FDIRCMD_DROP;
790 fdirhash = atr_compute_perfect_hash_82599(&input,
791 dev->data->dev_conf.fdir_conf.pballoc);
793 fdir_write_perfect_filter_82599(hw, &input, soft_id, queue,
794 fdircmd_flags, fdirhash);
799 ixgbe_fdir_add_perfect_filter(struct rte_eth_dev *dev,
800 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
801 uint8_t queue, uint8_t drop)
803 PMD_INIT_FUNC_TRACE();
804 return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue,
809 ixgbe_fdir_update_perfect_filter(struct rte_eth_dev *dev,
810 struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
811 uint8_t queue, uint8_t drop)
813 PMD_INIT_FUNC_TRACE();
814 return fdir_add_update_perfect_filter(dev, fdir_filter, soft_id, queue,
819 ixgbe_fdir_remove_perfect_filter(struct rte_eth_dev *dev,
820 struct rte_fdir_filter *fdir_filter,
823 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
824 union ixgbe_atr_input input;
828 PMD_INIT_FUNC_TRACE();
830 if (hw->mac.type != ixgbe_mac_82599EB)
833 err = fdir_filter_to_atr_input(fdir_filter, &input);
837 /* configure FDIRHASH register */
838 fdirhash = atr_compute_perfect_hash_82599(&input,
839 dev->data->dev_conf.fdir_conf.pballoc);
840 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
842 return fdir_erase_filter_82599(hw, &input, fdirhash);
846 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
848 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
849 struct ixgbe_hw_fdir_info *info =
850 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
853 if (hw->mac.type != ixgbe_mac_82599EB)
856 /* Get the information from registers */
857 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
858 info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
859 IXGBE_FDIRFREE_COLL_SHIFT);
860 info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
861 IXGBE_FDIRFREE_FREE_SHIFT);
863 reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
864 info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
865 IXGBE_FDIRLEN_MAXHASH_SHIFT);
866 info->maxlen = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
867 IXGBE_FDIRLEN_MAXLEN_SHIFT);
869 reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
870 info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
871 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
872 info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
873 IXGBE_FDIRUSTAT_ADD_SHIFT;
875 reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
876 info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
877 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
878 info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
879 IXGBE_FDIRFSTAT_FADD_SHIFT;
881 /* Copy the new information in the fdir parameter */
882 fdir->collision = info->collision;
883 fdir->free = info->free;
884 fdir->maxhash = info->maxhash;
885 fdir->maxlen = info->maxlen;
886 fdir->remove = info->remove;
887 fdir->add = info->add;
888 fdir->f_remove = info->f_remove;
889 fdir->f_add = info->f_add;