4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "ixgbe_logs.h"
75 #include "ixgbe/ixgbe_api.h"
76 #include "ixgbe/ixgbe_vf.h"
77 #include "ixgbe_ethdev.h"
78 #include "ixgbe/ixgbe_dcb.h"
79 #include "ixgbe/ixgbe_common.h"
80 #include "ixgbe_rxtx.h"
82 /* Bit Mask to indicate what bits required for building TX context */
83 #define IXGBE_TX_OFFLOAD_MASK ( \
89 static inline struct rte_mbuf *
90 rte_rxmbuf_alloc(struct rte_mempool *mp)
94 m = __rte_mbuf_raw_alloc(mp);
95 __rte_mbuf_sanity_check_raw(m, 0);
101 #define RTE_PMD_USE_PREFETCH
104 #ifdef RTE_PMD_USE_PREFETCH
106 * Prefetch a cache line into all cache levels.
108 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
110 #define rte_ixgbe_prefetch(p) do {} while(0)
113 /*********************************************************************
117 **********************************************************************/
120 * Check for descriptors with their DD bit set and free mbufs.
121 * Return the total number of buffers freed.
123 static inline int __attribute__((always_inline))
124 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
126 struct ixgbe_tx_entry *txep;
130 /* check DD bit on threshold descriptor */
131 status = txq->tx_ring[txq->tx_next_dd].wb.status;
132 if (! (status & IXGBE_ADVTXD_STAT_DD))
136 * first buffer to free from S/W ring is at index
137 * tx_next_dd - (tx_rs_thresh-1)
139 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
141 /* free buffers one at a time */
142 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
143 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
144 txep->mbuf->next = NULL;
145 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
149 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
150 rte_pktmbuf_free_seg(txep->mbuf);
155 /* buffers were freed, update counters */
156 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
157 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
158 if (txq->tx_next_dd >= txq->nb_tx_desc)
159 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
161 return txq->tx_rs_thresh;
164 /* Populate 4 descriptors with data from 4 mbufs */
166 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
168 uint64_t buf_dma_addr;
172 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
173 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
174 pkt_len = (*pkts)->data_len;
176 /* write data to descriptor */
177 txdp->read.buffer_addr = buf_dma_addr;
178 txdp->read.cmd_type_len =
179 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
180 txdp->read.olinfo_status =
181 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
182 rte_prefetch0(&(*pkts)->pool);
186 /* Populate 1 descriptor with data from 1 mbuf */
188 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
190 uint64_t buf_dma_addr;
193 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
194 pkt_len = (*pkts)->data_len;
196 /* write data to descriptor */
197 txdp->read.buffer_addr = buf_dma_addr;
198 txdp->read.cmd_type_len =
199 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
200 txdp->read.olinfo_status =
201 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
202 rte_prefetch0(&(*pkts)->pool);
206 * Fill H/W descriptor ring with mbuf data.
207 * Copy mbuf pointers to the S/W ring.
210 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
213 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
214 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
215 const int N_PER_LOOP = 4;
216 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
217 int mainpart, leftover;
221 * Process most of the packets in chunks of N pkts. Any
222 * leftover packets will get processed one at a time.
224 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
225 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
226 for (i = 0; i < mainpart; i += N_PER_LOOP) {
227 /* Copy N mbuf pointers to the S/W ring */
228 for (j = 0; j < N_PER_LOOP; ++j) {
229 (txep + i + j)->mbuf = *(pkts + i + j);
231 tx4(txdp + i, pkts + i);
234 if (unlikely(leftover > 0)) {
235 for (i = 0; i < leftover; ++i) {
236 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
237 tx1(txdp + mainpart + i, pkts + mainpart + i);
242 static inline uint16_t
243 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
246 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
247 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
251 * Begin scanning the H/W ring for done descriptors when the
252 * number of available descriptors drops below tx_free_thresh. For
253 * each done descriptor, free the associated buffer.
255 if (txq->nb_tx_free < txq->tx_free_thresh)
256 ixgbe_tx_free_bufs(txq);
258 /* Only use descriptors that are available */
259 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
260 if (unlikely(nb_pkts == 0))
263 /* Use exactly nb_pkts descriptors */
264 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
267 * At this point, we know there are enough descriptors in the
268 * ring to transmit all the packets. This assumes that each
269 * mbuf contains a single segment, and that no new offloads
270 * are expected, which would require a new context descriptor.
274 * See if we're going to wrap-around. If so, handle the top
275 * of the descriptor ring first, then do the bottom. If not,
276 * the processing looks just like the "bottom" part anyway...
278 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
279 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
280 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
283 * We know that the last descriptor in the ring will need to
284 * have its RS bit set because tx_rs_thresh has to be
285 * a divisor of the ring size
287 tx_r[txq->tx_next_rs].read.cmd_type_len |=
288 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
289 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
294 /* Fill H/W descriptor ring with mbuf data */
295 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
296 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
299 * Determine if RS bit should be set
300 * This is what we actually want:
301 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
302 * but instead of subtracting 1 and doing >=, we can just do
303 * greater than without subtracting.
305 if (txq->tx_tail > txq->tx_next_rs) {
306 tx_r[txq->tx_next_rs].read.cmd_type_len |=
307 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
308 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
310 if (txq->tx_next_rs >= txq->nb_tx_desc)
311 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
315 * Check for wrap-around. This would only happen if we used
316 * up to the last descriptor in the ring, no more, no less.
318 if (txq->tx_tail >= txq->nb_tx_desc)
321 /* update tail pointer */
323 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
329 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
334 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
335 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
336 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
338 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
342 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
343 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
344 nb_tx = (uint16_t)(nb_tx + ret);
345 nb_pkts = (uint16_t)(nb_pkts - ret);
354 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
355 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
356 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
358 uint32_t type_tucmd_mlhl;
359 uint32_t mss_l4len_idx = 0;
361 uint32_t vlan_macip_lens;
362 union ixgbe_tx_offload tx_offload_mask;
364 ctx_idx = txq->ctx_curr;
365 tx_offload_mask.data = 0;
368 /* Specify which HW CTX to upload. */
369 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
371 if (ol_flags & PKT_TX_VLAN_PKT) {
372 tx_offload_mask.vlan_tci |= ~0;
375 /* check if TCP segmentation required for this packet */
376 if (ol_flags & PKT_TX_TCP_SEG) {
377 /* implies IP cksum and TCP cksum */
378 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
379 IXGBE_ADVTXD_TUCMD_L4T_TCP |
380 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
382 tx_offload_mask.l2_len |= ~0;
383 tx_offload_mask.l3_len |= ~0;
384 tx_offload_mask.l4_len |= ~0;
385 tx_offload_mask.tso_segsz |= ~0;
386 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
387 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
388 } else { /* no TSO, check if hardware checksum is needed */
389 if (ol_flags & PKT_TX_IP_CKSUM) {
390 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
391 tx_offload_mask.l2_len |= ~0;
392 tx_offload_mask.l3_len |= ~0;
395 switch (ol_flags & PKT_TX_L4_MASK) {
396 case PKT_TX_UDP_CKSUM:
397 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
398 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
399 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
400 tx_offload_mask.l2_len |= ~0;
401 tx_offload_mask.l3_len |= ~0;
403 case PKT_TX_TCP_CKSUM:
404 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
405 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
406 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
407 tx_offload_mask.l2_len |= ~0;
408 tx_offload_mask.l3_len |= ~0;
409 tx_offload_mask.l4_len |= ~0;
411 case PKT_TX_SCTP_CKSUM:
412 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
413 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
414 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
415 tx_offload_mask.l2_len |= ~0;
416 tx_offload_mask.l3_len |= ~0;
419 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
420 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
425 txq->ctx_cache[ctx_idx].flags = ol_flags;
426 txq->ctx_cache[ctx_idx].tx_offload.data =
427 tx_offload_mask.data & tx_offload.data;
428 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
430 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
431 vlan_macip_lens = tx_offload.l3_len;
432 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
433 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
434 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
435 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
436 ctx_txd->seqnum_seed = 0;
440 * Check which hardware context can be used. Use the existing match
441 * or create a new context descriptor.
443 static inline uint32_t
444 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
445 union ixgbe_tx_offload tx_offload)
447 /* If match with the current used context */
448 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
449 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
450 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
451 return txq->ctx_curr;
454 /* What if match with the next context */
456 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
457 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
458 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
459 return txq->ctx_curr;
462 /* Mismatch, use the previous context */
463 return (IXGBE_CTX_NUM);
466 static inline uint32_t
467 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
470 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
471 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
472 if (ol_flags & PKT_TX_IP_CKSUM)
473 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
474 if (ol_flags & PKT_TX_TCP_SEG)
475 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
479 static inline uint32_t
480 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
482 uint32_t cmdtype = 0;
483 if (ol_flags & PKT_TX_VLAN_PKT)
484 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
485 if (ol_flags & PKT_TX_TCP_SEG)
486 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
490 /* Default RS bit threshold values */
491 #ifndef DEFAULT_TX_RS_THRESH
492 #define DEFAULT_TX_RS_THRESH 32
494 #ifndef DEFAULT_TX_FREE_THRESH
495 #define DEFAULT_TX_FREE_THRESH 32
498 /* Reset transmit descriptors after they have been used */
500 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
502 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
503 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
504 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
505 uint16_t nb_tx_desc = txq->nb_tx_desc;
506 uint16_t desc_to_clean_to;
507 uint16_t nb_tx_to_clean;
509 /* Determine the last descriptor needing to be cleaned */
510 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
511 if (desc_to_clean_to >= nb_tx_desc)
512 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
514 /* Check to make sure the last descriptor to clean is done */
515 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
516 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
518 PMD_TX_FREE_LOG(DEBUG,
519 "TX descriptor %4u is not done"
520 "(port=%d queue=%d)",
522 txq->port_id, txq->queue_id);
523 /* Failed to clean any descriptors, better luck next time */
527 /* Figure out how many descriptors will be cleaned */
528 if (last_desc_cleaned > desc_to_clean_to)
529 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
532 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
535 PMD_TX_FREE_LOG(DEBUG,
536 "Cleaning %4u TX descriptors: %4u to %4u "
537 "(port=%d queue=%d)",
538 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
539 txq->port_id, txq->queue_id);
542 * The last descriptor to clean is done, so that means all the
543 * descriptors from the last descriptor that was cleaned
544 * up to the last descriptor with the RS bit set
545 * are done. Only reset the threshold descriptor.
547 txr[desc_to_clean_to].wb.status = 0;
549 /* Update the txq to reflect the last descriptor that was cleaned */
550 txq->last_desc_cleaned = desc_to_clean_to;
551 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
558 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
561 struct ixgbe_tx_queue *txq;
562 struct ixgbe_tx_entry *sw_ring;
563 struct ixgbe_tx_entry *txe, *txn;
564 volatile union ixgbe_adv_tx_desc *txr;
565 volatile union ixgbe_adv_tx_desc *txd;
566 struct rte_mbuf *tx_pkt;
567 struct rte_mbuf *m_seg;
568 uint64_t buf_dma_addr;
569 uint32_t olinfo_status;
570 uint32_t cmd_type_len;
581 union ixgbe_tx_offload tx_offload = { .data = 0 };
584 sw_ring = txq->sw_ring;
586 tx_id = txq->tx_tail;
587 txe = &sw_ring[tx_id];
589 /* Determine if the descriptor ring needs to be cleaned. */
590 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh) {
591 ixgbe_xmit_cleanup(txq);
594 rte_prefetch0(&txe->mbuf->pool);
597 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
600 pkt_len = tx_pkt->pkt_len;
603 * Determine how many (if any) context descriptors
604 * are needed for offload functionality.
606 ol_flags = tx_pkt->ol_flags;
608 /* If hardware offload required */
609 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
611 tx_offload.l2_len = tx_pkt->l2_len;
612 tx_offload.l3_len = tx_pkt->l3_len;
613 tx_offload.l4_len = tx_pkt->l4_len;
614 tx_offload.vlan_tci = tx_pkt->vlan_tci;
615 tx_offload.tso_segsz = tx_pkt->tso_segsz;
617 /* If new context need be built or reuse the exist ctx. */
618 ctx = what_advctx_update(txq, tx_ol_req,
620 /* Only allocate context descriptor if required*/
621 new_ctx = (ctx == IXGBE_CTX_NUM);
626 * Keep track of how many descriptors are used this loop
627 * This will always be the number of segments + the number of
628 * Context descriptors required to transmit the packet
630 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
633 * The number of descriptors that must be allocated for a
634 * packet is the number of segments of that packet, plus 1
635 * Context Descriptor for the hardware offload, if any.
636 * Determine the last TX descriptor to allocate in the TX ring
637 * for the packet, starting from the current position (tx_id)
640 tx_last = (uint16_t) (tx_id + nb_used - 1);
643 if (tx_last >= txq->nb_tx_desc)
644 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
646 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
647 " tx_first=%u tx_last=%u",
648 (unsigned) txq->port_id,
649 (unsigned) txq->queue_id,
655 * Make sure there are enough TX descriptors available to
656 * transmit the entire packet.
657 * nb_used better be less than or equal to txq->tx_rs_thresh
659 if (nb_used > txq->nb_tx_free) {
660 PMD_TX_FREE_LOG(DEBUG,
661 "Not enough free TX descriptors "
662 "nb_used=%4u nb_free=%4u "
663 "(port=%d queue=%d)",
664 nb_used, txq->nb_tx_free,
665 txq->port_id, txq->queue_id);
667 if (ixgbe_xmit_cleanup(txq) != 0) {
668 /* Could not clean any descriptors */
674 /* nb_used better be <= txq->tx_rs_thresh */
675 if (unlikely(nb_used > txq->tx_rs_thresh)) {
676 PMD_TX_FREE_LOG(DEBUG,
677 "The number of descriptors needed to "
678 "transmit the packet exceeds the "
679 "RS bit threshold. This will impact "
681 "nb_used=%4u nb_free=%4u "
683 "(port=%d queue=%d)",
684 nb_used, txq->nb_tx_free,
686 txq->port_id, txq->queue_id);
688 * Loop here until there are enough TX
689 * descriptors or until the ring cannot be
692 while (nb_used > txq->nb_tx_free) {
693 if (ixgbe_xmit_cleanup(txq) != 0) {
695 * Could not clean any
707 * By now there are enough free TX descriptors to transmit
712 * Set common flags of all TX Data Descriptors.
714 * The following bits must be set in all Data Descriptors:
715 * - IXGBE_ADVTXD_DTYP_DATA
716 * - IXGBE_ADVTXD_DCMD_DEXT
718 * The following bits must be set in the first Data Descriptor
719 * and are ignored in the other ones:
720 * - IXGBE_ADVTXD_DCMD_IFCS
721 * - IXGBE_ADVTXD_MAC_1588
722 * - IXGBE_ADVTXD_DCMD_VLE
724 * The following bits must only be set in the last Data
726 * - IXGBE_TXD_CMD_EOP
728 * The following bits can be set in any Data Descriptor, but
729 * are only set in the last Data Descriptor:
732 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
733 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
735 #ifdef RTE_LIBRTE_IEEE1588
736 if (ol_flags & PKT_TX_IEEE1588_TMST)
737 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
743 if (ol_flags & PKT_TX_TCP_SEG) {
744 /* when TSO is on, paylen in descriptor is the
745 * not the packet len but the tcp payload len */
746 pkt_len -= (tx_offload.l2_len +
747 tx_offload.l3_len + tx_offload.l4_len);
751 * Setup the TX Advanced Context Descriptor if required
754 volatile struct ixgbe_adv_tx_context_desc *
757 ctx_txd = (volatile struct
758 ixgbe_adv_tx_context_desc *)
761 txn = &sw_ring[txe->next_id];
762 rte_prefetch0(&txn->mbuf->pool);
764 if (txe->mbuf != NULL) {
765 rte_pktmbuf_free_seg(txe->mbuf);
769 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
772 txe->last_id = tx_last;
773 tx_id = txe->next_id;
778 * Setup the TX Advanced Data Descriptor,
779 * This path will go through
780 * whatever new/reuse the context descriptor
782 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
783 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
784 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
787 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
792 txn = &sw_ring[txe->next_id];
793 rte_prefetch0(&txn->mbuf->pool);
795 if (txe->mbuf != NULL)
796 rte_pktmbuf_free_seg(txe->mbuf);
800 * Set up Transmit Data Descriptor.
802 slen = m_seg->data_len;
803 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
804 txd->read.buffer_addr =
805 rte_cpu_to_le_64(buf_dma_addr);
806 txd->read.cmd_type_len =
807 rte_cpu_to_le_32(cmd_type_len | slen);
808 txd->read.olinfo_status =
809 rte_cpu_to_le_32(olinfo_status);
810 txe->last_id = tx_last;
811 tx_id = txe->next_id;
814 } while (m_seg != NULL);
817 * The last packet data descriptor needs End Of Packet (EOP)
819 cmd_type_len |= IXGBE_TXD_CMD_EOP;
820 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
821 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
823 /* Set RS bit only on threshold packets' last descriptor */
824 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
825 PMD_TX_FREE_LOG(DEBUG,
826 "Setting RS bit on TXD id="
827 "%4u (port=%d queue=%d)",
828 tx_last, txq->port_id, txq->queue_id);
830 cmd_type_len |= IXGBE_TXD_CMD_RS;
832 /* Update txq RS bit counters */
835 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
841 * Set the Transmit Descriptor Tail (TDT)
843 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
844 (unsigned) txq->port_id, (unsigned) txq->queue_id,
845 (unsigned) tx_id, (unsigned) nb_tx);
846 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
847 txq->tx_tail = tx_id;
852 /*********************************************************************
856 **********************************************************************/
857 static inline uint64_t
858 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
862 static const uint64_t ip_pkt_types_map[16] = {
863 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
864 PKT_RX_IPV6_HDR, 0, 0, 0,
865 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
866 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
869 static const uint64_t ip_rss_types_map[16] = {
870 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
871 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
872 PKT_RX_RSS_HASH, 0, 0, 0,
873 0, 0, 0, PKT_RX_FDIR,
876 #ifdef RTE_LIBRTE_IEEE1588
877 static uint64_t ip_pkt_etqf_map[8] = {
878 0, 0, 0, PKT_RX_IEEE1588_PTP,
882 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
883 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
884 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
886 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
887 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
890 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
893 static inline uint64_t
894 rx_desc_status_to_pkt_flags(uint32_t rx_status)
899 * Check if VLAN present only.
900 * Do not check whether L3/L4 rx checksum done by NIC or not,
901 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
903 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
905 #ifdef RTE_LIBRTE_IEEE1588
906 if (rx_status & IXGBE_RXD_STAT_TMST)
907 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
912 static inline uint64_t
913 rx_desc_error_to_pkt_flags(uint32_t rx_status)
916 * Bit 31: IPE, IPv4 checksum error
917 * Bit 30: L4I, L4I integrity error
919 static uint64_t error_to_pkt_flags_map[4] = {
920 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
921 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
923 return error_to_pkt_flags_map[(rx_status >>
924 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
927 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
929 * LOOK_AHEAD defines how many desc statuses to check beyond the
930 * current descriptor.
931 * It must be a pound define for optimal performance.
932 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
933 * function only works with LOOK_AHEAD=8.
936 #if (LOOK_AHEAD != 8)
937 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
940 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
942 volatile union ixgbe_adv_rx_desc *rxdp;
943 struct ixgbe_rx_entry *rxep;
947 int s[LOOK_AHEAD], nb_dd;
951 /* get references to current descriptor and S/W ring entry */
952 rxdp = &rxq->rx_ring[rxq->rx_tail];
953 rxep = &rxq->sw_ring[rxq->rx_tail];
955 /* check to make sure there is at least 1 packet to receive */
956 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
960 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
961 * reference packets that are ready to be received.
963 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
964 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
966 /* Read desc statuses backwards to avoid race condition */
967 for (j = LOOK_AHEAD-1; j >= 0; --j)
968 s[j] = rxdp[j].wb.upper.status_error;
970 /* Compute how many status bits were set */
972 for (j = 0; j < LOOK_AHEAD; ++j)
973 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
977 /* Translate descriptor info to mbuf format */
978 for (j = 0; j < nb_dd; ++j) {
980 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
981 mb->data_len = pkt_len;
982 mb->pkt_len = pkt_len;
983 mb->vlan_tci = rxdp[j].wb.upper.vlan;
984 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
986 /* convert descriptor fields to rte mbuf flags */
987 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
988 rxdp[j].wb.lower.lo_dword.data);
989 /* reuse status field from scan list */
990 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
991 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
992 mb->ol_flags = pkt_flags;
994 if (likely(pkt_flags & PKT_RX_RSS_HASH))
995 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
996 else if (pkt_flags & PKT_RX_FDIR) {
998 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
999 & IXGBE_ATR_HASH_MASK);
1000 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1004 /* Move mbuf pointers from the S/W ring to the stage */
1005 for (j = 0; j < LOOK_AHEAD; ++j) {
1006 rxq->rx_stage[i + j] = rxep[j].mbuf;
1009 /* stop if all requested packets could not be received */
1010 if (nb_dd != LOOK_AHEAD)
1014 /* clear software ring entries so we can cleanup correctly */
1015 for (i = 0; i < nb_rx; ++i) {
1016 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1024 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq)
1026 volatile union ixgbe_adv_rx_desc *rxdp;
1027 struct ixgbe_rx_entry *rxep;
1028 struct rte_mbuf *mb;
1033 /* allocate buffers in bulk directly into the S/W ring */
1034 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1035 (rxq->rx_free_thresh - 1));
1036 rxep = &rxq->sw_ring[alloc_idx];
1037 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1038 rxq->rx_free_thresh);
1039 if (unlikely(diag != 0))
1042 rxdp = &rxq->rx_ring[alloc_idx];
1043 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1044 /* populate the static rte mbuf fields */
1046 rte_mbuf_refcnt_set(mb, 1);
1048 mb->data_off = RTE_PKTMBUF_HEADROOM;
1050 mb->port = rxq->port_id;
1052 /* populate the descriptors */
1053 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1054 rxdp[i].read.hdr_addr = dma_addr;
1055 rxdp[i].read.pkt_addr = dma_addr;
1058 /* update tail pointer */
1060 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rxq->rx_free_trigger);
1062 /* update state of internal queue structure */
1063 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_trigger +
1064 rxq->rx_free_thresh);
1065 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1066 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1072 static inline uint16_t
1073 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1076 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1079 /* how many packets are ready to return? */
1080 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1082 /* copy mbuf pointers to the application's packet list */
1083 for (i = 0; i < nb_pkts; ++i)
1084 rx_pkts[i] = stage[i];
1086 /* update internal queue state */
1087 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1088 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1093 static inline uint16_t
1094 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1097 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1100 /* Any previously recv'd pkts will be returned from the Rx stage */
1101 if (rxq->rx_nb_avail)
1102 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1104 /* Scan the H/W ring for packets to receive */
1105 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1107 /* update internal queue state */
1108 rxq->rx_next_avail = 0;
1109 rxq->rx_nb_avail = nb_rx;
1110 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1112 /* if required, allocate new buffers to replenish descriptors */
1113 if (rxq->rx_tail > rxq->rx_free_trigger) {
1114 if (ixgbe_rx_alloc_bufs(rxq) != 0) {
1116 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1117 "queue_id=%u", (unsigned) rxq->port_id,
1118 (unsigned) rxq->queue_id);
1120 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1121 rxq->rx_free_thresh;
1124 * Need to rewind any previous receives if we cannot
1125 * allocate new buffers to replenish the old ones.
1127 rxq->rx_nb_avail = 0;
1128 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1129 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1130 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1136 if (rxq->rx_tail >= rxq->nb_rx_desc)
1139 /* received any packets this loop? */
1140 if (rxq->rx_nb_avail)
1141 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1146 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1148 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1153 if (unlikely(nb_pkts == 0))
1156 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1157 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1159 /* request is relatively large, chunk it up */
1163 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1164 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1165 nb_rx = (uint16_t)(nb_rx + ret);
1166 nb_pkts = (uint16_t)(nb_pkts - ret);
1176 /* Stub to avoid extra ifdefs */
1178 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1179 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1184 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1187 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1190 struct ixgbe_rx_queue *rxq;
1191 volatile union ixgbe_adv_rx_desc *rx_ring;
1192 volatile union ixgbe_adv_rx_desc *rxdp;
1193 struct ixgbe_rx_entry *sw_ring;
1194 struct ixgbe_rx_entry *rxe;
1195 struct rte_mbuf *rxm;
1196 struct rte_mbuf *nmb;
1197 union ixgbe_adv_rx_desc rxd;
1200 uint32_t hlen_type_rss;
1210 rx_id = rxq->rx_tail;
1211 rx_ring = rxq->rx_ring;
1212 sw_ring = rxq->sw_ring;
1213 while (nb_rx < nb_pkts) {
1215 * The order of operations here is important as the DD status
1216 * bit must not be read after any other descriptor fields.
1217 * rx_ring and rxdp are pointing to volatile data so the order
1218 * of accesses cannot be reordered by the compiler. If they were
1219 * not volatile, they could be reordered which could lead to
1220 * using invalid descriptor fields when read from rxd.
1222 rxdp = &rx_ring[rx_id];
1223 staterr = rxdp->wb.upper.status_error;
1224 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1231 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1232 * is likely to be invalid and to be dropped by the various
1233 * validation checks performed by the network stack.
1235 * Allocate a new mbuf to replenish the RX ring descriptor.
1236 * If the allocation fails:
1237 * - arrange for that RX descriptor to be the first one
1238 * being parsed the next time the receive function is
1239 * invoked [on the same queue].
1241 * - Stop parsing the RX ring and return immediately.
1243 * This policy do not drop the packet received in the RX
1244 * descriptor for which the allocation of a new mbuf failed.
1245 * Thus, it allows that packet to be later retrieved if
1246 * mbuf have been freed in the mean time.
1247 * As a side effect, holding RX descriptors instead of
1248 * systematically giving them back to the NIC may lead to
1249 * RX ring exhaustion situations.
1250 * However, the NIC can gracefully prevent such situations
1251 * to happen by sending specific "back-pressure" flow control
1252 * frames to its peer(s).
1254 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1255 "ext_err_stat=0x%08x pkt_len=%u",
1256 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1257 (unsigned) rx_id, (unsigned) staterr,
1258 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1260 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1262 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1263 "queue_id=%u", (unsigned) rxq->port_id,
1264 (unsigned) rxq->queue_id);
1265 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1270 rxe = &sw_ring[rx_id];
1272 if (rx_id == rxq->nb_rx_desc)
1275 /* Prefetch next mbuf while processing current one. */
1276 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1279 * When next RX descriptor is on a cache-line boundary,
1280 * prefetch the next 4 RX descriptors and the next 8 pointers
1283 if ((rx_id & 0x3) == 0) {
1284 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1285 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1291 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1292 rxdp->read.hdr_addr = dma_addr;
1293 rxdp->read.pkt_addr = dma_addr;
1296 * Initialize the returned mbuf.
1297 * 1) setup generic mbuf fields:
1298 * - number of segments,
1301 * - RX port identifier.
1302 * 2) integrate hardware offload data, if any:
1303 * - RSS flag & hash,
1304 * - IP checksum flag,
1305 * - VLAN TCI, if any,
1308 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1310 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1311 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1314 rxm->pkt_len = pkt_len;
1315 rxm->data_len = pkt_len;
1316 rxm->port = rxq->port_id;
1318 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1319 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1320 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1322 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1323 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1324 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1325 rxm->ol_flags = pkt_flags;
1327 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1328 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1329 else if (pkt_flags & PKT_RX_FDIR) {
1330 rxm->hash.fdir.hash =
1331 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1332 & IXGBE_ATR_HASH_MASK);
1333 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1336 * Store the mbuf address into the next entry of the array
1337 * of returned packets.
1339 rx_pkts[nb_rx++] = rxm;
1341 rxq->rx_tail = rx_id;
1344 * If the number of free RX descriptors is greater than the RX free
1345 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1347 * Update the RDT with the value of the last processed RX descriptor
1348 * minus 1, to guarantee that the RDT register is never equal to the
1349 * RDH register, which creates a "full" ring situtation from the
1350 * hardware point of view...
1352 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1353 if (nb_hold > rxq->rx_free_thresh) {
1354 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1355 "nb_hold=%u nb_rx=%u",
1356 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1357 (unsigned) rx_id, (unsigned) nb_hold,
1359 rx_id = (uint16_t) ((rx_id == 0) ?
1360 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1361 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1364 rxq->nb_rx_hold = nb_hold;
1369 ixgbe_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1372 struct ixgbe_rx_queue *rxq;
1373 volatile union ixgbe_adv_rx_desc *rx_ring;
1374 volatile union ixgbe_adv_rx_desc *rxdp;
1375 struct ixgbe_rx_entry *sw_ring;
1376 struct ixgbe_rx_entry *rxe;
1377 struct rte_mbuf *first_seg;
1378 struct rte_mbuf *last_seg;
1379 struct rte_mbuf *rxm;
1380 struct rte_mbuf *nmb;
1381 union ixgbe_adv_rx_desc rxd;
1382 uint64_t dma; /* Physical address of mbuf data buffer */
1384 uint32_t hlen_type_rss;
1394 rx_id = rxq->rx_tail;
1395 rx_ring = rxq->rx_ring;
1396 sw_ring = rxq->sw_ring;
1399 * Retrieve RX context of current packet, if any.
1401 first_seg = rxq->pkt_first_seg;
1402 last_seg = rxq->pkt_last_seg;
1404 while (nb_rx < nb_pkts) {
1407 * The order of operations here is important as the DD status
1408 * bit must not be read after any other descriptor fields.
1409 * rx_ring and rxdp are pointing to volatile data so the order
1410 * of accesses cannot be reordered by the compiler. If they were
1411 * not volatile, they could be reordered which could lead to
1412 * using invalid descriptor fields when read from rxd.
1414 rxdp = &rx_ring[rx_id];
1415 staterr = rxdp->wb.upper.status_error;
1416 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1423 * Allocate a new mbuf to replenish the RX ring descriptor.
1424 * If the allocation fails:
1425 * - arrange for that RX descriptor to be the first one
1426 * being parsed the next time the receive function is
1427 * invoked [on the same queue].
1429 * - Stop parsing the RX ring and return immediately.
1431 * This policy does not drop the packet received in the RX
1432 * descriptor for which the allocation of a new mbuf failed.
1433 * Thus, it allows that packet to be later retrieved if
1434 * mbuf have been freed in the mean time.
1435 * As a side effect, holding RX descriptors instead of
1436 * systematically giving them back to the NIC may lead to
1437 * RX ring exhaustion situations.
1438 * However, the NIC can gracefully prevent such situations
1439 * to happen by sending specific "back-pressure" flow control
1440 * frames to its peer(s).
1442 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1443 "staterr=0x%x data_len=%u",
1444 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1445 (unsigned) rx_id, (unsigned) staterr,
1446 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1448 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1450 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1451 "queue_id=%u", (unsigned) rxq->port_id,
1452 (unsigned) rxq->queue_id);
1453 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1458 rxe = &sw_ring[rx_id];
1460 if (rx_id == rxq->nb_rx_desc)
1463 /* Prefetch next mbuf while processing current one. */
1464 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1467 * When next RX descriptor is on a cache-line boundary,
1468 * prefetch the next 4 RX descriptors and the next 8 pointers
1471 if ((rx_id & 0x3) == 0) {
1472 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1473 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1477 * Update RX descriptor with the physical address of the new
1478 * data buffer of the new allocated mbuf.
1482 dma = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1483 rxdp->read.hdr_addr = dma;
1484 rxdp->read.pkt_addr = dma;
1487 * Set data length & data buffer address of mbuf.
1489 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1490 rxm->data_len = data_len;
1491 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1494 * If this is the first buffer of the received packet,
1495 * set the pointer to the first mbuf of the packet and
1496 * initialize its context.
1497 * Otherwise, update the total length and the number of segments
1498 * of the current scattered packet, and update the pointer to
1499 * the last mbuf of the current packet.
1501 if (first_seg == NULL) {
1503 first_seg->pkt_len = data_len;
1504 first_seg->nb_segs = 1;
1506 first_seg->pkt_len = (uint16_t)(first_seg->pkt_len
1508 first_seg->nb_segs++;
1509 last_seg->next = rxm;
1513 * If this is not the last buffer of the received packet,
1514 * update the pointer to the last mbuf of the current scattered
1515 * packet and continue to parse the RX ring.
1517 if (! (staterr & IXGBE_RXDADV_STAT_EOP)) {
1523 * This is the last buffer of the received packet.
1524 * If the CRC is not stripped by the hardware:
1525 * - Subtract the CRC length from the total packet length.
1526 * - If the last buffer only contains the whole CRC or a part
1527 * of it, free the mbuf associated to the last buffer.
1528 * If part of the CRC is also contained in the previous
1529 * mbuf, subtract the length of that CRC part from the
1530 * data length of the previous mbuf.
1533 if (unlikely(rxq->crc_len > 0)) {
1534 first_seg->pkt_len -= ETHER_CRC_LEN;
1535 if (data_len <= ETHER_CRC_LEN) {
1536 rte_pktmbuf_free_seg(rxm);
1537 first_seg->nb_segs--;
1538 last_seg->data_len = (uint16_t)
1539 (last_seg->data_len -
1540 (ETHER_CRC_LEN - data_len));
1541 last_seg->next = NULL;
1544 (uint16_t) (data_len - ETHER_CRC_LEN);
1548 * Initialize the first mbuf of the returned packet:
1549 * - RX port identifier,
1550 * - hardware offload data, if any:
1551 * - RSS flag & hash,
1552 * - IP checksum flag,
1553 * - VLAN TCI, if any,
1556 first_seg->port = rxq->port_id;
1559 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1560 * set in the pkt_flags field.
1562 first_seg->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1563 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1564 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1565 pkt_flags = (pkt_flags |
1566 rx_desc_status_to_pkt_flags(staterr));
1567 pkt_flags = (pkt_flags |
1568 rx_desc_error_to_pkt_flags(staterr));
1569 first_seg->ol_flags = pkt_flags;
1571 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1572 first_seg->hash.rss =
1573 rte_le_to_cpu_32(rxd.wb.lower.hi_dword.rss);
1574 else if (pkt_flags & PKT_RX_FDIR) {
1575 first_seg->hash.fdir.hash =
1576 rte_le_to_cpu_16(rxd.wb.lower.hi_dword.csum_ip.csum)
1577 & IXGBE_ATR_HASH_MASK;
1578 first_seg->hash.fdir.id =
1579 rte_le_to_cpu_16(rxd.wb.lower.hi_dword.csum_ip.ip_id);
1582 /* Prefetch data of first segment, if configured to do so. */
1583 rte_packet_prefetch((char *)first_seg->buf_addr +
1584 first_seg->data_off);
1587 * Store the mbuf address into the next entry of the array
1588 * of returned packets.
1590 rx_pkts[nb_rx++] = first_seg;
1593 * Setup receipt context for a new packet.
1599 * Record index of the next RX descriptor to probe.
1601 rxq->rx_tail = rx_id;
1604 * Save receive context.
1606 rxq->pkt_first_seg = first_seg;
1607 rxq->pkt_last_seg = last_seg;
1610 * If the number of free RX descriptors is greater than the RX free
1611 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1613 * Update the RDT with the value of the last processed RX descriptor
1614 * minus 1, to guarantee that the RDT register is never equal to the
1615 * RDH register, which creates a "full" ring situtation from the
1616 * hardware point of view...
1618 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1619 if (nb_hold > rxq->rx_free_thresh) {
1620 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1621 "nb_hold=%u nb_rx=%u",
1622 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1623 (unsigned) rx_id, (unsigned) nb_hold,
1625 rx_id = (uint16_t) ((rx_id == 0) ?
1626 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1627 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1630 rxq->nb_rx_hold = nb_hold;
1634 /*********************************************************************
1636 * Queue management functions
1638 **********************************************************************/
1641 * Rings setup and release.
1643 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1644 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1645 * also optimize cache line size effect. H/W supports up to cache line size 128.
1647 #define IXGBE_ALIGN 128
1650 * Maximum number of Ring Descriptors.
1652 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1653 * descriptors should meet the following condition:
1654 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1656 #define IXGBE_MIN_RING_DESC 32
1657 #define IXGBE_MAX_RING_DESC 4096
1660 * Create memzone for HW rings. malloc can't be used as the physical address is
1661 * needed. If the memzone is already created, then this function returns a ptr
1664 static const struct rte_memzone *
1665 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1666 uint16_t queue_id, uint32_t ring_size, int socket_id)
1668 char z_name[RTE_MEMZONE_NAMESIZE];
1669 const struct rte_memzone *mz;
1671 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1672 dev->driver->pci_drv.name, ring_name,
1673 dev->data->port_id, queue_id);
1675 mz = rte_memzone_lookup(z_name);
1679 #ifdef RTE_LIBRTE_XEN_DOM0
1680 return rte_memzone_reserve_bounded(z_name, ring_size,
1681 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1683 return rte_memzone_reserve_aligned(z_name, ring_size,
1684 socket_id, 0, IXGBE_ALIGN);
1689 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1693 if (txq->sw_ring != NULL) {
1694 for (i = 0; i < txq->nb_tx_desc; i++) {
1695 if (txq->sw_ring[i].mbuf != NULL) {
1696 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1697 txq->sw_ring[i].mbuf = NULL;
1704 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1707 txq->sw_ring != NULL)
1708 rte_free(txq->sw_ring);
1712 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1714 if (txq != NULL && txq->ops != NULL) {
1715 txq->ops->release_mbufs(txq);
1716 txq->ops->free_swring(txq);
1722 ixgbe_dev_tx_queue_release(void *txq)
1724 ixgbe_tx_queue_release(txq);
1727 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1729 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1731 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
1733 struct ixgbe_tx_entry *txe = txq->sw_ring;
1736 /* Zero out HW ring memory */
1737 for (i = 0; i < txq->nb_tx_desc; i++) {
1738 txq->tx_ring[i] = zeroed_desc;
1741 /* Initialize SW ring entries */
1742 prev = (uint16_t) (txq->nb_tx_desc - 1);
1743 for (i = 0; i < txq->nb_tx_desc; i++) {
1744 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
1745 txd->wb.status = IXGBE_TXD_STAT_DD;
1748 txe[prev].next_id = i;
1752 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1753 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1756 txq->nb_tx_used = 0;
1758 * Always allow 1 descriptor to be un-allocated to avoid
1759 * a H/W race condition
1761 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
1762 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
1764 memset((void*)&txq->ctx_cache, 0,
1765 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
1768 static const struct ixgbe_txq_ops def_txq_ops = {
1769 .release_mbufs = ixgbe_tx_queue_release_mbufs,
1770 .free_swring = ixgbe_tx_free_swring,
1771 .reset = ixgbe_reset_tx_queue,
1774 /* Takes an ethdev and a queue and sets up the tx function to be used based on
1775 * the queue parameters. Used in tx_queue_setup by primary process and then
1776 * in dev_init by secondary process when attaching to an existing ethdev.
1779 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
1781 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
1782 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
1783 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
1784 PMD_INIT_LOG(INFO, "Using simple tx code path");
1785 #ifdef RTE_IXGBE_INC_VECTOR
1786 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
1787 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
1788 ixgbe_txq_vec_setup(txq) == 0)) {
1789 PMD_INIT_LOG(INFO, "Vector tx enabled.");
1790 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
1793 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
1795 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
1797 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
1798 (unsigned long)txq->txq_flags,
1799 (unsigned long)IXGBE_SIMPLE_FLAGS);
1801 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
1802 (unsigned long)txq->tx_rs_thresh,
1803 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
1804 dev->tx_pkt_burst = ixgbe_xmit_pkts;
1809 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
1812 unsigned int socket_id,
1813 const struct rte_eth_txconf *tx_conf)
1815 const struct rte_memzone *tz;
1816 struct ixgbe_tx_queue *txq;
1817 struct ixgbe_hw *hw;
1818 uint16_t tx_rs_thresh, tx_free_thresh;
1820 PMD_INIT_FUNC_TRACE();
1821 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1824 * Validate number of transmit descriptors.
1825 * It must not exceed hardware maximum, and must be multiple
1828 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
1829 (nb_desc > IXGBE_MAX_RING_DESC) ||
1830 (nb_desc < IXGBE_MIN_RING_DESC)) {
1835 * The following two parameters control the setting of the RS bit on
1836 * transmit descriptors.
1837 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
1838 * descriptors have been used.
1839 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
1840 * descriptors are used or if the number of descriptors required
1841 * to transmit a packet is greater than the number of free TX
1843 * The following constraints must be satisfied:
1844 * tx_rs_thresh must be greater than 0.
1845 * tx_rs_thresh must be less than the size of the ring minus 2.
1846 * tx_rs_thresh must be less than or equal to tx_free_thresh.
1847 * tx_rs_thresh must be a divisor of the ring size.
1848 * tx_free_thresh must be greater than 0.
1849 * tx_free_thresh must be less than the size of the ring minus 3.
1850 * One descriptor in the TX ring is used as a sentinel to avoid a
1851 * H/W race condition, hence the maximum threshold constraints.
1852 * When set to zero use default values.
1854 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1855 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1856 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1857 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1858 if (tx_rs_thresh >= (nb_desc - 2)) {
1859 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
1860 "of TX descriptors minus 2. (tx_rs_thresh=%u "
1861 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1862 (int)dev->data->port_id, (int)queue_idx);
1865 if (tx_free_thresh >= (nb_desc - 3)) {
1866 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1867 "tx_free_thresh must be less than the number of "
1868 "TX descriptors minus 3. (tx_free_thresh=%u "
1869 "port=%d queue=%d)",
1870 (unsigned int)tx_free_thresh,
1871 (int)dev->data->port_id, (int)queue_idx);
1874 if (tx_rs_thresh > tx_free_thresh) {
1875 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
1876 "tx_free_thresh. (tx_free_thresh=%u "
1877 "tx_rs_thresh=%u port=%d queue=%d)",
1878 (unsigned int)tx_free_thresh,
1879 (unsigned int)tx_rs_thresh,
1880 (int)dev->data->port_id,
1884 if ((nb_desc % tx_rs_thresh) != 0) {
1885 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1886 "number of TX descriptors. (tx_rs_thresh=%u "
1887 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1888 (int)dev->data->port_id, (int)queue_idx);
1893 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
1894 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
1895 * by the NIC and all descriptors are written back after the NIC
1896 * accumulates WTHRESH descriptors.
1898 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1899 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1900 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
1901 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
1902 (int)dev->data->port_id, (int)queue_idx);
1906 /* Free memory prior to re-allocation if needed... */
1907 if (dev->data->tx_queues[queue_idx] != NULL) {
1908 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
1909 dev->data->tx_queues[queue_idx] = NULL;
1912 /* First allocate the tx queue data structure */
1913 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
1914 RTE_CACHE_LINE_SIZE, socket_id);
1919 * Allocate TX ring hardware descriptors. A memzone large enough to
1920 * handle the maximum ring size is allocated in order to allow for
1921 * resizing in later calls to the queue setup function.
1923 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
1924 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
1927 ixgbe_tx_queue_release(txq);
1931 txq->nb_tx_desc = nb_desc;
1932 txq->tx_rs_thresh = tx_rs_thresh;
1933 txq->tx_free_thresh = tx_free_thresh;
1934 txq->pthresh = tx_conf->tx_thresh.pthresh;
1935 txq->hthresh = tx_conf->tx_thresh.hthresh;
1936 txq->wthresh = tx_conf->tx_thresh.wthresh;
1937 txq->queue_id = queue_idx;
1938 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
1939 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
1940 txq->port_id = dev->data->port_id;
1941 txq->txq_flags = tx_conf->txq_flags;
1942 txq->ops = &def_txq_ops;
1943 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1946 * Modification to set VFTDT for virtual function if vf is detected
1948 if (hw->mac.type == ixgbe_mac_82599_vf ||
1949 hw->mac.type == ixgbe_mac_X540_vf ||
1950 hw->mac.type == ixgbe_mac_X550_vf ||
1951 hw->mac.type == ixgbe_mac_X550EM_x_vf)
1952 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
1954 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
1955 #ifndef RTE_LIBRTE_XEN_DOM0
1956 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
1958 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1960 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
1962 /* Allocate software ring */
1963 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
1964 sizeof(struct ixgbe_tx_entry) * nb_desc,
1965 RTE_CACHE_LINE_SIZE, socket_id);
1966 if (txq->sw_ring == NULL) {
1967 ixgbe_tx_queue_release(txq);
1970 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
1971 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
1973 /* set up vector or scalar TX function as appropriate */
1974 ixgbe_set_tx_function(dev, txq);
1976 txq->ops->reset(txq);
1978 dev->data->tx_queues[queue_idx] = txq;
1985 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
1989 if (rxq->sw_ring != NULL) {
1990 for (i = 0; i < rxq->nb_rx_desc; i++) {
1991 if (rxq->sw_ring[i].mbuf != NULL) {
1992 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1993 rxq->sw_ring[i].mbuf = NULL;
1996 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1997 if (rxq->rx_nb_avail) {
1998 for (i = 0; i < rxq->rx_nb_avail; ++i) {
1999 struct rte_mbuf *mb;
2000 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2001 rte_pktmbuf_free_seg(mb);
2003 rxq->rx_nb_avail = 0;
2010 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2013 ixgbe_rx_queue_release_mbufs(rxq);
2014 rte_free(rxq->sw_ring);
2020 ixgbe_dev_rx_queue_release(void *rxq)
2022 ixgbe_rx_queue_release(rxq);
2026 * Check if Rx Burst Bulk Alloc function can be used.
2028 * 0: the preconditions are satisfied and the bulk allocation function
2030 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2031 * function must be used.
2034 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2035 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2037 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2043 * Make sure the following pre-conditions are satisfied:
2044 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2045 * rxq->rx_free_thresh < rxq->nb_rx_desc
2046 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2047 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2048 * Scattered packets are not supported. This should be checked
2049 * outside of this function.
2051 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2052 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2053 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2054 "rxq->rx_free_thresh=%d, "
2055 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2056 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2058 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2059 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2060 "rxq->rx_free_thresh=%d, "
2061 "rxq->nb_rx_desc=%d",
2062 rxq->rx_free_thresh, rxq->nb_rx_desc);
2064 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2065 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2066 "rxq->nb_rx_desc=%d, "
2067 "rxq->rx_free_thresh=%d",
2068 rxq->nb_rx_desc, rxq->rx_free_thresh);
2070 } else if (!(rxq->nb_rx_desc <
2071 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2072 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2073 "rxq->nb_rx_desc=%d, "
2074 "IXGBE_MAX_RING_DESC=%d, "
2075 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2076 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2077 RTE_PMD_IXGBE_RX_MAX_BURST);
2087 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2089 ixgbe_reset_rx_queue(struct ixgbe_hw *hw, struct ixgbe_rx_queue *rxq)
2091 static const union ixgbe_adv_rx_desc zeroed_desc = { .read = {
2094 uint16_t len = rxq->nb_rx_desc;
2097 * By default, the Rx queue setup function allocates enough memory for
2098 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2099 * extra memory at the end of the descriptor ring to be zero'd out. A
2100 * pre-condition for using the Rx burst bulk alloc function is that the
2101 * number of descriptors is less than or equal to
2102 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2103 * constraints here to see if we need to zero out memory after the end
2104 * of the H/W descriptor ring.
2106 if (hw->rx_bulk_alloc_allowed)
2107 /* zero out extra memory */
2108 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2111 * Zero out HW ring memory. Zero out extra memory at the end of
2112 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2113 * reads extra memory as zeros.
2115 for (i = 0; i < len; i++) {
2116 rxq->rx_ring[i] = zeroed_desc;
2119 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2121 * initialize extra software ring entries. Space for these extra
2122 * entries is always allocated
2124 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2125 for (i = rxq->nb_rx_desc; i < len; ++i) {
2126 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2129 rxq->rx_nb_avail = 0;
2130 rxq->rx_next_avail = 0;
2131 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2132 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2134 rxq->nb_rx_hold = 0;
2135 rxq->pkt_first_seg = NULL;
2136 rxq->pkt_last_seg = NULL;
2140 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2143 unsigned int socket_id,
2144 const struct rte_eth_rxconf *rx_conf,
2145 struct rte_mempool *mp)
2147 const struct rte_memzone *rz;
2148 struct ixgbe_rx_queue *rxq;
2149 struct ixgbe_hw *hw;
2152 PMD_INIT_FUNC_TRACE();
2153 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156 * Validate number of receive descriptors.
2157 * It must not exceed hardware maximum, and must be multiple
2160 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2161 (nb_desc > IXGBE_MAX_RING_DESC) ||
2162 (nb_desc < IXGBE_MIN_RING_DESC)) {
2166 /* Free memory prior to re-allocation if needed... */
2167 if (dev->data->rx_queues[queue_idx] != NULL) {
2168 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2169 dev->data->rx_queues[queue_idx] = NULL;
2172 /* First allocate the rx queue data structure */
2173 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2174 RTE_CACHE_LINE_SIZE, socket_id);
2178 rxq->nb_rx_desc = nb_desc;
2179 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2180 rxq->queue_id = queue_idx;
2181 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2182 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2183 rxq->port_id = dev->data->port_id;
2184 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2186 rxq->drop_en = rx_conf->rx_drop_en;
2187 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2190 * Allocate RX ring hardware descriptors. A memzone large enough to
2191 * handle the maximum ring size is allocated in order to allow for
2192 * resizing in later calls to the queue setup function.
2194 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2195 RX_RING_SZ, socket_id);
2197 ixgbe_rx_queue_release(rxq);
2202 * Zero init all the descriptors in the ring.
2204 memset (rz->addr, 0, RX_RING_SZ);
2207 * Modified to setup VFRDT for Virtual Function
2209 if (hw->mac.type == ixgbe_mac_82599_vf ||
2210 hw->mac.type == ixgbe_mac_X540_vf ||
2211 hw->mac.type == ixgbe_mac_X550_vf ||
2212 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2214 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2216 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2220 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2222 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2224 #ifndef RTE_LIBRTE_XEN_DOM0
2225 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2227 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2229 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2232 * Certain constraints must be met in order to use the bulk buffer
2233 * allocation Rx burst function. If any of Rx queues doesn't meet them
2234 * the feature should be disabled for the whole port.
2236 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2237 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2238 "preconditions - canceling the feature for "
2239 "the whole port[%d]",
2240 rxq->queue_id, rxq->port_id);
2241 hw->rx_bulk_alloc_allowed = false;
2245 * Allocate software ring. Allow for space at the end of the
2246 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2247 * function does not access an invalid memory region.
2250 if (hw->rx_bulk_alloc_allowed)
2251 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2253 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2254 sizeof(struct ixgbe_rx_entry) * len,
2255 RTE_CACHE_LINE_SIZE, socket_id);
2256 if (rxq->sw_ring == NULL) {
2257 ixgbe_rx_queue_release(rxq);
2260 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2261 rxq->sw_ring, rxq->rx_ring, rxq->rx_ring_phys_addr);
2263 if (!rte_is_power_of_2(nb_desc)) {
2264 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2265 "preconditions - canceling the feature for "
2266 "the whole port[%d]",
2267 rxq->queue_id, rxq->port_id);
2268 hw->rx_vec_allowed = false;
2270 ixgbe_rxq_vec_setup(rxq);
2272 dev->data->rx_queues[queue_idx] = rxq;
2274 ixgbe_reset_rx_queue(hw, rxq);
2280 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2282 #define IXGBE_RXQ_SCAN_INTERVAL 4
2283 volatile union ixgbe_adv_rx_desc *rxdp;
2284 struct ixgbe_rx_queue *rxq;
2287 if (rx_queue_id >= dev->data->nb_rx_queues) {
2288 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2292 rxq = dev->data->rx_queues[rx_queue_id];
2293 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2295 while ((desc < rxq->nb_rx_desc) &&
2296 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2297 desc += IXGBE_RXQ_SCAN_INTERVAL;
2298 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2299 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2300 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2301 desc - rxq->nb_rx_desc]);
2308 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2310 volatile union ixgbe_adv_rx_desc *rxdp;
2311 struct ixgbe_rx_queue *rxq = rx_queue;
2314 if (unlikely(offset >= rxq->nb_rx_desc))
2316 desc = rxq->rx_tail + offset;
2317 if (desc >= rxq->nb_rx_desc)
2318 desc -= rxq->nb_rx_desc;
2320 rxdp = &rxq->rx_ring[desc];
2321 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2325 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2328 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330 PMD_INIT_FUNC_TRACE();
2332 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2333 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2335 txq->ops->release_mbufs(txq);
2336 txq->ops->reset(txq);
2340 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2341 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2343 ixgbe_rx_queue_release_mbufs(rxq);
2344 ixgbe_reset_rx_queue(hw, rxq);
2349 /*********************************************************************
2351 * Device RX/TX init functions
2353 **********************************************************************/
2356 * Receive Side Scaling (RSS)
2357 * See section 7.1.2.8 in the following document:
2358 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2361 * The source and destination IP addresses of the IP header and the source
2362 * and destination ports of TCP/UDP headers, if any, of received packets are
2363 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2364 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2365 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2366 * RSS output index which is used as the RX queue index where to store the
2368 * The following output is supplied in the RX write-back descriptor:
2369 * - 32-bit result of the Microsoft RSS hash function,
2370 * - 4-bit RSS type field.
2374 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2375 * Used as the default key.
2377 static uint8_t rss_intel_key[40] = {
2378 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2379 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2380 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2381 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2382 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2386 ixgbe_rss_disable(struct rte_eth_dev *dev)
2388 struct ixgbe_hw *hw;
2391 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2393 mrqc &= ~IXGBE_MRQC_RSSEN;
2394 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2398 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2406 hash_key = rss_conf->rss_key;
2407 if (hash_key != NULL) {
2408 /* Fill in RSS hash key */
2409 for (i = 0; i < 10; i++) {
2410 rss_key = hash_key[(i * 4)];
2411 rss_key |= hash_key[(i * 4) + 1] << 8;
2412 rss_key |= hash_key[(i * 4) + 2] << 16;
2413 rss_key |= hash_key[(i * 4) + 3] << 24;
2414 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2418 /* Set configured hashing protocols in MRQC register */
2419 rss_hf = rss_conf->rss_hf;
2420 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2421 if (rss_hf & ETH_RSS_IPV4)
2422 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2423 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2424 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2425 if (rss_hf & ETH_RSS_IPV6)
2426 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2427 if (rss_hf & ETH_RSS_IPV6_EX)
2428 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2429 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2430 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2431 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2432 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2433 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2434 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2435 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2436 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2437 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2438 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2439 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2443 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2444 struct rte_eth_rss_conf *rss_conf)
2446 struct ixgbe_hw *hw;
2450 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2453 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2454 * "RSS enabling cannot be done dynamically while it must be
2455 * preceded by a software reset"
2456 * Before changing anything, first check that the update RSS operation
2457 * does not attempt to disable RSS, if RSS was enabled at
2458 * initialization time, or does not attempt to enable RSS, if RSS was
2459 * disabled at initialization time.
2461 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2462 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2463 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2464 if (rss_hf != 0) /* Enable RSS */
2466 return 0; /* Nothing to do */
2469 if (rss_hf == 0) /* Disable RSS */
2471 ixgbe_hw_rss_hash_set(hw, rss_conf);
2476 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2477 struct rte_eth_rss_conf *rss_conf)
2479 struct ixgbe_hw *hw;
2486 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487 hash_key = rss_conf->rss_key;
2488 if (hash_key != NULL) {
2489 /* Return RSS hash key */
2490 for (i = 0; i < 10; i++) {
2491 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2492 hash_key[(i * 4)] = rss_key & 0x000000FF;
2493 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2494 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2495 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2499 /* Get RSS functions configured in MRQC register */
2500 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2501 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2502 rss_conf->rss_hf = 0;
2506 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2507 rss_hf |= ETH_RSS_IPV4;
2508 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2509 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2510 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2511 rss_hf |= ETH_RSS_IPV6;
2512 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2513 rss_hf |= ETH_RSS_IPV6_EX;
2514 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2515 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2516 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2517 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2518 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2519 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2520 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2521 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2522 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2523 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2524 rss_conf->rss_hf = rss_hf;
2529 ixgbe_rss_configure(struct rte_eth_dev *dev)
2531 struct rte_eth_rss_conf rss_conf;
2532 struct ixgbe_hw *hw;
2537 PMD_INIT_FUNC_TRACE();
2538 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 * Fill in redirection table
2542 * The byte-swap is needed because NIC registers are in
2543 * little-endian order.
2546 for (i = 0, j = 0; i < 128; i++, j++) {
2547 if (j == dev->data->nb_rx_queues)
2549 reta = (reta << 8) | j;
2551 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2556 * Configure the RSS key and the RSS protocols used to compute
2557 * the RSS hash of input packets.
2559 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2560 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2561 ixgbe_rss_disable(dev);
2564 if (rss_conf.rss_key == NULL)
2565 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2566 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2569 #define NUM_VFTA_REGISTERS 128
2570 #define NIC_RX_BUFFER_SIZE 0x200
2573 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2575 struct rte_eth_vmdq_dcb_conf *cfg;
2576 struct ixgbe_hw *hw;
2577 enum rte_eth_nb_pools num_pools;
2578 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2580 uint8_t nb_tcs; /* number of traffic classes */
2583 PMD_INIT_FUNC_TRACE();
2584 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2586 num_pools = cfg->nb_queue_pools;
2587 /* Check we have a valid number of pools */
2588 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2589 ixgbe_rss_disable(dev);
2592 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2593 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2597 * split rx buffer up into sections, each for 1 traffic class
2599 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2600 for (i = 0 ; i < nb_tcs; i++) {
2601 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2602 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2603 /* clear 10 bits. */
2604 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2605 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2607 /* zero alloc all unused TCs */
2608 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2609 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2610 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2611 /* clear 10 bits. */
2612 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2615 /* MRQC: enable vmdq and dcb */
2616 mrqc = ((num_pools == ETH_16_POOLS) ? \
2617 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2618 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2620 /* PFVTCTL: turn on virtualisation and set the default pool */
2621 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2622 if (cfg->enable_default_pool) {
2623 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2625 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2628 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2630 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2632 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2634 * mapping is done with 3 bits per priority,
2635 * so shift by i*3 each time
2637 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2639 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2641 /* RTRPCS: DCB related */
2642 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2644 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2645 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2646 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2647 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2649 /* VFTA - enable all vlan filters */
2650 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2651 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2654 /* VFRE: pool enabling for receive - 16 or 32 */
2655 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2656 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2659 * MPSAR - allow pools to read specific mac addresses
2660 * In this case, all pools should be able to read from mac addr 0
2662 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
2663 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
2665 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
2666 for (i = 0; i < cfg->nb_pool_maps; i++) {
2667 /* set vlan id in VF register and set the valid bit */
2668 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
2669 (cfg->pool_map[i].vlan_id & 0xFFF)));
2671 * Put the allowed pools in VFB reg. As we only have 16 or 32
2672 * pools, we only need to use the first half of the register
2675 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
2680 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
2681 * @hw: pointer to hardware structure
2682 * @dcb_config: pointer to ixgbe_dcb_config structure
2685 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
2686 struct ixgbe_dcb_config *dcb_config)
2691 PMD_INIT_FUNC_TRACE();
2692 if (hw->mac.type != ixgbe_mac_82598EB) {
2693 /* Disable the Tx desc arbiter so that MTQC can be changed */
2694 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2695 reg |= IXGBE_RTTDCS_ARBDIS;
2696 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2698 /* Enable DCB for Tx with 8 TCs */
2699 if (dcb_config->num_tcs.pg_tcs == 8) {
2700 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2703 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2705 if (dcb_config->vt_mode)
2706 reg |= IXGBE_MTQC_VT_ENA;
2707 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2709 /* Disable drop for all queues */
2710 for (q = 0; q < 128; q++)
2711 IXGBE_WRITE_REG(hw, IXGBE_QDE,
2712 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
2714 /* Enable the Tx desc arbiter */
2715 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2716 reg &= ~IXGBE_RTTDCS_ARBDIS;
2717 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
2719 /* Enable Security TX Buffer IFG for DCB */
2720 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2721 reg |= IXGBE_SECTX_DCB;
2722 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2728 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
2729 * @dev: pointer to rte_eth_dev structure
2730 * @dcb_config: pointer to ixgbe_dcb_config structure
2733 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
2734 struct ixgbe_dcb_config *dcb_config)
2736 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2737 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2738 struct ixgbe_hw *hw =
2739 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2741 PMD_INIT_FUNC_TRACE();
2742 if (hw->mac.type != ixgbe_mac_82598EB)
2743 /*PF VF Transmit Enable*/
2744 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
2745 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
2747 /*Configure general DCB TX parameters*/
2748 ixgbe_dcb_tx_hw_config(hw,dcb_config);
2753 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
2754 struct ixgbe_dcb_config *dcb_config)
2756 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
2757 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2758 struct ixgbe_dcb_tc_config *tc;
2761 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2762 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
2763 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2764 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2767 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2768 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2770 /* User Priority to Traffic Class mapping */
2771 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2772 j = vmdq_rx_conf->dcb_queue[i];
2773 tc = &dcb_config->tc_config[j];
2774 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2780 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
2781 struct ixgbe_dcb_config *dcb_config)
2783 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
2784 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
2785 struct ixgbe_dcb_tc_config *tc;
2788 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
2789 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
2790 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
2791 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
2794 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
2795 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
2798 /* User Priority to Traffic Class mapping */
2799 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2800 j = vmdq_tx_conf->dcb_queue[i];
2801 tc = &dcb_config->tc_config[j];
2802 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2809 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
2810 struct ixgbe_dcb_config *dcb_config)
2812 struct rte_eth_dcb_rx_conf *rx_conf =
2813 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
2814 struct ixgbe_dcb_tc_config *tc;
2817 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
2818 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
2820 /* User Priority to Traffic Class mapping */
2821 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2822 j = rx_conf->dcb_queue[i];
2823 tc = &dcb_config->tc_config[j];
2824 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
2830 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
2831 struct ixgbe_dcb_config *dcb_config)
2833 struct rte_eth_dcb_tx_conf *tx_conf =
2834 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
2835 struct ixgbe_dcb_tc_config *tc;
2838 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
2839 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
2841 /* User Priority to Traffic Class mapping */
2842 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2843 j = tx_conf->dcb_queue[i];
2844 tc = &dcb_config->tc_config[j];
2845 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
2851 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
2852 * @hw: pointer to hardware structure
2853 * @dcb_config: pointer to ixgbe_dcb_config structure
2856 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
2857 struct ixgbe_dcb_config *dcb_config)
2863 PMD_INIT_FUNC_TRACE();
2865 * Disable the arbiter before changing parameters
2866 * (always enable recycle mode; WSP)
2868 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
2869 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2871 if (hw->mac.type != ixgbe_mac_82598EB) {
2872 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
2873 if (dcb_config->num_tcs.pg_tcs == 4) {
2874 if (dcb_config->vt_mode)
2875 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2876 IXGBE_MRQC_VMDQRT4TCEN;
2878 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2879 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2883 if (dcb_config->num_tcs.pg_tcs == 8) {
2884 if (dcb_config->vt_mode)
2885 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2886 IXGBE_MRQC_VMDQRT8TCEN;
2888 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
2889 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
2894 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
2897 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2898 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2899 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2900 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2902 /* VFTA - enable all vlan filters */
2903 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2904 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2908 * Configure Rx packet plane (recycle mode; WSP) and
2911 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
2912 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
2918 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
2919 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2921 switch (hw->mac.type) {
2922 case ixgbe_mac_82598EB:
2923 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
2925 case ixgbe_mac_82599EB:
2926 case ixgbe_mac_X540:
2927 case ixgbe_mac_X550:
2928 case ixgbe_mac_X550EM_x:
2929 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
2938 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
2939 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
2941 switch (hw->mac.type) {
2942 case ixgbe_mac_82598EB:
2943 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
2944 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
2946 case ixgbe_mac_82599EB:
2947 case ixgbe_mac_X540:
2948 case ixgbe_mac_X550:
2949 case ixgbe_mac_X550EM_x:
2950 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
2951 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
2958 #define DCB_RX_CONFIG 1
2959 #define DCB_TX_CONFIG 1
2960 #define DCB_TX_PB 1024
2962 * ixgbe_dcb_hw_configure - Enable DCB and configure
2963 * general DCB in VT mode and non-VT mode parameters
2964 * @dev: pointer to rte_eth_dev structure
2965 * @dcb_config: pointer to ixgbe_dcb_config structure
2968 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
2969 struct ixgbe_dcb_config *dcb_config)
2972 uint8_t i,pfc_en,nb_tcs;
2974 uint8_t config_dcb_rx = 0;
2975 uint8_t config_dcb_tx = 0;
2976 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2977 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2978 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2979 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2980 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
2981 struct ixgbe_dcb_tc_config *tc;
2982 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2983 struct ixgbe_hw *hw =
2984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2986 switch(dev->data->dev_conf.rxmode.mq_mode){
2987 case ETH_MQ_RX_VMDQ_DCB:
2988 dcb_config->vt_mode = true;
2989 if (hw->mac.type != ixgbe_mac_82598EB) {
2990 config_dcb_rx = DCB_RX_CONFIG;
2992 *get dcb and VT rx configuration parameters
2995 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
2996 /*Configure general VMDQ and DCB RX parameters*/
2997 ixgbe_vmdq_dcb_configure(dev);
3001 dcb_config->vt_mode = false;
3002 config_dcb_rx = DCB_RX_CONFIG;
3003 /* Get dcb TX configuration parameters from rte_eth_conf */
3004 ixgbe_dcb_rx_config(dev,dcb_config);
3005 /*Configure general DCB RX parameters*/
3006 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3009 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3012 switch (dev->data->dev_conf.txmode.mq_mode) {
3013 case ETH_MQ_TX_VMDQ_DCB:
3014 dcb_config->vt_mode = true;
3015 config_dcb_tx = DCB_TX_CONFIG;
3016 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3017 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3018 /*Configure general VMDQ and DCB TX parameters*/
3019 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3023 dcb_config->vt_mode = false;
3024 config_dcb_tx = DCB_TX_CONFIG;
3025 /*get DCB TX configuration parameters from rte_eth_conf*/
3026 ixgbe_dcb_tx_config(dev,dcb_config);
3027 /*Configure general DCB TX parameters*/
3028 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3031 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3035 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3037 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3038 if(nb_tcs == ETH_4_TCS) {
3039 /* Avoid un-configured priority mapping to TC0 */
3041 uint8_t mask = 0xFF;
3042 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3043 mask = (uint8_t)(mask & (~ (1 << map[i])));
3044 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3045 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3049 /* Re-configure 4 TCs BW */
3050 for (i = 0; i < nb_tcs; i++) {
3051 tc = &dcb_config->tc_config[i];
3052 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3053 (uint8_t)(100 / nb_tcs);
3054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3055 (uint8_t)(100 / nb_tcs);
3057 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3058 tc = &dcb_config->tc_config[i];
3059 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3060 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3065 /* Set RX buffer size */
3066 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3067 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3068 for (i = 0 ; i < nb_tcs; i++) {
3069 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3071 /* zero alloc all unused TCs */
3072 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3073 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3077 /* Only support an equally distributed Tx packet buffer strategy. */
3078 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3079 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3080 for (i = 0; i < nb_tcs; i++) {
3081 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3082 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3084 /* Clear unused TCs, if any, to zero buffer size*/
3085 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3086 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3087 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3091 /*Calculates traffic class credits*/
3092 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3093 IXGBE_DCB_TX_CONFIG);
3094 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3095 IXGBE_DCB_RX_CONFIG);
3098 /* Unpack CEE standard containers */
3099 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3100 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3101 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3102 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3103 /* Configure PG(ETS) RX */
3104 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3108 /* Unpack CEE standard containers */
3109 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3110 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3111 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3112 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3113 /* Configure PG(ETS) TX */
3114 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3117 /*Configure queue statistics registers*/
3118 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3120 /* Check if the PFC is supported */
3121 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3122 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3123 for (i = 0; i < nb_tcs; i++) {
3125 * If the TC count is 8,and the default high_water is 48,
3126 * the low_water is 16 as default.
3128 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3129 hw->fc.low_water[i] = pbsize / 4;
3130 /* Enable pfc for this TC */
3131 tc = &dcb_config->tc_config[i];
3132 tc->pfc = ixgbe_dcb_pfc_enabled;
3134 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3135 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3137 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3144 * ixgbe_configure_dcb - Configure DCB Hardware
3145 * @dev: pointer to rte_eth_dev
3147 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3149 struct ixgbe_dcb_config *dcb_cfg =
3150 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3151 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3153 PMD_INIT_FUNC_TRACE();
3155 /* check support mq_mode for DCB */
3156 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3157 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3160 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3163 /** Configure DCB hardware **/
3164 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3170 * VMDq only support for 10 GbE NIC.
3173 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3175 struct rte_eth_vmdq_rx_conf *cfg;
3176 struct ixgbe_hw *hw;
3177 enum rte_eth_nb_pools num_pools;
3178 uint32_t mrqc, vt_ctl, vlanctrl;
3182 PMD_INIT_FUNC_TRACE();
3183 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3184 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3185 num_pools = cfg->nb_queue_pools;
3187 ixgbe_rss_disable(dev);
3189 /* MRQC: enable vmdq */
3190 mrqc = IXGBE_MRQC_VMDQEN;
3191 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3193 /* PFVTCTL: turn on virtualisation and set the default pool */
3194 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3195 if (cfg->enable_default_pool)
3196 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3198 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3200 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3202 for (i = 0; i < (int)num_pools; i++) {
3203 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3204 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3207 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3208 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3209 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3210 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3212 /* VFTA - enable all vlan filters */
3213 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3214 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3216 /* VFRE: pool enabling for receive - 64 */
3217 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3218 if (num_pools == ETH_64_POOLS)
3219 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3222 * MPSAR - allow pools to read specific mac addresses
3223 * In this case, all pools should be able to read from mac addr 0
3225 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3226 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3228 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3229 for (i = 0; i < cfg->nb_pool_maps; i++) {
3230 /* set vlan id in VF register and set the valid bit */
3231 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3232 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3234 * Put the allowed pools in VFB reg. As we only have 16 or 64
3235 * pools, we only need to use the first half of the register
3238 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3239 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3240 (cfg->pool_map[i].pools & UINT32_MAX));
3242 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3243 ((cfg->pool_map[i].pools >> 32) \
3248 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3249 if (cfg->enable_loop_back) {
3250 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3251 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3252 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3255 IXGBE_WRITE_FLUSH(hw);
3259 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3260 * @hw: pointer to hardware structure
3263 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3268 PMD_INIT_FUNC_TRACE();
3269 /*PF VF Transmit Enable*/
3270 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3271 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3273 /* Disable the Tx desc arbiter so that MTQC can be changed */
3274 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3275 reg |= IXGBE_RTTDCS_ARBDIS;
3276 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3278 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3279 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3281 /* Disable drop for all queues */
3282 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3283 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3284 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3286 /* Enable the Tx desc arbiter */
3287 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3288 reg &= ~IXGBE_RTTDCS_ARBDIS;
3289 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3291 IXGBE_WRITE_FLUSH(hw);
3297 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3299 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3303 /* Initialize software ring entries */
3304 for (i = 0; i < rxq->nb_rx_desc; i++) {
3305 volatile union ixgbe_adv_rx_desc *rxd;
3306 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3308 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3309 (unsigned) rxq->queue_id);
3313 rte_mbuf_refcnt_set(mbuf, 1);
3315 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3317 mbuf->port = rxq->port_id;
3320 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3321 rxd = &rxq->rx_ring[i];
3322 rxd->read.hdr_addr = dma_addr;
3323 rxd->read.pkt_addr = dma_addr;
3331 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3333 struct ixgbe_hw *hw;
3336 ixgbe_rss_configure(dev);
3338 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340 /* MRQC: enable VF RSS */
3341 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3342 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3343 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3345 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3349 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3353 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3357 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3363 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3365 struct ixgbe_hw *hw =
3366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3370 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3375 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3376 IXGBE_MRQC_VMDQRT4TCEN);
3380 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3381 IXGBE_MRQC_VMDQRT8TCEN);
3385 "invalid pool number in IOV mode");
3392 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3394 struct ixgbe_hw *hw =
3395 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397 if (hw->mac.type == ixgbe_mac_82598EB)
3400 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3402 * SRIOV inactive scheme
3403 * any DCB/RSS w/o VMDq multi-queue setting
3405 switch (dev->data->dev_conf.rxmode.mq_mode) {
3407 ixgbe_rss_configure(dev);
3410 case ETH_MQ_RX_VMDQ_DCB:
3411 ixgbe_vmdq_dcb_configure(dev);
3414 case ETH_MQ_RX_VMDQ_ONLY:
3415 ixgbe_vmdq_rx_hw_configure(dev);
3418 case ETH_MQ_RX_NONE:
3419 /* if mq_mode is none, disable rss mode.*/
3420 default: ixgbe_rss_disable(dev);
3424 * SRIOV active scheme
3425 * Support RSS together with VMDq & SRIOV
3427 switch (dev->data->dev_conf.rxmode.mq_mode) {
3429 case ETH_MQ_RX_VMDQ_RSS:
3430 ixgbe_config_vf_rss(dev);
3433 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3434 case ETH_MQ_RX_VMDQ_DCB:
3435 case ETH_MQ_RX_VMDQ_DCB_RSS:
3437 "Could not support DCB with VMDq & SRIOV");
3440 ixgbe_config_vf_default(dev);
3449 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3451 struct ixgbe_hw *hw =
3452 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3456 if (hw->mac.type == ixgbe_mac_82598EB)
3459 /* disable arbiter before setting MTQC */
3460 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3461 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3462 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3464 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3466 * SRIOV inactive scheme
3467 * any DCB w/o VMDq multi-queue setting
3469 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3470 ixgbe_vmdq_tx_hw_configure(hw);
3472 mtqc = IXGBE_MTQC_64Q_1PB;
3473 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3476 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3479 * SRIOV active scheme
3480 * FIXME if support DCB together with VMDq & SRIOV
3483 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3486 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3489 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3493 mtqc = IXGBE_MTQC_64Q_1PB;
3494 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3496 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3499 /* re-enable arbiter */
3500 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3501 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3506 void ixgbe_set_rx_function(struct rte_eth_dev *dev)
3508 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3511 * In order to allow Vector Rx there are a few configuration
3512 * conditions to be met and Rx Bulk Allocation should be allowed.
3514 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3515 !hw->rx_bulk_alloc_allowed) {
3516 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3517 "preconditions or RTE_IXGBE_INC_VECTOR is "
3519 dev->data->port_id);
3521 hw->rx_vec_allowed = false;
3524 if (dev->data->scattered_rx) {
3526 * Set the non-LRO scattered callback: there are Vector and
3527 * single allocation versions.
3529 if (hw->rx_vec_allowed) {
3530 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3531 "callback (port=%d).",
3532 dev->data->port_id);
3534 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3536 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector) "
3537 "Scattered Rx callback "
3539 dev->data->port_id);
3541 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
3544 * Below we set "simple" callbacks according to port/queues parameters.
3545 * If parameters allow we are going to choose between the following
3549 * - Single buffer allocation (the simplest one)
3551 } else if (hw->rx_vec_allowed) {
3552 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
3553 "burst size no less than 32.");
3555 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
3556 } else if (hw->rx_bulk_alloc_allowed) {
3557 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3558 "satisfied. Rx Burst Bulk Alloc function "
3559 "will be used on port=%d.",
3560 dev->data->port_id);
3562 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
3564 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3565 "satisfied, or Scattered Rx is requested, "
3566 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
3567 "is not enabled (port=%d).",
3568 dev->data->port_id);
3570 dev->rx_pkt_burst = ixgbe_recv_pkts;
3575 * Initializes Receive Unit.
3578 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
3580 struct ixgbe_hw *hw;
3581 struct ixgbe_rx_queue *rxq;
3582 struct rte_pktmbuf_pool_private *mbp_priv;
3594 PMD_INIT_FUNC_TRACE();
3595 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3598 * Make sure receives are disabled while setting
3599 * up the RX context (registers, descriptor rings, etc.).
3601 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3602 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3604 /* Enable receipt of broadcasted frames */
3605 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3606 fctrl |= IXGBE_FCTRL_BAM;
3607 fctrl |= IXGBE_FCTRL_DPF;
3608 fctrl |= IXGBE_FCTRL_PMCF;
3609 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3612 * Configure CRC stripping, if any.
3614 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3615 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3616 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
3618 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
3621 * Configure jumbo frame support, if any.
3623 if (dev->data->dev_conf.rxmode.jumbo_frame == 1) {
3624 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3625 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3626 maxfrs &= 0x0000FFFF;
3627 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3628 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3630 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3633 * If loopback mode is configured for 82599, set LPBK bit.
3635 if (hw->mac.type == ixgbe_mac_82599EB &&
3636 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3637 hlreg0 |= IXGBE_HLREG0_LPBK;
3639 hlreg0 &= ~IXGBE_HLREG0_LPBK;
3641 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3643 /* Setup RX queues */
3644 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3645 rxq = dev->data->rx_queues[i];
3648 * Reset crc_len in case it was changed after queue setup by a
3649 * call to configure.
3651 rxq->crc_len = (uint8_t)
3652 ((dev->data->dev_conf.rxmode.hw_strip_crc) ? 0 :
3655 /* Setup the Base and Length of the Rx Descriptor Rings */
3656 bus_addr = rxq->rx_ring_phys_addr;
3657 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
3658 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3659 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
3660 (uint32_t)(bus_addr >> 32));
3661 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
3662 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
3663 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3664 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
3666 /* Configure the SRRCTL register */
3667 #ifdef RTE_HEADER_SPLIT_ENABLE
3669 * Configure Header Split
3671 if (dev->data->dev_conf.rxmode.header_split) {
3672 if (hw->mac.type == ixgbe_mac_82599EB) {
3673 /* Must setup the PSRTYPE register */
3675 psrtype = IXGBE_PSRTYPE_TCPHDR |
3676 IXGBE_PSRTYPE_UDPHDR |
3677 IXGBE_PSRTYPE_IPV4HDR |
3678 IXGBE_PSRTYPE_IPV6HDR;
3679 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
3681 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
3682 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
3683 IXGBE_SRRCTL_BSIZEHDR_MASK);
3684 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
3687 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3689 /* Set if packets are dropped when no descriptors available */
3691 srrctl |= IXGBE_SRRCTL_DROP_EN;
3694 * Configure the RX buffer size in the BSIZEPACKET field of
3695 * the SRRCTL register of the queue.
3696 * The value is in 1 KB resolution. Valid values can be from
3699 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
3700 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
3701 RTE_PKTMBUF_HEADROOM);
3702 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
3703 IXGBE_SRRCTL_BSIZEPKT_MASK);
3704 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
3706 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
3707 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
3709 /* It adds dual VLAN length for supporting dual VLAN */
3710 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
3711 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
3712 dev->data->scattered_rx = 1;
3715 if (dev->data->dev_conf.rxmode.enable_scatter)
3716 dev->data->scattered_rx = 1;
3718 ixgbe_set_rx_function(dev);
3721 * Device configured with multiple RX queues.
3723 ixgbe_dev_mq_rx_configure(dev);
3726 * Setup the Checksum Register.
3727 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
3728 * Enable IP/L4 checkum computation by hardware if requested to do so.
3730 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3731 rxcsum |= IXGBE_RXCSUM_PCSD;
3732 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
3733 rxcsum |= IXGBE_RXCSUM_IPPCSE;
3735 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
3737 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3739 if (hw->mac.type == ixgbe_mac_82599EB ||
3740 hw->mac.type == ixgbe_mac_X540) {
3741 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3742 if (dev->data->dev_conf.rxmode.hw_strip_crc)
3743 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3745 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
3746 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3747 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3754 * Initializes Transmit Unit.
3757 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
3759 struct ixgbe_hw *hw;
3760 struct ixgbe_tx_queue *txq;
3766 PMD_INIT_FUNC_TRACE();
3767 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 /* Enable TX CRC (checksum offload requirement) and hw padding
3770 * (TSO requirement) */
3771 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3772 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
3773 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3775 /* Setup the Base and Length of the Tx Descriptor Rings */
3776 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3777 txq = dev->data->tx_queues[i];
3779 bus_addr = txq->tx_ring_phys_addr;
3780 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
3781 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
3782 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
3783 (uint32_t)(bus_addr >> 32));
3784 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
3785 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
3786 /* Setup the HW Tx Head and TX Tail descriptor pointers */
3787 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
3788 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
3791 * Disable Tx Head Writeback RO bit, since this hoses
3792 * bookkeeping if things aren't delivered in order.
3794 switch (hw->mac.type) {
3795 case ixgbe_mac_82598EB:
3796 txctrl = IXGBE_READ_REG(hw,
3797 IXGBE_DCA_TXCTRL(txq->reg_idx));
3798 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3799 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
3803 case ixgbe_mac_82599EB:
3804 case ixgbe_mac_X540:
3805 case ixgbe_mac_X550:
3806 case ixgbe_mac_X550EM_x:
3808 txctrl = IXGBE_READ_REG(hw,
3809 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
3810 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
3811 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
3817 /* Device configured with multiple TX queues. */
3818 ixgbe_dev_mq_tx_configure(dev);
3822 * Set up link for 82599 loopback mode Tx->Rx.
3825 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
3827 PMD_INIT_FUNC_TRACE();
3829 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3830 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
3832 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
3841 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
3842 ixgbe_reset_pipeline_82599(hw);
3844 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3850 * Start Transmit and Receive Units.
3853 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
3855 struct ixgbe_hw *hw;
3856 struct ixgbe_tx_queue *txq;
3857 struct ixgbe_rx_queue *rxq;
3864 PMD_INIT_FUNC_TRACE();
3865 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3867 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3868 txq = dev->data->tx_queues[i];
3869 /* Setup Transmit Threshold Registers */
3870 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
3871 txdctl |= txq->pthresh & 0x7F;
3872 txdctl |= ((txq->hthresh & 0x7F) << 8);
3873 txdctl |= ((txq->wthresh & 0x7F) << 16);
3874 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
3877 if (hw->mac.type != ixgbe_mac_82598EB) {
3878 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3879 dmatxctl |= IXGBE_DMATXCTL_TE;
3880 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3883 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3884 txq = dev->data->tx_queues[i];
3885 if (!txq->tx_deferred_start) {
3886 ret = ixgbe_dev_tx_queue_start(dev, i);
3892 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3893 rxq = dev->data->rx_queues[i];
3894 if (!rxq->rx_deferred_start) {
3895 ret = ixgbe_dev_rx_queue_start(dev, i);
3901 /* Enable Receive engine */
3902 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3903 if (hw->mac.type == ixgbe_mac_82598EB)
3904 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3905 rxctrl |= IXGBE_RXCTRL_RXEN;
3906 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3908 /* If loopback mode is enabled for 82599, set up the link accordingly */
3909 if (hw->mac.type == ixgbe_mac_82599EB &&
3910 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
3911 ixgbe_setup_loopback_link_82599(hw);
3917 * Start Receive Units for specified queue.
3920 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3922 struct ixgbe_hw *hw;
3923 struct ixgbe_rx_queue *rxq;
3927 PMD_INIT_FUNC_TRACE();
3928 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3930 if (rx_queue_id < dev->data->nb_rx_queues) {
3931 rxq = dev->data->rx_queues[rx_queue_id];
3933 /* Allocate buffers for descriptor rings */
3934 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
3935 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
3939 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3940 rxdctl |= IXGBE_RXDCTL_ENABLE;
3941 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3943 /* Wait until RX Enable ready */
3944 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3947 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3948 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3950 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
3953 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
3954 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
3962 * Stop Receive Units for specified queue.
3965 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
3967 struct ixgbe_hw *hw;
3968 struct ixgbe_rx_queue *rxq;
3972 PMD_INIT_FUNC_TRACE();
3973 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3975 if (rx_queue_id < dev->data->nb_rx_queues) {
3976 rxq = dev->data->rx_queues[rx_queue_id];
3978 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3979 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3980 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
3982 /* Wait until RX Enable ready */
3983 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
3986 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
3987 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
3989 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
3992 rte_delay_us(RTE_IXGBE_WAIT_100_US);
3994 ixgbe_rx_queue_release_mbufs(rxq);
3995 ixgbe_reset_rx_queue(hw, rxq);
4004 * Start Transmit Units for specified queue.
4007 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4009 struct ixgbe_hw *hw;
4010 struct ixgbe_tx_queue *txq;
4014 PMD_INIT_FUNC_TRACE();
4015 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4017 if (tx_queue_id < dev->data->nb_tx_queues) {
4018 txq = dev->data->tx_queues[tx_queue_id];
4019 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4020 txdctl |= IXGBE_TXDCTL_ENABLE;
4021 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4023 /* Wait until TX Enable ready */
4024 if (hw->mac.type == ixgbe_mac_82599EB) {
4025 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4028 txdctl = IXGBE_READ_REG(hw,
4029 IXGBE_TXDCTL(txq->reg_idx));
4030 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4032 PMD_INIT_LOG(ERR, "Could not enable "
4033 "Tx Queue %d", tx_queue_id);
4036 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4037 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4045 * Stop Transmit Units for specified queue.
4048 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4050 struct ixgbe_hw *hw;
4051 struct ixgbe_tx_queue *txq;
4053 uint32_t txtdh, txtdt;
4056 PMD_INIT_FUNC_TRACE();
4057 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059 if (tx_queue_id < dev->data->nb_tx_queues) {
4060 txq = dev->data->tx_queues[tx_queue_id];
4062 /* Wait until TX queue is empty */
4063 if (hw->mac.type == ixgbe_mac_82599EB) {
4064 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4066 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4067 txtdh = IXGBE_READ_REG(hw,
4068 IXGBE_TDH(txq->reg_idx));
4069 txtdt = IXGBE_READ_REG(hw,
4070 IXGBE_TDT(txq->reg_idx));
4071 } while (--poll_ms && (txtdh != txtdt));
4073 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4074 "when stopping.", tx_queue_id);
4077 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4078 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4079 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4081 /* Wait until TX Enable ready */
4082 if (hw->mac.type == ixgbe_mac_82599EB) {
4083 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4086 txdctl = IXGBE_READ_REG(hw,
4087 IXGBE_TXDCTL(txq->reg_idx));
4088 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4090 PMD_INIT_LOG(ERR, "Could not disable "
4091 "Tx Queue %d", tx_queue_id);
4094 if (txq->ops != NULL) {
4095 txq->ops->release_mbufs(txq);
4096 txq->ops->reset(txq);
4105 * [VF] Initializes Receive Unit.
4108 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4110 struct ixgbe_hw *hw;
4111 struct ixgbe_rx_queue *rxq;
4112 struct rte_pktmbuf_pool_private *mbp_priv;
4114 uint32_t srrctl, psrtype = 0;
4119 PMD_INIT_FUNC_TRACE();
4120 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4123 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4124 "it should be power of 2");
4128 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4129 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4130 "it should be equal to or less than %d",
4131 hw->mac.max_rx_queues);
4136 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4137 * disables the VF receipt of packets if the PF MTU is > 1500.
4138 * This is done to deal with 82599 limitations that imposes
4139 * the PF and all VFs to share the same MTU.
4140 * Then, the PF driver enables again the VF receipt of packet when
4141 * the VF driver issues a IXGBE_VF_SET_LPE request.
4142 * In the meantime, the VF device cannot be used, even if the VF driver
4143 * and the Guest VM network stack are ready to accept packets with a
4144 * size up to the PF MTU.
4145 * As a work-around to this PF behaviour, force the call to
4146 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4147 * VF packets received can work in all cases.
4149 ixgbevf_rlpml_set_vf(hw,
4150 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4152 /* Setup RX queues */
4153 dev->rx_pkt_burst = ixgbe_recv_pkts;
4154 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4155 rxq = dev->data->rx_queues[i];
4157 /* Allocate buffers for descriptor rings */
4158 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4162 /* Setup the Base and Length of the Rx Descriptor Rings */
4163 bus_addr = rxq->rx_ring_phys_addr;
4165 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4166 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4167 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4168 (uint32_t)(bus_addr >> 32));
4169 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4170 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4171 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4172 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4175 /* Configure the SRRCTL register */
4176 #ifdef RTE_HEADER_SPLIT_ENABLE
4178 * Configure Header Split
4180 if (dev->data->dev_conf.rxmode.header_split) {
4181 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4182 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4183 IXGBE_SRRCTL_BSIZEHDR_MASK);
4184 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4187 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4189 /* Set if packets are dropped when no descriptors available */
4191 srrctl |= IXGBE_SRRCTL_DROP_EN;
4194 * Configure the RX buffer size in the BSIZEPACKET field of
4195 * the SRRCTL register of the queue.
4196 * The value is in 1 KB resolution. Valid values can be from
4199 mbp_priv = rte_mempool_get_priv(rxq->mb_pool);
4200 buf_size = (uint16_t) (mbp_priv->mbuf_data_room_size -
4201 RTE_PKTMBUF_HEADROOM);
4202 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4203 IXGBE_SRRCTL_BSIZEPKT_MASK);
4206 * VF modification to write virtual function SRRCTL register
4208 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4210 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4211 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4213 if (dev->data->dev_conf.rxmode.enable_scatter ||
4214 /* It adds dual VLAN length for supporting dual VLAN */
4215 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4216 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4217 if (!dev->data->scattered_rx)
4218 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4219 dev->data->scattered_rx = 1;
4220 #ifdef RTE_IXGBE_INC_VECTOR
4221 if (rte_is_power_of_2(rxq->nb_rx_desc))
4223 ixgbe_recv_scattered_pkts_vec;
4226 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts;
4230 #ifdef RTE_HEADER_SPLIT_ENABLE
4231 if (dev->data->dev_conf.rxmode.header_split)
4232 /* Must setup the PSRTYPE register */
4233 psrtype = IXGBE_PSRTYPE_TCPHDR |
4234 IXGBE_PSRTYPE_UDPHDR |
4235 IXGBE_PSRTYPE_IPV4HDR |
4236 IXGBE_PSRTYPE_IPV6HDR;
4239 /* Set RQPL for VF RSS according to max Rx queue */
4240 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4241 IXGBE_PSRTYPE_RQPL_SHIFT;
4242 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4248 * [VF] Initializes Transmit Unit.
4251 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4253 struct ixgbe_hw *hw;
4254 struct ixgbe_tx_queue *txq;
4259 PMD_INIT_FUNC_TRACE();
4260 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262 /* Setup the Base and Length of the Tx Descriptor Rings */
4263 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4264 txq = dev->data->tx_queues[i];
4265 bus_addr = txq->tx_ring_phys_addr;
4266 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4267 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4268 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4269 (uint32_t)(bus_addr >> 32));
4270 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4271 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4272 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4273 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4274 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4277 * Disable Tx Head Writeback RO bit, since this hoses
4278 * bookkeeping if things aren't delivered in order.
4280 txctrl = IXGBE_READ_REG(hw,
4281 IXGBE_VFDCA_TXCTRL(i));
4282 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4283 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4289 * [VF] Start Transmit and Receive Units.
4292 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4294 struct ixgbe_hw *hw;
4295 struct ixgbe_tx_queue *txq;
4296 struct ixgbe_rx_queue *rxq;
4302 PMD_INIT_FUNC_TRACE();
4303 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4305 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4306 txq = dev->data->tx_queues[i];
4307 /* Setup Transmit Threshold Registers */
4308 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4309 txdctl |= txq->pthresh & 0x7F;
4310 txdctl |= ((txq->hthresh & 0x7F) << 8);
4311 txdctl |= ((txq->wthresh & 0x7F) << 16);
4312 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4315 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4317 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4318 txdctl |= IXGBE_TXDCTL_ENABLE;
4319 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4322 /* Wait until TX Enable ready */
4325 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4326 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4328 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4330 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4332 rxq = dev->data->rx_queues[i];
4334 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4335 rxdctl |= IXGBE_RXDCTL_ENABLE;
4336 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4338 /* Wait until RX Enable ready */
4342 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4343 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4345 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4347 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4352 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4353 int __attribute__((weak))
4354 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4359 uint16_t __attribute__((weak))
4360 ixgbe_recv_pkts_vec(
4361 void __rte_unused *rx_queue,
4362 struct rte_mbuf __rte_unused **rx_pkts,
4363 uint16_t __rte_unused nb_pkts)
4368 uint16_t __attribute__((weak))
4369 ixgbe_recv_scattered_pkts_vec(
4370 void __rte_unused *rx_queue,
4371 struct rte_mbuf __rte_unused **rx_pkts,
4372 uint16_t __rte_unused nb_pkts)
4377 int __attribute__((weak))
4378 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)