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34 #ifndef _IXGBE_RXTX_H_
35 #define _IXGBE_RXTX_H_
38 #define RTE_PMD_IXGBE_TX_MAX_BURST 32
40 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
41 #define RTE_PMD_IXGBE_RX_MAX_BURST 32
42 #define RTE_IXGBE_DESCS_PER_LOOP 4
43 #elif defined(RTE_IXGBE_INC_VECTOR)
44 #define RTE_IXGBE_DESCS_PER_LOOP 4
46 #define RTE_IXGBE_DESCS_PER_LOOP 1
49 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
50 (uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
52 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
53 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
55 #ifdef RTE_IXGBE_INC_VECTOR
56 #define RTE_IXGBE_VPMD_RX_BURST 32
57 #define RTE_IXGBE_VPMD_TX_BURST 32
58 #define RTE_IXGBE_RXQ_REARM_THRESH RTE_IXGBE_VPMD_RX_BURST
59 #define RTE_IXGBE_TX_MAX_FREE_BUF_SZ 64
62 #define RX_RING_SZ ((IXGBE_MAX_RING_DESC + RTE_IXGBE_DESCS_PER_LOOP - 1) * \
63 sizeof(union ixgbe_adv_rx_desc))
65 #ifdef RTE_PMD_PACKET_PREFETCH
66 #define rte_packet_prefetch(p) rte_prefetch1(p)
68 #define rte_packet_prefetch(p) do {} while(0)
71 #define RTE_IXGBE_REGISTER_POLL_WAIT_10_MS 10
72 #define RTE_IXGBE_WAIT_100_US 100
73 #define RTE_IXGBE_VMTXSW_REGISTER_COUNT 2
76 * Structure associated with each descriptor of the RX ring of a RX queue.
79 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
83 * Structure associated with each descriptor of the TX ring of a TX queue.
86 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
87 uint16_t next_id; /**< Index of next descriptor in ring. */
88 uint16_t last_id; /**< Index of last scattered descriptor. */
92 * Structure associated with each descriptor of the TX ring of a TX queue.
94 struct igb_tx_entry_v {
95 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
99 * Structure associated with each RX queue.
101 struct igb_rx_queue {
102 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
103 volatile union ixgbe_adv_rx_desc *rx_ring; /**< RX ring virtual address. */
104 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
105 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
106 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
107 struct igb_rx_entry *sw_ring; /**< address of RX software ring. */
108 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
109 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
110 uint64_t mbuf_initializer; /**< value to init mbufs */
111 uint16_t nb_rx_desc; /**< number of RX descriptors. */
112 uint16_t rx_tail; /**< current value of RDT register. */
113 uint16_t nb_rx_hold; /**< number of held free RX desc. */
114 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
115 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
116 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
117 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
119 #ifdef RTE_IXGBE_INC_VECTOR
120 uint16_t rxrearm_nb; /**< the idx we start the re-arming from */
121 uint16_t rxrearm_start; /**< number of remaining to be re-armed */
123 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
124 uint16_t queue_id; /**< RX queue index. */
125 uint16_t reg_idx; /**< RX queue register index. */
126 uint8_t port_id; /**< Device port identifier. */
127 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
128 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
129 uint8_t rx_deferred_start; /**< not in global dev start. */
130 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
131 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
132 struct rte_mbuf fake_mbuf;
133 /** hold packets to return to application */
134 struct rte_mbuf *rx_stage[RTE_PMD_IXGBE_RX_MAX_BURST*2];
139 * IXGBE CTX Constants
141 enum ixgbe_advctx_num {
142 IXGBE_CTX_0 = 0, /**< CTX0 */
143 IXGBE_CTX_1 = 1, /**< CTX1 */
144 IXGBE_CTX_NUM = 2, /**< CTX NUMBER */
147 /** Offload features */
148 union ixgbe_vlan_macip {
151 uint16_t l2_l3_len; /**< combined 9-bit l3, 7-bit l2 lengths */
153 /**< VLAN Tag Control Identifier (CPU order). */
158 * Compare mask for vlan_macip_len.data,
159 * should be in sync with ixgbe_vlan_macip.f layout.
161 #define TX_VLAN_CMP_MASK 0xFFFF0000 /**< VLAN length - 16-bits. */
162 #define TX_MAC_LEN_CMP_MASK 0x0000FE00 /**< MAC length - 7-bits. */
163 #define TX_IP_LEN_CMP_MASK 0x000001FF /**< IP length - 9-bits. */
164 /** MAC+IP length. */
165 #define TX_MACIP_LEN_CMP_MASK (TX_MAC_LEN_CMP_MASK | TX_IP_LEN_CMP_MASK)
168 * Structure to check if new context need be built
171 struct ixgbe_advctx_info {
172 uint64_t flags; /**< ol_flags for context build. */
173 uint32_t cmp_mask; /**< compare mask for vlan_macip_lens */
174 union ixgbe_vlan_macip vlan_macip_lens; /**< vlan, mac ip length. */
178 * Structure associated with each TX queue.
180 struct igb_tx_queue {
181 /** TX ring virtual address. */
182 volatile union ixgbe_adv_tx_desc *tx_ring;
183 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
184 struct igb_tx_entry *sw_ring; /**< virtual address of SW ring. */
185 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
186 uint16_t nb_tx_desc; /**< number of TX descriptors. */
187 uint16_t tx_tail; /**< current value of TDT reg. */
188 uint16_t tx_free_thresh;/**< minimum TX before freeing. */
189 /** Number of TX descriptors to use before RS bit is set. */
190 uint16_t tx_rs_thresh;
191 /** Number of TX descriptors used since RS bit was set. */
193 /** Index to last TX descriptor to have been cleaned. */
194 uint16_t last_desc_cleaned;
195 /** Total number of TX descriptors ready to be allocated. */
197 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
198 uint16_t tx_next_rs; /**< next desc to set RS bit */
199 uint16_t queue_id; /**< TX queue index. */
200 uint16_t reg_idx; /**< TX queue register index. */
201 uint8_t port_id; /**< Device port identifier. */
202 uint8_t pthresh; /**< Prefetch threshold register. */
203 uint8_t hthresh; /**< Host threshold register. */
204 uint8_t wthresh; /**< Write-back threshold reg. */
205 uint32_t txq_flags; /**< Holds flags for this TXq */
206 uint32_t ctx_curr; /**< Hardware context states. */
207 /** Hardware context0 history. */
208 struct ixgbe_advctx_info ctx_cache[IXGBE_CTX_NUM];
209 struct ixgbe_txq_ops *ops; /**< txq ops */
210 uint8_t tx_deferred_start; /**< not in global dev start. */
213 struct ixgbe_txq_ops {
214 void (*release_mbufs)(struct igb_tx_queue *txq);
215 void (*free_swring)(struct igb_tx_queue *txq);
216 void (*reset)(struct igb_tx_queue *txq);
220 * The "simple" TX queue functions require that the following
221 * flags are set when the TX queue is configured:
222 * - ETH_TXQ_FLAGS_NOMULTSEGS
223 * - ETH_TXQ_FLAGS_NOVLANOFFL
224 * - ETH_TXQ_FLAGS_NOXSUMSCTP
225 * - ETH_TXQ_FLAGS_NOXSUMUDP
226 * - ETH_TXQ_FLAGS_NOXSUMTCP
227 * and that the RS bit threshold (tx_rs_thresh) is at least equal to
228 * RTE_PMD_IXGBE_TX_MAX_BURST.
230 #define IXGBE_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
231 ETH_TXQ_FLAGS_NOOFFLOADS)
234 * Populate descriptors with the following info:
235 * 1.) buffer_addr = phys_addr + headroom
236 * 2.) cmd_type_len = DCMD_DTYP_FLAGS | pkt_len
237 * 3.) olinfo_status = pkt_len << PAYLEN_SHIFT
240 /* Defines for Tx descriptor */
241 #define DCMD_DTYP_FLAGS (IXGBE_ADVTXD_DTYP_DATA |\
242 IXGBE_ADVTXD_DCMD_IFCS |\
243 IXGBE_ADVTXD_DCMD_DEXT |\
244 IXGBE_ADVTXD_DCMD_EOP)
246 #ifdef RTE_IXGBE_INC_VECTOR
247 uint16_t ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
249 uint16_t ixgbe_recv_scattered_pkts_vec(void *rx_queue,
250 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
251 uint16_t ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
253 int ixgbe_txq_vec_setup(struct igb_tx_queue *txq);
254 int ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq);
255 int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev);