4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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35 #include <rte_ethdev.h>
36 #include <rte_malloc.h>
38 #include "ixgbe_ethdev.h"
39 #include "ixgbe_rxtx.h"
41 #include <tmmintrin.h>
43 #ifndef __INTEL_COMPILER
44 #pragma GCC diagnostic ignored "-Wcast-qual"
48 ixgbe_rxq_rearm(struct igb_rx_queue *rxq)
52 volatile union ixgbe_adv_rx_desc *rxdp;
53 struct igb_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
54 struct rte_mbuf *mb0, *mb1;
55 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
56 RTE_PKTMBUF_HEADROOM);
57 __m128i dma_addr0, dma_addr1;
59 rxdp = rxq->rx_ring + rxq->rxrearm_start;
61 /* Pull 'n' more MBUFs into the software ring */
62 if (rte_mempool_get_bulk(rxq->mb_pool,
64 RTE_IXGBE_RXQ_REARM_THRESH) < 0) {
65 if (rxq->rxrearm_nb + RTE_IXGBE_RXQ_REARM_THRESH >=
67 dma_addr0 = _mm_setzero_si128();
68 for (i = 0; i < RTE_IXGBE_DESCS_PER_LOOP; i++) {
69 rxep[i].mbuf = &rxq->fake_mbuf;
70 _mm_store_si128((__m128i *)&rxdp[i].read,
77 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
78 for (i = 0; i < RTE_IXGBE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
79 __m128i vaddr0, vaddr1;
84 /* flush mbuf with pkt template */
85 mb0->rearm_data[0] = rxq->mbuf_initializer;
86 mb1->rearm_data[0] = rxq->mbuf_initializer;
88 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
89 vaddr0 = _mm_loadu_si128((__m128i *)&(mb0->buf_addr));
90 vaddr1 = _mm_loadu_si128((__m128i *)&(mb1->buf_addr));
92 /* convert pa to dma_addr hdr/data */
93 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
94 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
96 /* add headroom to pa values */
97 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
98 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
100 /* flush desc with pa dma_addr */
101 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
102 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
105 rxq->rxrearm_start += RTE_IXGBE_RXQ_REARM_THRESH;
106 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
107 rxq->rxrearm_start = 0;
109 rxq->rxrearm_nb -= RTE_IXGBE_RXQ_REARM_THRESH;
111 rx_id = (uint16_t) ((rxq->rxrearm_start == 0) ?
112 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
114 /* Update the tail pointer on the NIC */
115 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
118 /* Handling the offload flags (olflags) field takes computation
119 * time when receiving packets. Therefore we provide a flag to disable
120 * the processing of the olflags field when they are not needed. This
121 * gives improved performance, at the cost of losing the offload info
122 * in the received packet
124 #ifdef RTE_IXGBE_RX_OLFLAGS_ENABLE
126 #define OLFLAGS_MASK ((uint16_t)(PKT_RX_VLAN_PKT | PKT_RX_IPV4_HDR |\
127 PKT_RX_IPV4_HDR_EXT | PKT_RX_IPV6_HDR |\
128 PKT_RX_IPV6_HDR_EXT))
129 #define OLFLAGS_MASK_V (((uint64_t)OLFLAGS_MASK << 48) | \
130 ((uint64_t)OLFLAGS_MASK << 32) | \
131 ((uint64_t)OLFLAGS_MASK << 16) | \
132 ((uint64_t)OLFLAGS_MASK))
133 #define PTYPE_SHIFT (1)
134 #define VTAG_SHIFT (3)
137 desc_to_olflags_v(__m128i descs[4], struct rte_mbuf **rx_pkts)
139 __m128i ptype0, ptype1, vtag0, vtag1;
145 ptype0 = _mm_unpacklo_epi16(descs[0], descs[1]);
146 ptype1 = _mm_unpacklo_epi16(descs[2], descs[3]);
147 vtag0 = _mm_unpackhi_epi16(descs[0], descs[1]);
148 vtag1 = _mm_unpackhi_epi16(descs[2], descs[3]);
150 ptype1 = _mm_unpacklo_epi32(ptype0, ptype1);
151 vtag1 = _mm_unpacklo_epi32(vtag0, vtag1);
153 ptype1 = _mm_slli_epi16(ptype1, PTYPE_SHIFT);
154 vtag1 = _mm_srli_epi16(vtag1, VTAG_SHIFT);
156 ptype1 = _mm_or_si128(ptype1, vtag1);
157 vol.dword = _mm_cvtsi128_si64(ptype1) & OLFLAGS_MASK_V;
159 rx_pkts[0]->ol_flags = vol.e[0];
160 rx_pkts[1]->ol_flags = vol.e[1];
161 rx_pkts[2]->ol_flags = vol.e[2];
162 rx_pkts[3]->ol_flags = vol.e[3];
165 #define desc_to_olflags_v(desc, rx_pkts) do {} while (0)
169 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
173 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
174 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
176 * - don't support ol_flags for rss and csum err
178 static inline uint16_t
179 _recv_raw_pkts_vec(struct igb_rx_queue *rxq, struct rte_mbuf **rx_pkts,
180 uint16_t nb_pkts, uint8_t *split_packet)
182 volatile union ixgbe_adv_rx_desc *rxdp;
183 struct igb_rx_entry *sw_ring;
184 uint16_t nb_pkts_recd;
188 __m128i crc_adjust = _mm_set_epi16(
189 0, 0, 0, 0, /* ignore non-length fields */
190 0, /* ignore high-16bits of pkt_len */
191 -rxq->crc_len, /* sub crc on pkt_len */
192 -rxq->crc_len, /* sub crc on data_len */
193 0 /* ignore pkt_type field */
195 __m128i dd_check, eop_check;
197 if (unlikely(nb_pkts < RTE_IXGBE_VPMD_RX_BURST))
200 /* Just the act of getting into the function from the application is
201 * going to cost about 7 cycles */
202 rxdp = rxq->rx_ring + rxq->rx_tail;
204 _mm_prefetch((const void *)rxdp, _MM_HINT_T0);
206 /* See if we need to rearm the RX queue - gives the prefetch a bit
208 if (rxq->rxrearm_nb > RTE_IXGBE_RXQ_REARM_THRESH)
209 ixgbe_rxq_rearm(rxq);
211 /* Before we start moving massive data around, check to see if
212 * there is actually a packet available */
213 if (!(rxdp->wb.upper.status_error &
214 rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
217 /* 4 packets DD mask */
218 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
220 /* 4 packets EOP mask */
221 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
223 /* mask to shuffle from desc. to mbuf */
224 shuf_msk = _mm_set_epi8(
225 7, 6, 5, 4, /* octet 4~7, 32bits rss */
226 0xFF, 0xFF, /* skip high 16 bits vlan_macip, zero out */
227 15, 14, /* octet 14~15, low 16 bits vlan_macip */
228 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
229 13, 12, /* octet 12~13, low 16 bits pkt_len */
230 13, 12, /* octet 12~13, 16 bits data_len */
231 0xFF, 0xFF /* skip pkt_type field */
234 /* Cache is empty -> need to scan the buffer rings, but first move
235 * the next 'n' mbufs into the cache */
236 sw_ring = &rxq->sw_ring[rxq->rx_tail];
239 * A. load 4 packet in one loop
240 * B. copy 4 mbuf point from swring to rx_pkts
241 * C. calc the number of DD bits among the 4 packets
242 * [C*. extract the end-of-packet bit, if requested]
243 * D. fill info. from desc to mbuf
245 for (pos = 0, nb_pkts_recd = 0; pos < RTE_IXGBE_VPMD_RX_BURST;
246 pos += RTE_IXGBE_DESCS_PER_LOOP,
247 rxdp += RTE_IXGBE_DESCS_PER_LOOP) {
248 __m128i descs[RTE_IXGBE_DESCS_PER_LOOP];
249 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
250 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
251 __m128i mbp1, mbp2; /* two mbuf pointer in one XMM reg. */
254 rte_prefetch0(&rx_pkts[pos]->cacheline1);
255 rte_prefetch0(&rx_pkts[pos + 1]->cacheline1);
256 rte_prefetch0(&rx_pkts[pos + 2]->cacheline1);
257 rte_prefetch0(&rx_pkts[pos + 3]->cacheline1);
260 /* B.1 load 1 mbuf point */
261 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
263 /* Read desc statuses backwards to avoid race condition */
264 /* A.1 load 4 pkts desc */
265 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
267 /* B.2 copy 2 mbuf point into rx_pkts */
268 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
270 /* B.1 load 1 mbuf point */
271 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos+2]);
273 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
274 /* B.1 load 2 mbuf point */
275 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
276 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
278 /* B.2 copy 2 mbuf point into rx_pkts */
279 _mm_storeu_si128((__m128i *)&rx_pkts[pos+2], mbp2);
281 /* avoid compiler reorder optimization */
282 rte_compiler_barrier();
284 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
285 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
286 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
288 /* C.1 4=>2 filter staterr info only */
289 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
290 /* C.1 4=>2 filter staterr info only */
291 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
293 /* set ol_flags with packet type and vlan tag */
294 desc_to_olflags_v(descs, &rx_pkts[pos]);
296 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
297 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
298 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
300 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
301 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
302 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
304 /* C.2 get 4 pkts staterr value */
305 zero = _mm_xor_si128(dd_check, dd_check);
306 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
308 /* D.3 copy final 3,4 data to rx_pkts */
309 _mm_storeu_si128((void *)&rx_pkts[pos+3]->rx_descriptor_fields1,
311 _mm_storeu_si128((void *)&rx_pkts[pos+2]->rx_descriptor_fields1,
314 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
315 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
316 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
318 /* C* extract and record EOP bit */
320 __m128i eop_shuf_mask = _mm_set_epi8(
321 0xFF, 0xFF, 0xFF, 0xFF,
322 0xFF, 0xFF, 0xFF, 0xFF,
323 0xFF, 0xFF, 0xFF, 0xFF,
324 0x04, 0x0C, 0x00, 0x08
327 /* and with mask to extract bits, flipping 1-0 */
328 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
329 /* the staterr values are not in order, as the count
330 * count of dd bits doesn't care. However, for end of
331 * packet tracking, we do care, so shuffle. This also
332 * compresses the 32-bit values to 8-bit */
333 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
334 /* store the resulting 32-bit value */
335 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
336 split_packet += RTE_IXGBE_DESCS_PER_LOOP;
338 /* zero-out next pointers */
339 rx_pkts[pos]->next = NULL;
340 rx_pkts[pos + 1]->next = NULL;
341 rx_pkts[pos + 2]->next = NULL;
342 rx_pkts[pos + 3]->next = NULL;
345 /* C.3 calc available number of desc */
346 staterr = _mm_and_si128(staterr, dd_check);
347 staterr = _mm_packs_epi32(staterr, zero);
349 /* D.3 copy final 1,2 data to rx_pkts */
350 _mm_storeu_si128((void *)&rx_pkts[pos+1]->rx_descriptor_fields1,
352 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
355 /* C.4 calc avaialbe number of desc */
356 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
358 if (likely(var != RTE_IXGBE_DESCS_PER_LOOP))
362 /* Update our internal tail pointer */
363 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
364 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
365 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
371 * vPMD receive routine, now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
375 * - nb_pkts < RTE_IXGBE_VPMD_RX_BURST, just return no packet
376 * - nb_pkts > RTE_IXGBE_VPMD_RX_BURST, only scan RTE_IXGBE_VPMD_RX_BURST
378 * - don't support ol_flags for rss and csum err
381 ixgbe_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
384 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
387 static inline uint16_t
388 reassemble_packets(struct igb_rx_queue *rxq, struct rte_mbuf **rx_bufs,
389 uint16_t nb_bufs, uint8_t *split_flags)
391 struct rte_mbuf *pkts[RTE_IXGBE_VPMD_RX_BURST]; /*finished pkts*/
392 struct rte_mbuf *start = rxq->pkt_first_seg;
393 struct rte_mbuf *end = rxq->pkt_last_seg;
394 unsigned pkt_idx = 0, buf_idx = 0;
397 while (buf_idx < nb_bufs) {
399 /* processing a split packet */
400 end->next = rx_bufs[buf_idx];
401 rx_bufs[buf_idx]->data_len += rxq->crc_len;
404 start->pkt_len += rx_bufs[buf_idx]->data_len;
407 if (!split_flags[buf_idx]) {
408 /* it's the last packet of the set */
409 start->hash = end->hash;
410 start->ol_flags = end->ol_flags;
411 /* we need to strip crc for the whole packet */
412 start->pkt_len -= rxq->crc_len;
413 if (end->data_len > rxq->crc_len)
414 end->data_len -= rxq->crc_len;
416 /* free up last mbuf */
417 struct rte_mbuf *secondlast = start;
418 while (secondlast->next != end)
419 secondlast = secondlast->next;
420 secondlast->data_len -= (rxq->crc_len -
422 secondlast->next = NULL;
423 rte_pktmbuf_free_seg(end);
426 pkts[pkt_idx++] = start;
430 /* not processing a split packet */
431 if (!split_flags[buf_idx]) {
432 /* not a split packet, save and skip */
433 pkts[pkt_idx++] = rx_bufs[buf_idx];
436 end = start = rx_bufs[buf_idx];
437 rx_bufs[buf_idx]->data_len += rxq->crc_len;
438 rx_bufs[buf_idx]->pkt_len += rxq->crc_len;
443 /* save the partial packet for next time */
444 rxq->pkt_first_seg = start;
445 rxq->pkt_last_seg = end;
446 memcpy(rx_bufs, pkts, pkt_idx * (sizeof(*pkts)));
451 * vPMD receive routine that reassembles scattered packets
454 * - don't support ol_flags for rss and csum err
455 * - now only accept (nb_pkts == RTE_IXGBE_VPMD_RX_BURST)
458 ixgbe_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
461 struct igb_rx_queue *rxq = rx_queue;
462 uint8_t split_flags[RTE_IXGBE_VPMD_RX_BURST] = {0};
464 /* get some new buffers */
465 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
470 /* happy day case, full burst + no packets to be joined */
471 const uint32_t *split_fl32 = (uint32_t *)split_flags;
472 if (rxq->pkt_first_seg == NULL &&
473 split_fl32[0] == 0 && split_fl32[1] == 0 &&
474 split_fl32[2] == 0 && split_fl32[3] == 0)
477 /* reassemble any packets that need reassembly*/
479 if (rxq->pkt_first_seg == NULL) {
480 /* find the first split flag, and only reassemble then*/
481 while (!split_flags[i] && i < nb_bufs)
486 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
491 vtx1(volatile union ixgbe_adv_tx_desc *txdp,
492 struct rte_mbuf *pkt, uint64_t flags)
494 __m128i descriptor = _mm_set_epi64x((uint64_t)pkt->pkt_len << 46 |
495 flags | pkt->data_len,
496 pkt->buf_physaddr + pkt->data_off);
497 _mm_store_si128((__m128i *)&txdp->read, descriptor);
501 vtx(volatile union ixgbe_adv_tx_desc *txdp,
502 struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags)
505 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
506 vtx1(txdp, *pkt, flags);
509 static inline int __attribute__((always_inline))
510 ixgbe_tx_free_bufs(struct igb_tx_queue *txq)
512 struct igb_tx_entry_v *txep;
517 struct rte_mbuf *m, *free[RTE_IXGBE_TX_MAX_FREE_BUF_SZ];
519 /* check DD bit on threshold descriptor */
520 status = txq->tx_ring[txq->tx_next_dd].wb.status;
521 if (!(status & IXGBE_ADVTXD_STAT_DD))
524 n = txq->tx_rs_thresh;
527 * first buffer to free from S/W ring is at index
528 * tx_next_dd - (tx_rs_thresh-1)
530 txep = &((struct igb_tx_entry_v *)txq->sw_ring)[txq->tx_next_dd -
532 #ifdef RTE_MBUF_REFCNT
533 m = __rte_pktmbuf_prefree_seg(txep[0].mbuf);
537 if (likely(m != NULL)) {
540 for (i = 1; i < n; i++) {
541 #ifdef RTE_MBUF_REFCNT
542 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
546 if (likely(m != NULL)) {
547 if (likely(m->pool == free[0]->pool))
550 rte_mempool_put_bulk(free[0]->pool,
551 (void *)free, nb_free);
557 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
559 for (i = 1; i < n; i++) {
560 m = __rte_pktmbuf_prefree_seg(txep[i].mbuf);
562 rte_mempool_put(m->pool, m);
566 /* buffers were freed, update counters */
567 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
568 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
569 if (txq->tx_next_dd >= txq->nb_tx_desc)
570 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
572 return txq->tx_rs_thresh;
575 static inline void __attribute__((always_inline))
576 tx_backlog_entry(struct igb_tx_entry_v *txep,
577 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
580 for (i = 0; i < (int)nb_pkts; ++i)
581 txep[i].mbuf = tx_pkts[i];
585 ixgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
588 struct igb_tx_queue *txq = (struct igb_tx_queue *)tx_queue;
589 volatile union ixgbe_adv_tx_desc *txdp;
590 struct igb_tx_entry_v *txep;
591 uint16_t n, nb_commit, tx_id;
592 uint64_t flags = DCMD_DTYP_FLAGS;
593 uint64_t rs = IXGBE_ADVTXD_DCMD_RS|DCMD_DTYP_FLAGS;
596 if (unlikely(nb_pkts > RTE_IXGBE_VPMD_TX_BURST))
597 nb_pkts = RTE_IXGBE_VPMD_TX_BURST;
599 if (txq->nb_tx_free < txq->tx_free_thresh)
600 ixgbe_tx_free_bufs(txq);
602 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
603 if (unlikely(nb_pkts == 0))
606 tx_id = txq->tx_tail;
607 txdp = &txq->tx_ring[tx_id];
608 txep = &((struct igb_tx_entry_v *)txq->sw_ring)[tx_id];
610 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
612 n = (uint16_t)(txq->nb_tx_desc - tx_id);
613 if (nb_commit >= n) {
615 tx_backlog_entry(txep, tx_pkts, n);
617 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
618 vtx1(txdp, *tx_pkts, flags);
620 vtx1(txdp, *tx_pkts++, rs);
622 nb_commit = (uint16_t)(nb_commit - n);
625 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
627 /* avoid reach the end of ring */
628 txdp = &(txq->tx_ring[tx_id]);
629 txep = &(((struct igb_tx_entry_v *)txq->sw_ring)[tx_id]);
632 tx_backlog_entry(txep, tx_pkts, nb_commit);
634 vtx(txdp, tx_pkts, nb_commit, flags);
636 tx_id = (uint16_t)(tx_id + nb_commit);
637 if (tx_id > txq->tx_next_rs) {
638 txq->tx_ring[txq->tx_next_rs].read.cmd_type_len |=
639 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
640 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
644 txq->tx_tail = tx_id;
646 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
652 ixgbe_tx_queue_release_mbufs(struct igb_tx_queue *txq)
655 struct igb_tx_entry_v *txe;
656 uint16_t nb_free, max_desc;
658 if (txq->sw_ring != NULL) {
659 /* release the used mbufs in sw_ring */
660 nb_free = txq->nb_tx_free;
661 max_desc = (uint16_t)(txq->nb_tx_desc - 1);
662 for (i = txq->tx_next_dd - (txq->tx_rs_thresh - 1);
663 nb_free < max_desc && i != txq->tx_tail;
664 i = (i + 1) & max_desc) {
665 txe = (struct igb_tx_entry_v *)&txq->sw_ring[i];
666 if (txe->mbuf != NULL)
667 rte_pktmbuf_free_seg(txe->mbuf);
670 for (i = 0; i < txq->nb_tx_desc; i++) {
671 txe = (struct igb_tx_entry_v *)&txq->sw_ring[i];
678 ixgbe_tx_free_swring(struct igb_tx_queue *txq)
683 if (txq->sw_ring != NULL) {
684 rte_free((struct igb_rx_entry *)txq->sw_ring - 1);
690 ixgbe_reset_tx_queue(struct igb_tx_queue *txq)
692 static const union ixgbe_adv_tx_desc zeroed_desc = { .read = {
694 struct igb_tx_entry_v *txe = (struct igb_tx_entry_v *)txq->sw_ring;
697 /* Zero out HW ring memory */
698 for (i = 0; i < txq->nb_tx_desc; i++)
699 txq->tx_ring[i] = zeroed_desc;
701 /* Initialize SW ring entries */
702 for (i = 0; i < txq->nb_tx_desc; i++) {
703 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
704 txd->wb.status = IXGBE_TXD_STAT_DD;
708 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
709 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
714 * Always allow 1 descriptor to be un-allocated to avoid
715 * a H/W race condition
717 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
718 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
720 memset((void *)&txq->ctx_cache, 0,
721 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
724 static struct ixgbe_txq_ops vec_txq_ops = {
725 .release_mbufs = ixgbe_tx_queue_release_mbufs,
726 .free_swring = ixgbe_tx_free_swring,
727 .reset = ixgbe_reset_tx_queue,
731 ixgbe_rxq_vec_setup(struct igb_rx_queue *rxq)
733 struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
736 mb_def.data_off = RTE_PKTMBUF_HEADROOM;
737 mb_def.buf_len = rxq->mb_pool->elt_size - sizeof(struct rte_mbuf);
738 mb_def.port = rxq->port_id;
739 rte_mbuf_refcnt_set(&mb_def, 1);
740 rxq->mbuf_initializer = *((uint64_t *)&mb_def.rearm_data);
744 int ixgbe_txq_vec_setup(struct igb_tx_queue *txq)
746 if (txq->sw_ring == NULL)
749 /* leave the first one for overflow */
750 txq->sw_ring = (struct igb_tx_entry *)
751 ((struct igb_tx_entry_v *)txq->sw_ring + 1);
752 txq->ops = &vec_txq_ops;
757 int ixgbe_rx_vec_condition_check(struct rte_eth_dev *dev)
759 #ifndef RTE_LIBRTE_IEEE1588
760 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
761 struct rte_fdir_conf *fconf = &dev->data->dev_conf.fdir_conf;
763 #ifndef RTE_IXGBE_RX_OLFLAGS_ENABLE
764 /* whithout rx ol_flags, no VP flag report */
765 if (rxmode->hw_vlan_strip != 0 ||
766 rxmode->hw_vlan_extend != 0)
770 /* no fdir support */
771 if (fconf->mode != RTE_FDIR_MODE_NONE)
775 * - no csum error report support
776 * - no header split support
778 if (rxmode->hw_ip_checksum == 1 ||
779 rxmode->header_split == 1)