2 * Copyright Droids Corporation, Microb Technology, Eirbot (2005)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 * Revision : $Id: adc_archs.h,v 1.4.4.4 2009-02-27 21:37:49 zer0 Exp $
25 /** this file contains definitions for following configuration constants :
27 ADC_REF_xxx : selection of a reference source
29 MUX_xxx : selection options for the analog input multiplexerof the ADC
31 prescaler : selected automatically with your clock setting.
35 /* ------------------------------------------------------------------------------------
36 ---------------------------- REGISTER VARIATIONS -------------------------------
37 ------------------------------------------------------------------------------------ */
41 Detailed register configurations, over the various AVR micros:
43 ADMUX ADCSRA ADCSRB SFIOR
44 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
45 ATM64 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0
46 also AT90CAN64 AT90CAN64 ATM164 ATM324 ATM644 ATM165 (ATM325 ATM3250 ATM645 ATM5450)
48 ATM128 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0
51 AT90CAN128 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADHSM ADTS2 ADTS1 ADTS0
52 also AT90USB1286 ATUSB1287 ATUSB646 ATUSB647
54 ATM16 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0
57 ATM48 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0
58 also ATM88 ATM168 ATM169 ATM329 ATM3290 ATM649 ATM6490
60 ATM8 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0
62 AT90PWM2 REFS1 REFS0 ADLAR - MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADHSM ADASCR ADTS2 ADTS1 ADTS0
63 also AT90PWM3 (! AT90PWM2B and 3B do not have ADASCR !)
65 ATM640 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 MUX5 ADTS2 ADTS1 ADTS0
66 also ATM1280 ATM1281 ATM2560 ATM2561
68 ATtiny13 - REFS0 ADLAR - - - MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADTS2 ADTS1 ADTS0
69 ATtiny15 REFS1 REFS0 ADLAR - - MUX2 MUX1 MUX0 ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0
70 ATtiny24 REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 BIN ADLAR ADTS2 ADTS1 ADTS0
71 also ATtiny44 ATtiny84
72 ATtiny25 REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 BIN - IPR ADTS2 ADTS1 ADTS0
73 also ATtiny45 ATtiny85
78 ATmega325_3250_645_6540 : preliminary incomplete DS, so not implemented now
80 NO ADC : ATM162 ATM8515 ATtiny11 ATtiny12 ATtiny2313 ATtiny28
82 ATMEGA406 : completely different, 12bits, not implemented
86 /* some default defines */
87 #define MUX5_MASK_IN_CONFIG (1<<MUX5)
88 #define ADLAR_MASK_IN_CONFIG (1<<ADLAR)
93 #if ( defined (__AVR_ATmega162__) \
94 || defined (__AVR_ATmega8515__) \
95 || defined (__AVR_ATtiny11__) || defined (__AVR_ATtiny12__) \
96 || defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny28__) )
98 # error no ADC on your AVR device, please deactivate the ADC module
101 #if ( defined (__AVR_ATmega406__) )
102 # error no The ADC of the ATmega406 is currently not supported by the ADC module
105 #if ( defined (__AVR_ATmega325__) || defined (__AVR_ATmega2350__) \
106 || defined (__AVR_ATmega645__) || defined (__AVR_ATmega6540__) )
108 # error ADC module not implemented currently for your device (only incomplete preliminary Datasheet available)
111 /* this is not used for the moment */
112 #if ( defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__) \
113 || defined (__AVR_ATmega8535__) )
115 # define ADTS_IN_SFIOR
118 /* this is a pity, on these devices, two bits are relocated */
119 #if ( defined (__AVR_ATtiny24__) || defined (__AVR_ATtiny44__) \
120 || defined (__AVR_ATtiny84__) )
122 # define ADLAR_IN_ADCSRB
123 # define MUX5_IN_ADMUX
125 # undef ADLAR_MASK_IN_CONFIG
126 # define ADLAR_MASK_IN_CONFIG 0x0100
129 /* additional mux5, this time at another location */
130 #if ( defined (__AVR_ATmega640__) \
131 || defined (__AVR_ATmega1280__) || defined (__AVR_ATmega1281__) \
132 || defined (__AVR_ATmega2560__) || defined (__AVR_ATmega2561__) )
134 # define MUX5_IN_ADCSRB
136 # undef MUX5_MASK_IN_CONFIG
137 # define MUX5_MASK_IN_CONFIG 0x0100
147 /* ------------------------------------------------------------------------------------
148 ---------------------------- REF SELECTION -------------------------------------
149 ------------------------------------------------------------------------------------ */
153 0 : AREF is reference
154 1 : AVCC is reference
155 2 : internal reference2 (rarely available)
156 3 : internal reference1 (2.56 or 1.1 V, depends on AVR type, see DS)
158 VREF2 is available on : ATM164 ATM324 ATM644 ATM640 ATM1280 ATM1281 ATM2561
159 VREF2 is without external cap on : ATtiny24-44-84
160 more options on ATtiny25-45-85, not implmented yet
164 #define ADC_REF_AREF (0 << REFS0)
165 #define ADC_REF_AVCC (1 << REFS0)
166 #define ADC_REF_VREF2 (2 << REFS0)
167 #define ADC_REF_VREF (3 << REFS0)
171 /* ------------------------------------------------------------------------------------
172 ---------------------------- MUX ------------------------------------------------
173 ------------------------------------------------------------------------------------ */
177 /** standard MUX table. if variations, please define MUX_NON_STD in your device specificity */
179 /* lacking configs on some devices :
182 no gain stages : ATM165 ATM169 aTM329 ATM3290 ATM649 ATM6490
183 no gain and no differential stages : ATM48 ATM88 ATM168 ATM8
186 #if ( defined (__AVR_ATmega165__) \
187 || defined (__AVR_ATmega169__) || defined (__AVR_ATmega329__) || defined (__AVR_ATmega3290__) \
188 || defined (__AVR_ATmega649__) || defined (__AVR_ATmega6490__) )
190 # define MUX_NO_GAINS
193 /* we let a bit more in the config, not a problem, this will just set the reserved bit, with no effect */
194 #if ( defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) \
195 || defined (__AVR_ATmega8__) )
197 # define MUX_NO_GAINS
204 /* 0x20 + 0x0-0x7 : individual channel 8 to 15 (ATM640 ATM1280 ATM1281 ATM2561 only !!) */
206 #if ( defined (__AVR_ATmega640__) || defined (__AVR_ATmega1280__) || defined (__AVR_ATmega1281__) \
207 || defined (__AVR_ATmega2561__) || defined (__AVR_ATmega2560__) )
210 # define MUX_ADC8 ((0 <<MUX0) | MUX5_MASK_IN_CONFIG)
211 # define MUX_ADC9 ((1 <<MUX0) | MUX5_MASK_IN_CONFIG)
212 # define MUX_ADC10 ((2 <<MUX0) | MUX5_MASK_IN_CONFIG)
213 # define MUX_ADC11 ((3 <<MUX0) | MUX5_MASK_IN_CONFIG)
214 # define MUX_ADC12 ((4 <<MUX0) | MUX5_MASK_IN_CONFIG)
215 # define MUX_ADC13 ((5 <<MUX0) | MUX5_MASK_IN_CONFIG)
216 # define MUX_ADC14 ((6 <<MUX0) | MUX5_MASK_IN_CONFIG)
217 # define MUX_ADC15 ((7 <<MUX0) | MUX5_MASK_IN_CONFIG)
222 AT30PWM2 &3 : only 4 MUX bits, as follow :
223 0x0 - 0xA : individual channel 0 to 10
229 we let a bit more in the config, not a problem, this will just set the reserved bit, with no effect
231 #if ( defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) \
232 || defined (__AVR_ATmega8__) )
234 # define MUX_NO_GAINS
237 # define MUX_AMP0 (0xB<<MUX0)
238 # define MUX_AMP1 (0xC<<MUX0)
242 /** \todo : finish implmentation fully */
244 ATtiny13 : only 4 inputs, no gain, no diff, no ref voltage
247 0x0 - 0x3 : individual channel
249 0x5 : (ADC2 - ADC2) *20
251 0x7 : (ADC2 - ADC3) *20
253 ATtiny24-44-84 : different table, not implemented yet
254 ATtiny25-45-85 : different table, not implemented yet
255 ATtiny26 : different table, not implemented yet
256 ATUSBxxx : different gains not implemanted yet, diffs available
259 yet these devices generate a warning, and select the default table, limited to 8 inputs
263 #if ( defined (__AVR_ATtiny13__) || defined (__AVR_ATtiny15__) \
264 || defined (__AVR_ATtiny24__) || defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) \
265 || defined (__AVR_ATtiny25__) || defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) \
266 || defined (__AVR_ATtiny26__) \
267 || defined (__AVR_AT90USB1286__) || defined (__AVR_AT90USB1287__) \
268 || defined (__AVR_AT90USB646__) || defined (__AVR_AT90USB647__) )
270 # warning The ADC MUX table of your device is not fully defined, some inputs could not work correctly, see adc_archs.h
272 # define MUX_NO_GAINS
280 currently implemented STD table is following :
283 0x0 - 0x7 : individual channel
285 01000 : (ADC0 - ADC0) * 10
286 01001 : (ADC1 - ADC0) * 10
287 01010 : (ADC0 - ADC0) * 200
288 01011 : (ADC1 - ADC0) * 200
290 01100 : (ADC2 - ADC2) * 10
291 01101 : (ADC3 - ADC2) * 10
292 01110 : (ADC2 - ADC2) * 200
293 01111 : (ADC3 - ADC2) * 200
295 10000 + 0x0-0x7 : ADCx - ADC1
296 11000 + 0x0-0x5 : ADCx - ADC2
298 0x1E : internal VBG reference (1.22V)
306 # define MUX_ADC0 (0 <<MUX0)
307 # define MUX_ADC1 (1 <<MUX0)
308 # define MUX_ADC2 (2 <<MUX0)
309 # define MUX_ADC3 (3 <<MUX0)
310 # define MUX_ADC4 (4 <<MUX0)
311 # define MUX_ADC5 (5 <<MUX0)
312 # define MUX_ADC6 (6 <<MUX0)
313 # define MUX_ADC7 (7 <<MUX0)
315 # ifndef MUX_NO_GAINS
316 # define MUX_ADC0_ADC0_GAIN10 ((0x8 <<MUX0) | ADC_RESULT_SIGNED ) /* specifies that the result is in signed mode */
317 # define MUX_ADC1_ADC0_GAIN10 ((0x9 <<MUX0) | ADC_RESULT_SIGNED )
318 # define MUX_ADC0_ADC0_GAIN200 ((0xA <<MUX0) | ADC_RESULT_SIGNED )
319 # define MUX_ADC1_ADC0_GAIN200 ((0xB <<MUX0) | ADC_RESULT_SIGNED )
321 # define MUX_ADC2_ADC2_GAIN10 ((0xC <<MUX0) | ADC_RESULT_SIGNED )
322 # define MUX_ADC3_ADC2_GAIN10 ((0xD <<MUX0) | ADC_RESULT_SIGNED )
323 # define MUX_ADC2_ADC2_GAIN200 ((0xE <<MUX0) | ADC_RESULT_SIGNED )
324 # define MUX_ADC3_ADC2_GAIN200 ((0xF <<MUX0) | ADC_RESULT_SIGNED )
325 # endif // MUX_NO_GAINS
328 # define MUX_ADC0_ADC1 ((0x10 <<MUX0) | ADC_RESULT_SIGNED )
329 # define MUX_ADC1_ADC1 ((0x11 <<MUX0) | ADC_RESULT_SIGNED )
330 # define MUX_ADC2_ADC1 ((0x12 <<MUX0) | ADC_RESULT_SIGNED )
331 # define MUX_ADC3_ADC1 ((0x13 <<MUX0) | ADC_RESULT_SIGNED )
332 # define MUX_ADC4_ADC1 ((0x14 <<MUX0) | ADC_RESULT_SIGNED )
333 # define MUX_ADC5_ADC1 ((0x15 <<MUX0) | ADC_RESULT_SIGNED )
334 # define MUX_ADC6_ADC1 ((0x16 <<MUX0) | ADC_RESULT_SIGNED )
335 # define MUX_ADC7_ADC1 ((0x17 <<MUX0) | ADC_RESULT_SIGNED )
337 # define MUX_ADC0_ADC2 ((0x18 <<MUX0) | ADC_RESULT_SIGNED )
338 # define MUX_ADC1_ADC2 ((0x19 <<MUX0) | ADC_RESULT_SIGNED )
339 # define MUX_ADC2_ADC2 ((0x1A <<MUX0) | ADC_RESULT_SIGNED )
340 # define MUX_ADC3_ADC2 ((0x1B <<MUX0) | ADC_RESULT_SIGNED )
341 # define MUX_ADC4_ADC2 ((0x1C <<MUX0) | ADC_RESULT_SIGNED )
342 # define MUX_ADC5_ADC2 ((0x1D <<MUX0) | ADC_RESULT_SIGNED )
343 # define MUX_ADC6_ADC2 ((0x1E <<MUX0) | ADC_RESULT_SIGNED )
344 # define MUX_ADC7_ADC2 ((0x1F <<MUX0) | ADC_RESULT_SIGNED )
345 # endif // MUX_NO_DIFF
348 # define MUX_VBG (0x1E <<MUX0)
349 # define MUX_GND (0x1F <<MUX0)
351 # define MUX_VBG ((0x1E <<MUX0) | MUX5_MASK_IN_CONFIG)
352 # define MUX_GND ((0x1F <<MUX0) | MUX5_MASK_IN_CONFIG)
355 #endif // MUX_NON_STD
360 /* ------------------------------------------------------------------------------------
361 ---------------------------- PRESCALER -----------------------------------------
362 ------------------------------------------------------------------------------------ */
377 This table is yet totally standard
378 the selection is based on the quartz frequency, given in autoconf.h
382 #include <autoconf.h>
384 #if ( CONFIG_QUARTZ < 100000l)
385 # warning your clock is too slow, the ADC result is not guaranted
388 #if (CONFIG_QUARTZ <= 400000l) // up to 400 kHz : PS = 2
389 # define ADC_PRESCALE 0
390 #elif (CONFIG_QUARTZ <= 800000l) // up to 800 kHz : PS = 4
391 # define ADC_PRESCALE 2
392 #elif (CONFIG_QUARTZ <= 1600000l) // up to 1.6 MHz : PS = 8
393 # define ADC_PRESCALE 3
394 #elif (CONFIG_QUARTZ <= 3200000l) // up to 3.2 MHz : PS = 16
395 # define ADC_PRESCALE 4
396 #elif (CONFIG_QUARTZ <= 6400000l) // up to 6.4 MHz : PS = 32
397 # define ADC_PRESCALE 5
398 #elif (CONFIG_QUARTZ <= 12800000l) // up to 12.8 MHz : PS = 64
399 # define ADC_PRESCALE 6
400 #elif ( CONFIG_QUARTZ <= 25600000l) // up to 25.6 MHz : PS = 128
401 # define ADC_PRESCALE 7
403 # define ADC_PRESCALE 7
404 # warning your clock is too fast, the ADC result is not guaranted
412 #endif // _ADC_ARCHS_