4 USE IEEE.STD_LOGIC_1164.ALL;
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5 USE ieee.numeric_std.ALL;
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7 --USE IEEE.STD_LOGIC_ARITH.ALL;
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8 --USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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11 PORT ( CLK : IN std_logic;
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12 sortie : OUT unsigned(7 DOWNTO 0);
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14 SEL : IN unsigned(1 DOWNTO 0);
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15 TX_bus : OUT std_logic;
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16 RX_bus : IN std_logic;
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17 TX_avr : IN std_logic;
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18 RX_avr : OUT std_logic;
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20 AB0 : IN unsigned(1 DOWNTO 0);
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21 AB1 : IN unsigned(1 DOWNTO 0);
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27 -- MASSE : std_logic
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33 ATTRIBUTE pin_assign : string;
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34 ATTRIBUTE pin_assign OF CLK : SIGNAL IS "7"; --clock
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35 ATTRIBUTE pin_assign OF sortie : SIGNAL IS "11 12 9 8 6 5 4 3 "; --data 0
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39 ATTRIBUTE pin_assign OF AB0 : SIGNAL IS "27 26"; --cod_d0
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40 ATTRIBUTE pin_assign OF AB1 : SIGNAL IS "25 29"; --cod_g0
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41 ATTRIBUTE pin_assign OF RX_bus : SIGNAL IS "19"; --rx_bus
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42 ATTRIBUTE pin_assign OF TX_bus : SIGNAL IS "22"; --tx_bus
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43 ATTRIBUTE pin_assign OF RX_avr : SIGNAL IS "14"; --rx_avr
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44 ATTRIBUTE pin_assign OF TX_avr : SIGNAL IS "13"; --tx_avr
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45 ATTRIBUTE pin_assign OF SEL : SIGNAL IS "1 44"; -- il reste data2 qui est inutilise
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46 -- ATTRIBUTE pin_assign OF MASSE : SIGNAL IS " 43";
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54 ARCHITECTURE Behavioral OF carte1 IS
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56 -- 1 traitement de codeur
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58 GENERIC (Nb_bascules : natural);
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59 PORT ( AB : IN unsigned(1 DOWNTO 0);
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60 cpt : OUT unsigned(7 DOWNTO 0);
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61 clk : IN std_ulogic;
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67 SIGNAL sortie0 : unsigned(7 DOWNTO 0);
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68 SIGNAL sortie1 : unsigned(7 DOWNTO 0);
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72 use entity work.compteur(Behavioral);
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82 GENERIC MAP (Nb_bascules => 1)
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83 PORT MAP ( AB => AB0, cpt => sortie0, clk => CLK , INV => '0' );
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87 GENERIC MAP (Nb_bascules => 1)
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88 PORT MAP ( AB => AB1, cpt => sortie1, clk => CLK, INV => '1' );
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91 MUX: PROCESS (SEL, sortie0, sortie1, sortie2, sortie3)
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92 BEGIN -- PROCESS MUX
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94 WHEN "00" => sortie <= sortie0;
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95 WHEN "01" => sortie <= sortie1;
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98 WHEN OTHERS => sortie <= (OTHERS => 'Z');
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104 UART : PROCESS (TX_avr,RX_bus)
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105 BEGIN -- PROCESS UART
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