CONFIG_RTE_MACHINE="dpaa2"
CONFIG_RTE_ARCH_ARM_TUNE="cortex-a72"
-#
-# Compile Environment Abstraction Layer
-#
CONFIG_RTE_MAX_LCORE=16
CONFIG_RTE_MAX_NUMA_NODES=1
CONFIG_RTE_CACHE_LINE_SIZE=64
-CONFIG_RTE_PKTMBUF_HEADROOM=256
+CONFIG_RTE_PKTMBUF_HEADROOM=128
# Doesn't support NUMA
CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
CONFIG_RTE_LIBRTE_VHOST_NUMA=n
-#
-# Compile Support Libraries for DPAA2
-#
-CONFIG_RTE_LIBRTE_DPAA2_MEMPOOL=y
-CONFIG_RTE_MBUF_DEFAULT_MEMPOOL_OPS="dpaa2"
CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=n
-
-#
-# Compile NXP DPAA2 FSL-MC Bus
-#
-CONFIG_RTE_LIBRTE_FSLMC_BUS=y
-
-#
-# Compile burst-oriented NXP DPAA2 PMD driver
-#
-CONFIG_RTE_LIBRTE_DPAA2_PMD=y
-CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT=n
-CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n
-CONFIG_RTE_LIBRTE_DPAA2_DEBUG_RX=n
-CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX=n
-CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX_FREE=n
-
-#
-# Compile NXP DPAA2 crypto sec driver for CAAM HW
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y
-CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n
-CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n
-CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n
-
-#
-# Number of sessions to create in the session memory pool
-# on a single DPAA2 SEC device.
-#
-CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048
-
-#
-# Compile schedule-oriented NXP DPAA2 EVENTDEV driver
-#
-CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y