#include <rte_alarm.h>
#include "bnxt.h"
-#include "bnxt_cpr.h"
#include "bnxt_filter.h"
#include "bnxt_hwrm.h"
#include "bnxt_irq.h"
#include "bnxt_vnic.h"
#include "hsi_struct_def_dpdk.h"
#include "bnxt_nvm_defs.h"
-#include "bnxt_util.h"
#define DRV_MODULE_NAME "bnxt"
static const char bnxt_version[] =
"Broadcom NetXtreme driver " DRV_MODULE_NAME;
int bnxt_logtype_driver;
-#define PCI_VENDOR_ID_BROADCOM 0x14E4
-
-#define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606
-#define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609
-#define BROADCOM_DEV_ID_STRATUS_NIC 0x1614
-#define BROADCOM_DEV_ID_57414_VF 0x16c1
-#define BROADCOM_DEV_ID_57301 0x16c8
-#define BROADCOM_DEV_ID_57302 0x16c9
-#define BROADCOM_DEV_ID_57304_PF 0x16ca
-#define BROADCOM_DEV_ID_57304_VF 0x16cb
-#define BROADCOM_DEV_ID_57417_MF 0x16cc
-#define BROADCOM_DEV_ID_NS2 0x16cd
-#define BROADCOM_DEV_ID_57311 0x16ce
-#define BROADCOM_DEV_ID_57312 0x16cf
-#define BROADCOM_DEV_ID_57402 0x16d0
-#define BROADCOM_DEV_ID_57404 0x16d1
-#define BROADCOM_DEV_ID_57406_PF 0x16d2
-#define BROADCOM_DEV_ID_57406_VF 0x16d3
-#define BROADCOM_DEV_ID_57402_MF 0x16d4
-#define BROADCOM_DEV_ID_57407_RJ45 0x16d5
-#define BROADCOM_DEV_ID_57412 0x16d6
-#define BROADCOM_DEV_ID_57414 0x16d7
-#define BROADCOM_DEV_ID_57416_RJ45 0x16d8
-#define BROADCOM_DEV_ID_57417_RJ45 0x16d9
-#define BROADCOM_DEV_ID_5741X_VF 0x16dc
-#define BROADCOM_DEV_ID_57412_MF 0x16de
-#define BROADCOM_DEV_ID_57314 0x16df
-#define BROADCOM_DEV_ID_57317_RJ45 0x16e0
-#define BROADCOM_DEV_ID_5731X_VF 0x16e1
-#define BROADCOM_DEV_ID_57417_SFP 0x16e2
-#define BROADCOM_DEV_ID_57416_SFP 0x16e3
-#define BROADCOM_DEV_ID_57317_SFP 0x16e4
-#define BROADCOM_DEV_ID_57404_MF 0x16e7
-#define BROADCOM_DEV_ID_57406_MF 0x16e8
-#define BROADCOM_DEV_ID_57407_SFP 0x16e9
-#define BROADCOM_DEV_ID_57407_MF 0x16ea
-#define BROADCOM_DEV_ID_57414_MF 0x16ec
-#define BROADCOM_DEV_ID_57416_MF 0x16ee
-#define BROADCOM_DEV_ID_57508 0x1750
-#define BROADCOM_DEV_ID_57504 0x1751
-#define BROADCOM_DEV_ID_57502 0x1752
-#define BROADCOM_DEV_ID_57500_VF1 0x1806
-#define BROADCOM_DEV_ID_57500_VF2 0x1807
-#define BROADCOM_DEV_ID_58802 0xd802
-#define BROADCOM_DEV_ID_58804 0xd804
-#define BROADCOM_DEV_ID_58808 0x16f0
-#define BROADCOM_DEV_ID_58802_VF 0xd800
-
+/*
+ * The set of PCI devices this driver supports
+ */
static const struct rte_pci_id bnxt_pci_id_map[] = {
{ RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM,
BROADCOM_DEV_ID_STRATUS_NIC_VF1) },
DEV_TX_OFFLOAD_GRE_TNL_TSO | \
DEV_TX_OFFLOAD_IPIP_TNL_TSO | \
DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \
+ DEV_TX_OFFLOAD_QINQ_INSERT | \
DEV_TX_OFFLOAD_MULTI_SEGS)
#define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \
DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \
DEV_RX_OFFLOAD_JUMBO_FRAME | \
DEV_RX_OFFLOAD_KEEP_CRC | \
- DEV_RX_OFFLOAD_TCP_LRO)
+ DEV_RX_OFFLOAD_VLAN_EXTEND | \
+ DEV_RX_OFFLOAD_TCP_LRO | \
+ DEV_RX_OFFLOAD_SCATTER)
static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask);
static void bnxt_print_link_info(struct rte_eth_dev *eth_dev);
static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev);
static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev);
static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev);
+static void bnxt_cancel_fw_health_check(struct bnxt *bp);
int is_bnxt_in_error(struct bnxt *bp)
{
* High level utility functions
*/
-static uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
+uint16_t bnxt_rss_ctxts(const struct bnxt *bp)
{
if (!BNXT_CHIP_THOR(bp))
return 1;
bnxt_free_rx_rings(bp);
}
bnxt_free_async_cp_ring(bp);
+ bnxt_free_rxtx_nq_ring(bp);
}
static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig)
if (rc)
goto alloc_mem_err;
+ rc = bnxt_alloc_rxtx_nq_ring(bp);
+ if (rc)
+ goto alloc_mem_err;
+
return 0;
alloc_mem_err:
goto err_out;
}
+ if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY))
+ goto skip_cosq_cfg;
+
+ for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) {
+ if (bp->rx_cos_queue[i].id != 0xff) {
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[j++];
+
+ if (!vnic) {
+ PMD_DRV_LOG(ERR,
+ "Num pools more than FW profile\n");
+ rc = -EINVAL;
+ goto err_out;
+ }
+ vnic->cos_queue_id = bp->rx_cos_queue[i].id;
+ bp->rx_cosq_cnt++;
+ }
+ }
+
+skip_cosq_cfg:
rc = bnxt_mq_rx_configure(bp);
if (rc) {
PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc);
for (i = 0; i < bp->nr_vnics; i++) {
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
- uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps;
- vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0);
- if (!vnic->fw_grp_ids) {
- PMD_DRV_LOG(ERR,
- "Failed to alloc %d bytes for group ids\n",
- size);
- rc = -ENOMEM;
+ rc = bnxt_vnic_grp_alloc(bp, vnic);
+ if (rc)
goto err_out;
- }
- memset(vnic->fw_grp_ids, -1, size);
PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n",
i, vnic, vnic->fw_grp_ids);
goto err_out;
}
- for (j = 0; j < bp->rx_nr_rings; j++) {
+ for (j = 0; j < bp->rx_num_qs_per_vnic; j++) {
rxq = bp->eth_dev->data->rx_queues[j];
PMD_DRV_LOG(DEBUG,
static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_info *dev_info)
{
+ struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device);
struct bnxt *bp = eth_dev->data->dev_private;
uint16_t max_vnics, i, j, vpool, vrxq;
unsigned int max_rx_rings;
/* PF/VF specifics */
if (BNXT_PF(bp))
- dev_info->max_vfs = bp->pdev->max_vfs;
+ dev_info->max_vfs = pdev->max_vfs;
+
max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx);
/* For the sake of symmetry, max_rx_queues = max_tx_queues */
dev_info->max_rx_queues = max_rx_rings;
dev_info->hash_key_size = 40;
max_vnics = bp->max_vnics;
+ /* MTU specifics */
+ dev_info->min_mtu = RTE_ETHER_MIN_MTU;
+ dev_info->max_mtu = BNXT_MAX_MTU;
+
/* Fast path specifics */
dev_info->min_rx_bufsize = 1;
- dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN +
- RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
+ dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN;
dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT;
if (bp->flags & BNXT_FLAG_PTP_SUPPORTED)
return -ENOSPC;
}
+ /* If a resource has already been allocated - in this case
+ * it is the async completion ring, free it. Reallocate it after
+ * resource reservation. This will ensure the resource counts
+ * are calculated correctly.
+ */
+
+ pthread_mutex_lock(&bp->def_cp_lock);
+
+ if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
+ bnxt_disable_int(bp);
+ bnxt_free_cp_ring(bp, bp->async_cp_ring);
+ }
+
rc = bnxt_hwrm_func_reserve_vf_resc(bp, false);
if (rc) {
PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc);
+ pthread_mutex_unlock(&bp->def_cp_lock);
return -ENOSPC;
}
+
+ if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) {
+ rc = bnxt_alloc_async_cp_ring(bp);
+ if (rc) {
+ pthread_mutex_unlock(&bp->def_cp_lock);
+ return rc;
+ }
+ bnxt_enable_int(bp);
+ }
+
+ pthread_mutex_unlock(&bp->def_cp_lock);
} else {
/* legacy driver needs to get updated values */
rc = bnxt_hwrm_func_qcaps(bp);
uint16_t buf_size;
int i;
+ if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER)
+ return 1;
+
for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
{
#ifdef RTE_ARCH_X86
+#ifndef RTE_LIBRTE_IEEE1588
/*
* Vector mode receive can be enabled only if scatter rx is not
* in use and rx offloads are limited to VLAN stripping and
eth_dev->data->port_id,
eth_dev->data->scattered_rx,
eth_dev->data->dev_conf.rxmode.offloads);
+#endif
#endif
return bnxt_recv_pkts;
}
bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
{
#ifdef RTE_ARCH_X86
+#ifndef RTE_LIBRTE_IEEE1588
/*
* Vector mode transmit can be enabled only if not using scatter rx
* or tx offloads.
eth_dev->data->port_id,
eth_dev->data->scattered_rx,
eth_dev->data->dev_conf.txmode.offloads);
+#endif
#endif
return bnxt_xmit_pkts;
}
return rc;
}
}
+ bnxt_enable_int(bp);
rc = bnxt_init_chip(bp);
if (rc)
eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
- bnxt_enable_int(bp);
bp->flags |= BNXT_FLAG_INIT_DONE;
eth_dev->data->dev_started = 1;
bp->dev_stopped = 0;
+ bnxt_schedule_fw_health_check(bp);
return 0;
error:
eth_dev->data->dev_link.link_status = 1;
bnxt_print_link_info(eth_dev);
- return 0;
+ return rc;
}
static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev)
/* disable uio/vfio intr/eventfd mapping */
rte_intr_disable(intr_handle);
+ bnxt_cancel_fw_health_check(bp);
+
bp->flags &= ~BNXT_FLAG_INIT_DONE;
if (bp->eth_dev->data->dev_started) {
/* TBD: STOP HW queues DMA */
eth_dev->data->dev_link.link_status = 0;
}
- bnxt_set_hwrm_link_config(bp, false);
+ bnxt_dev_set_link_down_op(eth_dev);
+
+ /* Wait for link to be reset and the async notification to process.
+ * During reset recovery, there is no need to wait
+ */
+ if (!is_bnxt_in_error(bp))
+ rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2);
/* Clean queue intr-vector mapping */
rte_intr_efd_disable(intr_handle);
bnxt_hwrm_port_clr_stats(bp);
bnxt_free_tx_mbufs(bp);
bnxt_free_rx_mbufs(bp);
+ /* Process any remaining notifications in default completion queue */
+ bnxt_int_handler(eth_dev);
bnxt_shutdown_nic(bp);
bnxt_hwrm_if_change(bp, 0);
bp->dev_stopped = 1;
}
}
+static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic,
+ struct rte_ether_addr *mac_addr, uint32_t index)
+{
+ struct bnxt_filter_info *filter;
+ int rc = 0;
+
+ filter = STAILQ_FIRST(&vnic->filter);
+ /* During bnxt_mac_addr_add_op, default MAC is
+ * already programmed, so skip it. But, when
+ * hw-vlan-filter is turned OFF from ON, default
+ * MAC filter should be restored
+ */
+ if (index == 0 && filter->dflt)
+ return 0;
+
+ filter = bnxt_alloc_filter(bp);
+ if (!filter) {
+ PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
+ return -ENODEV;
+ }
+
+ filter->mac_index = index;
+ /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So,
+ * if the MAC that's been programmed now is a different one, then,
+ * copy that addr to filter->l2_addr
+ */
+ if (mac_addr)
+ memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
+ filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
+
+ rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
+ if (!rc) {
+ if (filter->mac_index == 0) {
+ filter->dflt = true;
+ STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
+ } else {
+ STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
+ }
+ } else {
+ filter->mac_index = INVALID_MAC_INDEX;
+ memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
+ bnxt_free_filter(bp, filter);
+ }
+
+ return rc;
+}
+
static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev,
struct rte_ether_addr *mac_addr,
uint32_t index, uint32_t pool)
return 0;
}
}
- filter = bnxt_alloc_filter(bp);
- if (!filter) {
- PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
- return -ENODEV;
- }
- filter->mac_index = index;
- memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN);
-
- rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
- if (!rc) {
- STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
- } else {
- filter->mac_index = INVALID_MAC_INDEX;
- memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN);
- bnxt_free_filter(bp, filter);
- }
+ rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index);
return rc;
}
/* Timed out or success */
if (new.link_status != eth_dev->data->dev_link.link_status ||
new.link_speed != eth_dev->data->dev_link.link_speed) {
- memcpy(ð_dev->data->dev_link, &new,
- sizeof(struct rte_eth_link));
+ rte_eth_linkstatus_set(eth_dev, &new);
_rte_eth_dev_callback_process(eth_dev,
RTE_ETH_EVENT_INTR_LSC,
if (bp->vnic_info == NULL)
return 0;
- vnic = &bp->vnic_info[0];
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_PROMISC;
if (bp->vnic_info == NULL)
return 0;
- vnic = &bp->vnic_info[0];
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
old_flags = vnic->flags;
vnic->flags &= ~BNXT_VNIC_INFO_PROMISC;
if (bp->vnic_info == NULL)
return 0;
- vnic = &bp->vnic_info[0];
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
old_flags = vnic->flags;
vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
if (bp->vnic_info == NULL)
return 0;
- vnic = &bp->vnic_info[0];
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
old_flags = vnic->flags;
vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI;
vnic->rss_table[i] =
vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
-
- vnic->rss_table[i] =
- vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
bnxt_hwrm_vnic_rss_cfg(bp, vnic);
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_vnic_info *vnic;
- uint16_t hash_type = 0;
- unsigned int i;
int rc;
rc = is_bnxt_in_error(bp);
bp->flags |= BNXT_FLAG_UPDATE_HASH;
memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf));
- if (rss_conf->rss_hf & ETH_RSS_IPV4)
- hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4;
- if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
- hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4;
- if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
- hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4;
- if (rss_conf->rss_hf & ETH_RSS_IPV6)
- hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6;
- if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
- hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6;
- if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
- hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6;
-
- /* Update the RSS VNIC(s) */
- for (i = 0; i < bp->nr_vnics; i++) {
- vnic = &bp->vnic_info[i];
- vnic->hash_type = hash_type;
+ /* Update the default RSS VNIC(s) */
+ vnic = &bp->vnic_info[0];
+ vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf);
- /*
- * Use the supplied key if the key length is
- * acceptable and the rss_key is not NULL
- */
- if (rss_conf->rss_key &&
- rss_conf->rss_key_len <= HW_HASH_KEY_SIZE)
- memcpy(vnic->rss_hash_key, rss_conf->rss_key,
- rss_conf->rss_key_len);
+ /*
+ * If hashkey is not specified, use the previously configured
+ * hashkey
+ */
+ if (!rss_conf->rss_key)
+ goto rss_config;
- bnxt_hwrm_vnic_rss_cfg(bp, vnic);
+ if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) {
+ PMD_DRV_LOG(ERR,
+ "Invalid hashkey length, should be 16 bytes\n");
+ return -EINVAL;
}
+ memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len);
+
+rss_config:
+ bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
filter = STAILQ_FIRST(&vnic->filter);
while (filter) {
/* Search for this matching MAC+VLAN filter */
- if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
- !memcmp(filter->l2_addr,
- bp->mac_addr,
+ if ((filter->enables & chk) &&
+ (filter->l2_ivlan == vlan_id &&
+ filter->l2_ivlan_mask != 0) &&
+ !memcmp(filter->l2_addr, bp->mac_addr,
RTE_ETHER_ADDR_LEN)) {
/* Delete the filter */
rc = bnxt_hwrm_clear_l2_filter(bp, filter);
filter = STAILQ_FIRST(&vnic->filter);
/* Check if the VLAN has already been added */
while (filter) {
- if (filter->enables & chk && filter->l2_ivlan == vlan_id &&
- !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN))
+ if ((filter->enables & chk) &&
+ (filter->l2_ivlan == vlan_id &&
+ filter->l2_ivlan_mask == 0x0FFF) &&
+ !memcmp(filter->l2_addr, bp->mac_addr,
+ RTE_ETHER_ADDR_LEN))
return -EEXIST;
filter = STAILQ_NEXT(filter, next);
return -ENOMEM;
}
/* MAC + VLAN ID filter */
+ /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only
+ * untagged packets are received
+ *
+ * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged
+ * packets and only the programmed vlan's packets are received
+ */
filter->l2_ivlan = vlan_id;
filter->l2_ivlan_mask = 0x0FFF;
filter->enables |= en;
+ filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
+
rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
if (rc) {
/* Free the newly allocated filter as we were
filter->fw_l2_filter_id = UINT64_MAX;
STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next);
return rc;
+ } else {
+ /* Add this new filter to the list */
+ if (vlan_id == 0) {
+ filter->dflt = true;
+ STAILQ_INSERT_HEAD(&vnic->filter, filter, next);
+ } else {
+ STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
+ }
}
- /* Add this new filter to the list */
- STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
PMD_DRV_LOG(INFO,
"Added Vlan filter for %d\n", vlan_id);
return rc;
return bnxt_del_vlan_filter(bp, vlan_id);
}
+static int bnxt_del_dflt_mac_filter(struct bnxt *bp,
+ struct bnxt_vnic_info *vnic)
+{
+ struct bnxt_filter_info *filter;
+ int rc;
+
+ filter = STAILQ_FIRST(&vnic->filter);
+ while (filter) {
+ if (filter->dflt &&
+ !memcmp(filter->l2_addr, bp->mac_addr,
+ RTE_ETHER_ADDR_LEN)) {
+ rc = bnxt_hwrm_clear_l2_filter(bp, filter);
+ if (rc)
+ return rc;
+ filter->dflt = false;
+ STAILQ_REMOVE(&vnic->filter, filter,
+ bnxt_filter_info, next);
+ STAILQ_INSERT_TAIL(&bp->free_filter_list,
+ filter, next);
+ filter->fw_l2_filter_id = -1;
+ break;
+ }
+ filter = STAILQ_NEXT(filter, next);
+ }
+ return 0;
+}
+
static int
bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask)
{
struct bnxt *bp = dev->data->dev_private;
uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
+ struct bnxt_vnic_info *vnic;
unsigned int i;
int rc;
if (rc)
return rc;
- if (mask & ETH_VLAN_FILTER_MASK) {
- if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
- /* Remove any VLAN filters programmed */
- for (i = 0; i < 4095; i++)
- bnxt_del_vlan_filter(bp, i);
- }
- PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
- !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
+ if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) {
+ /* Remove any VLAN filters programmed */
+ for (i = 0; i < 4095; i++)
+ bnxt_del_vlan_filter(bp, i);
+
+ rc = bnxt_add_mac_filter(bp, vnic, NULL, 0);
+ if (rc)
+ return rc;
+ } else {
+ /* Default filter will allow packets that match the
+ * dest mac. So, it has to be deleted, otherwise, we
+ * will endup receiving vlan packets for which the
+ * filter is not programmed, when hw-vlan-filter
+ * configuration is ON
+ */
+ bnxt_del_dflt_mac_filter(bp, vnic);
+ /* This filter will allow only untagged packets */
+ bnxt_add_vlan_filter(bp, 0);
}
+ PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n",
+ !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER));
if (mask & ETH_VLAN_STRIP_MASK) {
/* Enable or disable VLAN stripping */
!!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP));
}
- if (mask & ETH_VLAN_EXTEND_MASK)
- PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n");
+ if (mask & ETH_VLAN_EXTEND_MASK) {
+ if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
+ PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n");
+ else
+ PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n");
+ }
+
+ return 0;
+}
+
+static int
+bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
+ uint16_t tpid)
+{
+ struct bnxt *bp = dev->data->dev_private;
+ int qinq = dev->data->dev_conf.rxmode.offloads &
+ DEV_RX_OFFLOAD_VLAN_EXTEND;
+
+ if (vlan_type != ETH_VLAN_TYPE_INNER &&
+ vlan_type != ETH_VLAN_TYPE_OUTER) {
+ PMD_DRV_LOG(ERR,
+ "Unsupported vlan type.");
+ return -EINVAL;
+ }
+ if (!qinq) {
+ PMD_DRV_LOG(ERR,
+ "QinQ not enabled. Needs to be ON as we can "
+ "accelerate only outer vlan\n");
+ return -EINVAL;
+ }
+
+ if (vlan_type == ETH_VLAN_TYPE_OUTER) {
+ switch (tpid) {
+ case RTE_ETHER_TYPE_QINQ:
+ bp->outer_tpid_bd =
+ TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8;
+ break;
+ case RTE_ETHER_TYPE_VLAN:
+ bp->outer_tpid_bd =
+ TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100;
+ break;
+ case 0x9100:
+ bp->outer_tpid_bd =
+ TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100;
+ break;
+ case 0x9200:
+ bp->outer_tpid_bd =
+ TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200;
+ break;
+ case 0x9300:
+ bp->outer_tpid_bd =
+ TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300;
+ break;
+ default:
+ PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid);
+ return -EINVAL;
+ }
+ bp->outer_tpid_bd |= tpid;
+ PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd);
+ } else if (vlan_type == ETH_VLAN_TYPE_INNER) {
+ PMD_DRV_LOG(ERR,
+ "Can accelerate only outer vlan in QinQ\n");
+ return -EINVAL;
+ }
return 0;
}
static int
bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev,
- struct rte_ether_addr *addr)
+ struct rte_ether_addr *addr)
{
struct bnxt *bp = dev->data->dev_private;
/* Default Filter is tied to VNIC 0 */
if (filter->mac_index != 0)
continue;
- memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN);
+ memcpy(filter->l2_addr, addr, RTE_ETHER_ADDR_LEN);
memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN);
- filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX;
+ filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX |
+ HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
filter->enables |=
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR |
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK;
rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter);
- if (rc)
+ if (rc) {
+ memcpy(filter->l2_addr, bp->mac_addr,
+ RTE_ETHER_ADDR_LEN);
return rc;
+ }
memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN);
PMD_DRV_LOG(DEBUG, "Set MAC addr\n");
if (rc)
return rc;
- vnic = &bp->vnic_info[0];
+ vnic = BNXT_GET_DEFAULT_VNIC(bp);
if (nb_mc_addr > BNXT_MAX_MC_ADDRS) {
vnic->flags |= BNXT_VNIC_INFO_ALLMULTI;
}
vnic->mc_addr_cnt = i;
+ if (vnic->mc_addr_cnt)
+ vnic->flags |= BNXT_VNIC_INFO_MCAST;
+ else
+ vnic->flags &= ~BNXT_VNIC_INFO_MCAST;
allmulti:
return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
qinfo->conf.rx_drop_en = 0;
- qinfo->conf.rx_deferred_start = 0;
+ qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
}
static void
static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
struct bnxt *bp = eth_dev->data->dev_private;
- struct rte_eth_dev_info dev_info;
uint32_t new_pkt_size;
uint32_t rc = 0;
uint32_t i;
new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
VLAN_TAG_SIZE * BNXT_NUM_VLANS;
- rc = bnxt_dev_info_get_op(eth_dev, &dev_info);
- if (rc != 0) {
- PMD_DRV_LOG(ERR, "Error during getting ethernet device info\n");
- return rc;
- }
-
- if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
- PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n",
- RTE_ETHER_MIN_MTU, BNXT_MAX_MTU);
- return -EINVAL;
- }
-
#ifdef RTE_ARCH_X86
/*
* If vector-mode tx/rx is active, disallow any MTU change that would
eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
- eth_dev->data->mtu = new_mtu;
- PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
-
for (i = 0; i < bp->nr_vnics; i++) {
struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
uint16_t size = 0;
- vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN +
- RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
+ vnic->mru = BNXT_VNIC_MRU(new_mtu);
rc = bnxt_hwrm_vnic_cfg(bp, vnic);
if (rc)
break;
}
}
+ PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu);
+
return rc;
}
struct bnxt_cp_ring_info *cpr;
struct bnxt_rx_queue *rxq;
struct rx_pkt_cmpl *rxcmp;
- uint16_t cmp_type;
- uint8_t cmp = 1;
- bool valid;
int rc;
rc = is_bnxt_in_error(bp);
rxq = dev->data->rx_queues[rx_queue_id];
cpr = rxq->cp_ring;
- valid = cpr->valid;
+ raw_cons = cpr->cp_raw_cons;
- while (raw_cons < rxq->nb_rx_desc) {
+ while (1) {
cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+ rte_prefetch0(&cpr->cp_desc_ring[cons]);
rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
- if (!CMPL_VALID(rxcmp, valid))
- goto nothing_to_do;
- valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid);
- cmp_type = CMP_TYPE(rxcmp);
- if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) {
- cmp = (rte_le_to_cpu_32(
- ((struct rx_tpa_end_cmpl *)
- (rxcmp))->agg_bufs_v1) &
- RX_TPA_END_CMPL_AGG_BUFS_MASK) >>
- RX_TPA_END_CMPL_AGG_BUFS_SFT;
- desc++;
- } else if (cmp_type == 0x11) {
- desc++;
- cmp = (rxcmp->agg_bufs_v1 &
- RX_PKT_CMPL_AGG_BUFS_MASK) >>
- RX_PKT_CMPL_AGG_BUFS_SFT;
+ if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) {
+ break;
} else {
- cmp = 1;
+ raw_cons++;
+ desc++;
}
-nothing_to_do:
- raw_cons += cmp ? cmp : 2;
}
return desc;
return -EINVAL;
}
-
if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
rte_memcpy(filter->dst_macaddr,
fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6);
static int
bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
{
- uint64_t ns, systime_cycles;
struct bnxt *bp = dev->data->dev_private;
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
+ uint64_t ns, systime_cycles = 0;
+ int rc = 0;
if (!ptp)
return 0;
- systime_cycles = bnxt_cc_read(bp);
+ if (BNXT_CHIP_THOR(bp))
+ rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME,
+ &systime_cycles);
+ else
+ systime_cycles = bnxt_cc_read(bp);
+
ns = rte_timecounter_update(&ptp->tc, systime_cycles);
*ts = rte_ns_to_timespec(ns);
- return 0;
+ return rc;
}
static int
bnxt_timesync_enable(struct rte_eth_dev *dev)
struct bnxt *bp = dev->data->dev_private;
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
uint32_t shift = 0;
+ int rc;
if (!ptp)
return 0;
ptp->tx_tstamp_en = 1;
ptp->rxctl = BNXT_PTP_MSG_EVENTS;
- if (!bnxt_hwrm_ptp_cfg(bp))
- bnxt_map_ptp_regs(bp);
+ rc = bnxt_hwrm_ptp_cfg(bp);
+ if (rc)
+ return rc;
memset(&ptp->tc, 0, sizeof(struct rte_timecounter));
memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
ptp->tx_tstamp_tc.cc_shift = shift;
ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
+ if (!BNXT_CHIP_THOR(bp))
+ bnxt_map_ptp_regs(bp);
+
return 0;
}
bnxt_hwrm_ptp_cfg(bp);
- bnxt_unmap_ptp_regs(bp);
+ if (!BNXT_CHIP_THOR(bp))
+ bnxt_unmap_ptp_regs(bp);
return 0;
}
if (!ptp)
return 0;
- bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
+ if (BNXT_CHIP_THOR(bp))
+ rx_tstamp_cycles = ptp->rx_timestamp;
+ else
+ bnxt_get_rx_ts(bp, &rx_tstamp_cycles);
+
ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles);
*timestamp = rte_ns_to_timespec(ns);
return 0;
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
uint64_t tx_tstamp_cycles = 0;
uint64_t ns;
+ int rc = 0;
if (!ptp)
return 0;
- bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
+ if (BNXT_CHIP_THOR(bp))
+ rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX,
+ &tx_tstamp_cycles);
+ else
+ rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles);
+
ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles);
*timestamp = rte_ns_to_timespec(ns);
- return 0;
+ return rc;
}
static int
.udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op,
.vlan_filter_set = bnxt_vlan_filter_set_op,
.vlan_offload_set = bnxt_vlan_offload_set_op,
+ .vlan_tpid_set = bnxt_vlan_tpid_set_op,
.vlan_pvid_set = bnxt_vlan_pvid_set_op,
.mtu_set = bnxt_mtu_set_op,
.mac_addr_set = bnxt_set_default_mac_addr_op,
.timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp,
};
+static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg)
+{
+ uint32_t offset;
+
+ /* Only pre-map the reset GRC registers using window 3 */
+ rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 +
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8);
+
+ offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc);
+
+ return offset;
+}
+
+int bnxt_map_fw_health_status_regs(struct bnxt *bp)
+{
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ uint32_t reg_base = 0xffffffff;
+ int i;
+
+ /* Only pre-map the monitoring GRC registers using window 2 */
+ for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) {
+ uint32_t reg = info->status_regs[i];
+
+ if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC)
+ continue;
+
+ if (reg_base == 0xffffffff)
+ reg_base = reg & 0xfffff000;
+ if ((reg & 0xfffff000) != reg_base)
+ return -ERANGE;
+
+ /* Use mask 0xffc as the Lower 2 bits indicates
+ * address space location
+ */
+ info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE +
+ (reg & 0xffc);
+ }
+
+ if (reg_base == 0xffffffff)
+ return 0;
+
+ rte_write32(reg_base, (uint8_t *)bp->bar0 +
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
+
+ return 0;
+}
+
+static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index)
+{
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ uint32_t delay = info->delay_after_reset[index];
+ uint32_t val = info->reset_reg_val[index];
+ uint32_t reg = info->reset_reg[index];
+ uint32_t type, offset;
+
+ type = BNXT_FW_STATUS_REG_TYPE(reg);
+ offset = BNXT_FW_STATUS_REG_OFF(reg);
+
+ switch (type) {
+ case BNXT_FW_STATUS_REG_TYPE_CFG:
+ rte_pci_write_config(bp->pdev, &val, sizeof(val), offset);
+ break;
+ case BNXT_FW_STATUS_REG_TYPE_GRC:
+ offset = bnxt_map_reset_regs(bp, offset);
+ rte_write32(val, (uint8_t *)bp->bar0 + offset);
+ break;
+ case BNXT_FW_STATUS_REG_TYPE_BAR0:
+ rte_write32(val, (uint8_t *)bp->bar0 + offset);
+ break;
+ }
+ /* wait on a specific interval of time until core reset is complete */
+ if (delay)
+ rte_delay_ms(delay);
+}
+
static void bnxt_dev_cleanup(struct bnxt *bp)
{
bnxt_set_hwrm_link_config(bp, false);
int timeout = bp->fw_reset_max_msecs;
int rc = 0;
+ /* Clear Error flag so that device re-init should happen */
+ bp->flags &= ~BNXT_FLAG_FATAL_ERROR;
+
do {
rc = bnxt_hwrm_ver_get(bp);
if (rc == 0)
bnxt_dev_cleanup(bp);
+ bnxt_wait_for_device_shutdown(bp);
+
rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs,
bnxt_dev_recover, (void *)bp);
if (rc)
PMD_DRV_LOG(ERR, "Error setting recovery alarm");
}
+uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index)
+{
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ uint32_t reg = info->status_regs[index];
+ uint32_t type, offset, val = 0;
+
+ type = BNXT_FW_STATUS_REG_TYPE(reg);
+ offset = BNXT_FW_STATUS_REG_OFF(reg);
+
+ switch (type) {
+ case BNXT_FW_STATUS_REG_TYPE_CFG:
+ rte_pci_read_config(bp->pdev, &val, sizeof(val), offset);
+ break;
+ case BNXT_FW_STATUS_REG_TYPE_GRC:
+ offset = info->mapped_status_regs[index];
+ /* FALLTHROUGH */
+ case BNXT_FW_STATUS_REG_TYPE_BAR0:
+ val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 +
+ offset));
+ break;
+ }
+
+ return val;
+}
+
+static int bnxt_fw_reset_all(struct bnxt *bp)
+{
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ uint32_t i;
+ int rc = 0;
+
+ if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
+ /* Reset through master function driver */
+ for (i = 0; i < info->reg_array_cnt; i++)
+ bnxt_write_fw_reset_reg(bp, i);
+ /* Wait for time specified by FW after triggering reset */
+ rte_delay_ms(info->master_func_wait_period_after_reset);
+ } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) {
+ /* Reset with the help of Kong processor */
+ rc = bnxt_hwrm_fw_reset(bp);
+ if (rc)
+ PMD_DRV_LOG(ERR, "Failed to reset FW\n");
+ }
+
+ return rc;
+}
+
+static void bnxt_fw_reset_cb(void *arg)
+{
+ struct bnxt *bp = arg;
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ int rc = 0;
+
+ /* Only Master function can do FW reset */
+ if (bnxt_is_master_func(bp) &&
+ bnxt_is_recovery_enabled(bp)) {
+ rc = bnxt_fw_reset_all(bp);
+ if (rc) {
+ PMD_DRV_LOG(ERR, "Adapter recovery failed\n");
+ return;
+ }
+ }
+
+ /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send
+ * EXCEPTION_FATAL_ASYNC event to all the functions
+ * (including MASTER FUNC). After receiving this Async, all the active
+ * drivers should treat this case as FW initiated recovery
+ */
+ if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) {
+ bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT;
+ bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT;
+
+ /* To recover from error */
+ rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume,
+ (void *)bp);
+ }
+}
+
+/* Driver should poll FW heartbeat, reset_counter with the frequency
+ * advertised by FW in HWRM_ERROR_RECOVERY_QCFG.
+ * When the driver detects heartbeat stop or change in reset_counter,
+ * it has to trigger a reset to recover from the error condition.
+ * A “master PF” is the function who will have the privilege to
+ * initiate the chimp reset. The master PF will be elected by the
+ * firmware and will be notified through async message.
+ */
+static void bnxt_check_fw_health(void *arg)
+{
+ struct bnxt *bp = arg;
+ struct bnxt_error_recovery_info *info = bp->recovery_info;
+ uint32_t val = 0, wait_msec;
+
+ if (!info || !bnxt_is_recovery_enabled(bp) ||
+ is_bnxt_in_error(bp))
+ return;
+
+ val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG);
+ if (val == info->last_heart_beat)
+ goto reset;
+
+ info->last_heart_beat = val;
+
+ val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG);
+ if (val != info->last_reset_counter)
+ goto reset;
+
+ info->last_reset_counter = val;
+
+ rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq,
+ bnxt_check_fw_health, (void *)bp);
+
+ return;
+reset:
+ /* Stop DMA to/from device */
+ bp->flags |= BNXT_FLAG_FATAL_ERROR;
+ bp->flags |= BNXT_FLAG_FW_RESET;
+
+ PMD_DRV_LOG(ERR, "Detected FW dead condition\n");
+
+ if (bnxt_is_master_func(bp))
+ wait_msec = info->master_func_wait_period;
+ else
+ wait_msec = info->normal_func_wait_period;
+
+ rte_eal_alarm_set(US_PER_MS * wait_msec,
+ bnxt_fw_reset_cb, (void *)bp);
+}
+
+void bnxt_schedule_fw_health_check(struct bnxt *bp)
+{
+ uint32_t polling_freq;
+
+ if (!bnxt_is_recovery_enabled(bp))
+ return;
+
+ if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED)
+ return;
+
+ polling_freq = bp->recovery_info->driver_polling_freq;
+
+ rte_eal_alarm_set(US_PER_MS * polling_freq,
+ bnxt_check_fw_health, (void *)bp);
+ bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
+}
+
+static void bnxt_cancel_fw_health_check(struct bnxt *bp)
+{
+ if (!bnxt_is_recovery_enabled(bp))
+ return;
+
+ rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp);
+ bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED;
+}
+
static bool bnxt_vf_pciid(uint16_t id)
{
if (id == BROADCOM_DEV_ID_57304_VF ||
memset(mz->addr, 0, mz->len);
mz_phys_addr = mz->iova;
if ((unsigned long)mz->addr == mz_phys_addr) {
- PMD_DRV_LOG(WARNING,
- "Memzone physical address same as virtual.\n");
- PMD_DRV_LOG(WARNING,
- "Using rte_mem_virt2iova()\n");
+ PMD_DRV_LOG(DEBUG,
+ "physical address same as virtual\n");
+ PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
mz_phys_addr = rte_mem_virt2iova(mz->addr);
if (mz_phys_addr == RTE_BAD_IOVA) {
PMD_DRV_LOG(ERR,
memset(mz->addr, 0, mz->len);
mz_phys_addr = mz->iova;
if ((unsigned long)mz->addr == mz_phys_addr) {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(DEBUG,
"Memzone physical address same as virtual.\n");
- PMD_DRV_LOG(WARNING,
- "Using rte_mem_virt2iova()\n");
+ PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE)
rte_mem_lock_page(((char *)mz->addr) + sz);
mz_phys_addr = rte_mem_virt2iova(mz->addr);
if (rc)
return rc;
- entries = ctx->qp_max_l2_entries;
+ entries = ctx->qp_max_l2_entries +
+ ctx->vnic_max_vnic_entries +
+ ctx->tqm_min_entries_per_ring;
entries = bnxt_roundup(entries, ctx->tqm_entries_multiple);
entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring,
ctx->tqm_max_entries_per_ring);
memset(mz->addr, 0, mz->len);
mz_phys_addr = mz->iova;
if ((unsigned long)mz->addr == mz_phys_addr) {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(DEBUG,
"Memzone physical address same as virtual.\n");
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(DEBUG,
"Using rte_mem_virt2iova()\n");
mz_phys_addr = rte_mem_virt2iova(mz->addr);
if (mz_phys_addr == RTE_BAD_IOVA) {
memset(mz->addr, 0, mz->len);
mz_phys_addr = mz->iova;
if ((unsigned long)mz->addr == mz_phys_addr) {
- PMD_DRV_LOG(WARNING,
+ PMD_DRV_LOG(DEBUG,
"Memzone physical address same as virtual\n");
- PMD_DRV_LOG(WARNING,
- "Using rte_mem_virt2iova()\n");
+ PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n");
mz_phys_addr = rte_mem_virt2iova(mz->addr);
if (mz_phys_addr == RTE_BAD_IOVA) {
PMD_DRV_LOG(ERR,
if (rc)
return -EIO;
+ rc = bnxt_hwrm_vnic_qcaps(bp);
+ if (rc)
+ return rc;
+
rc = bnxt_hwrm_queue_qportcfg(bp);
if (rc)
return rc;
- /* Get the MAX capabilities for this function */
+ /* Get the MAX capabilities for this function.
+ * This function also allocates context memory for TQM rings and
+ * informs the firmware about this allocated backing store memory.
+ */
rc = bnxt_hwrm_func_qcaps(bp);
if (rc)
return rc;
if (rc)
return rc;
+ rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp);
+ if (rc)
+ return rc;
+
+ /* Get the adapter error recovery support info */
+ rc = bnxt_hwrm_error_recovery_qcfg(bp);
+ if (rc)
+ bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY;
+
if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU &&
mtu != bp->eth_dev->data->mtu)
bp->eth_dev->data->mtu = mtu;
return 0;
}
+static int
+bnxt_init_locks(struct bnxt *bp)
+{
+ int err;
+
+ err = pthread_mutex_init(&bp->flow_lock, NULL);
+ if (err) {
+ PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n");
+ return err;
+ }
+
+ err = pthread_mutex_init(&bp->def_cp_lock, NULL);
+ if (err)
+ PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n");
+ return err;
+}
+
static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev)
{
int rc;
if (rc)
return rc;
+ rc = bnxt_init_locks(bp);
+ if (rc)
+ return rc;
+
return 0;
}
if (version_printed++ == 0)
PMD_DRV_LOG(INFO, "%s\n", bnxt_version);
- rte_eth_copy_pci_info(eth_dev, pci_dev);
-
- bp = eth_dev->data->dev_private;
-
- bp->dev_stopped = 1;
-
eth_dev->dev_ops = &bnxt_dev_ops;
eth_dev->rx_pkt_burst = &bnxt_recv_pkts;
eth_dev->tx_pkt_burst = &bnxt_xmit_pkts;
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
+ rte_eth_copy_pci_info(eth_dev, pci_dev);
+
+ bp = eth_dev->data->dev_private;
+
+ bp->dev_stopped = 1;
+
if (bnxt_vf_pciid(pci_dev->id.device_id))
bp->flags |= BNXT_FLAG_VF;
return rc;
}
+static void
+bnxt_uninit_locks(struct bnxt *bp)
+{
+ pthread_mutex_destroy(&bp->flow_lock);
+ pthread_mutex_destroy(&bp->def_cp_lock);
+}
+
static int
bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev)
{
int rc;
- bnxt_disable_int(bp);
bnxt_free_int(bp);
bnxt_free_mem(bp, reconfig_dev);
bnxt_hwrm_func_buf_unrgtr(bp);
rc = bnxt_hwrm_func_driver_unregister(bp, 0);
bp->flags &= ~BNXT_FLAG_REGISTERED;
bnxt_free_ctx_mem(bp);
- if (!reconfig_dev)
+ if (!reconfig_dev) {
bnxt_free_hwrm_resources(bp);
+ if (bp->recovery_info != NULL) {
+ rte_free(bp->recovery_info);
+ bp->recovery_info = NULL;
+ }
+ }
+
+ rte_free(bp->ptp_cfg);
+ bp->ptp_cfg = NULL;
return rc;
}
eth_dev->rx_pkt_burst = NULL;
eth_dev->tx_pkt_burst = NULL;
+ bnxt_uninit_locks(bp);
+
return rc;
}