*/
#define EF10_NVRAM_CHUNK 0x80
-/* Alignment requirement for value written to RX WPTR:
- * the WPTR must be aligned to an 8 descriptor boundary
+/*
+ * Alignment requirement for value written to RX WPTR: the WPTR must be aligned
+ * to an 8 descriptor boundary.
*/
#define EF10_RX_WPTR_ALIGN 8
__in efx_nic_t *enp,
__in unsigned int index,
__in efsys_mem_t *esmp,
- __in size_t n,
+ __in size_t ndescs,
__in uint32_t id,
__in uint32_t us,
__in uint32_t flags,
__in efx_evq_t *eep,
__in efx_rxq_t *erp,
__in unsigned int label,
- __in boolean_t packed_stream);
+ __in efx_rxq_type_t type);
void
ef10_ev_rxlabel_fini(
__out_bcount(size) caddr_t data,
__in size_t size);
+extern __checkReturn efx_rc_t
+ef10_nvram_partn_read_backup(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __in unsigned int offset,
+ __out_bcount(size) caddr_t data,
+ __in size_t size);
+
extern __checkReturn efx_rc_t
ef10_nvram_partn_erase(
__in efx_nic_t *enp,
extern __checkReturn efx_rc_t
ef10_nvram_partn_rw_finish(
__in efx_nic_t *enp,
- __in uint32_t partn);
+ __in uint32_t partn,
+ __out_opt uint32_t *verify_resultp);
extern __checkReturn efx_rc_t
ef10_nvram_partn_get_version(
__in_bcount(buffer_size)
caddr_t bufferp,
__in size_t buffer_size,
- __out uint32_t *startp
- );
+ __out uint32_t *startp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_find_end(
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
- __out uint32_t *endp
- );
+ __out uint32_t *endp);
extern __checkReturn __success(return != B_FALSE) boolean_t
ef10_nvram_buffer_find_item(
__in size_t buffer_size,
__in uint32_t offset,
__out uint32_t *startp,
- __out uint32_t *lengthp
- );
+ __out uint32_t *lengthp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_get_item(
__out_bcount_part(item_max_size, *lengthp)
caddr_t itemp,
__in size_t item_max_size,
- __out uint32_t *lengthp
- );
+ __out uint32_t *lengthp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_insert_item(
__in uint32_t offset,
__in_bcount(length) caddr_t keyp,
__in uint32_t length,
- __out uint32_t *lengthp
- );
+ __out uint32_t *lengthp);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_delete_item(
__in size_t buffer_size,
__in uint32_t offset,
__in uint32_t length,
- __in uint32_t end
- );
+ __in uint32_t end);
extern __checkReturn efx_rc_t
ef10_nvram_buffer_finish(
__in_bcount(buffer_size)
caddr_t bufferp,
- __in size_t buffer_size
- );
+ __in size_t buffer_size);
#endif /* EFSYS_OPT_NVRAM */
__in unsigned int index,
__in unsigned int label,
__in efsys_mem_t *esmp,
- __in size_t n,
+ __in size_t ndescs,
__in uint32_t id,
__in uint16_t flags,
__in efx_evq_t *eep,
ef10_tx_qdestroy(
__in efx_txq_t *etp);
-extern __checkReturn efx_rc_t
+extern __checkReturn efx_rc_t
ef10_tx_qpost(
- __in efx_txq_t *etp,
- __in_ecount(n) efx_buffer_t *eb,
- __in unsigned int n,
- __in unsigned int completed,
- __inout unsigned int *addedp);
+ __in efx_txq_t *etp,
+ __in_ecount(ndescs) efx_buffer_t *ebp,
+ __in unsigned int ndescs,
+ __in unsigned int completed,
+ __inout unsigned int *addedp);
extern void
ef10_tx_qpush(
#if EFSYS_OPT_RX_PACKED_STREAM
extern void
-ef10_rx_qps_update_credits(
- __in efx_rxq_t *erp);
+ef10_rx_qpush_ps_credits(
+ __in efx_rxq_t *erp);
extern __checkReturn uint8_t *
ef10_rx_qps_packet_info(
typedef uint32_t efx_piobuf_handle_t;
-#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t) -1)
+#define EFX_PIOBUF_HANDLE_INVALID ((efx_piobuf_handle_t)-1)
extern __checkReturn efx_rc_t
ef10_nic_pio_alloc(
/* VPD */
+#if EFSYS_OPT_VPD
+
+extern __checkReturn efx_rc_t
+ef10_vpd_init(
+ __in efx_nic_t *enp);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_size(
+ __in efx_nic_t *enp,
+ __out size_t *sizep);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_read(
+ __in efx_nic_t *enp,
+ __out_bcount(size) caddr_t data,
+ __in size_t size);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_verify(
+ __in efx_nic_t *enp,
+ __in_bcount(size) caddr_t data,
+ __in size_t size);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_reinit(
+ __in efx_nic_t *enp,
+ __in_bcount(size) caddr_t data,
+ __in size_t size);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_get(
+ __in efx_nic_t *enp,
+ __in_bcount(size) caddr_t data,
+ __in size_t size,
+ __inout efx_vpd_value_t *evvp);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_set(
+ __in efx_nic_t *enp,
+ __in_bcount(size) caddr_t data,
+ __in size_t size,
+ __in efx_vpd_value_t *evvp);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_next(
+ __in efx_nic_t *enp,
+ __in_bcount(size) caddr_t data,
+ __in size_t size,
+ __out efx_vpd_value_t *evvp,
+ __inout unsigned int *contp);
+
+extern __checkReturn efx_rc_t
+ef10_vpd_write(
+ __in efx_nic_t *enp,
+ __in_bcount(size) caddr_t data,
+ __in size_t size);
+
+extern void
+ef10_vpd_fini(
+ __in efx_nic_t *enp);
+
+#endif /* EFSYS_OPT_VPD */
+
/* RX */
#if EFSYS_OPT_RX_SCALE
+extern __checkReturn efx_rc_t
+ef10_rx_scale_context_alloc(
+ __in efx_nic_t *enp,
+ __in efx_rx_scale_context_type_t type,
+ __in uint32_t num_queues,
+ __out uint32_t *rss_contextp);
+
+extern __checkReturn efx_rc_t
+ef10_rx_scale_context_free(
+ __in efx_nic_t *enp,
+ __in uint32_t rss_context);
+
extern __checkReturn efx_rc_t
ef10_rx_scale_mode_set(
__in efx_nic_t *enp,
+ __in uint32_t rss_context,
__in efx_rx_hash_alg_t alg,
__in efx_rx_hash_type_t type,
__in boolean_t insert);
extern __checkReturn efx_rc_t
ef10_rx_scale_key_set(
__in efx_nic_t *enp,
+ __in uint32_t rss_context,
__in_ecount(n) uint8_t *key,
__in size_t n);
extern __checkReturn efx_rc_t
ef10_rx_scale_tbl_set(
__in efx_nic_t *enp,
+ __in uint32_t rss_context,
__in_ecount(n) unsigned int *table,
__in size_t n);
__in uint8_t *buffer,
__out uint16_t *lengthp);
-extern void
+extern void
ef10_rx_qpost(
- __in efx_rxq_t *erp,
- __in_ecount(n) efsys_dma_addr_t *addrp,
- __in size_t size,
- __in unsigned int n,
- __in unsigned int completed,
- __in unsigned int added);
+ __in efx_rxq_t *erp,
+ __in_ecount(ndescs) efsys_dma_addr_t *addrp,
+ __in size_t size,
+ __in unsigned int ndescs,
+ __in unsigned int completed,
+ __in unsigned int added);
extern void
ef10_rx_qpush(
__in unsigned int index,
__in unsigned int label,
__in efx_rxq_type_t type,
+ __in uint32_t type_data,
__in efsys_mem_t *esmp,
- __in size_t n,
+ __in size_t ndescs,
__in uint32_t id,
+ __in unsigned int flags,
__in efx_evq_t *eep,
__in efx_rxq_t *erp);
/* Allow for the broadcast address to be added to the multicast list */
#define EFX_EF10_FILTER_MULTICAST_FILTERS_MAX (EFX_MAC_MULTICAST_LIST_MAX + 1)
+/*
+ * For encapsulated packets, there is one filter each for each combination of
+ * IPv4 or IPv6 outer frame, VXLAN, GENEVE or NVGRE packet type, and unicast or
+ * multicast inner frames.
+ */
+#define EFX_EF10_FILTER_ENCAP_FILTERS_MAX 12
+
typedef struct ef10_filter_table_s {
ef10_filter_entry_t eft_entry[EFX_EF10_FILTER_TBL_ROWS];
efx_rxq_t *eft_default_rxq;
EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
uint32_t eft_mulcst_filter_count;
boolean_t eft_using_all_mulcst;
+ uint32_t eft_encap_filter_indexes[
+ EFX_EF10_FILTER_ENCAP_FILTERS_MAX];
+ uint32_t eft_encap_filter_count;
} ef10_filter_table_t;
__checkReturn efx_rc_t
extern __checkReturn efx_rc_t
ef10_filter_supported_filters(
- __in efx_nic_t *enp,
- __out uint32_t *list,
- __out size_t *length);
+ __in efx_nic_t *enp,
+ __out_ecount(buffer_length) uint32_t *buffer,
+ __in size_t buffer_length,
+ __out size_t *list_lengthp);
extern __checkReturn efx_rc_t
ef10_filter_reconfigure(
/* Minimum space for packet in packed stream mode */
#define EFX_RX_PACKED_STREAM_MIN_PACKET_SPACE \
P2ROUNDUP(EFX_RX_PACKED_STREAM_RX_PREFIX_SIZE + \
- EFX_MAC_PDU_MIN + \
- EFX_RX_PACKED_STREAM_ALIGNMENT, \
- EFX_RX_PACKED_STREAM_ALIGNMENT)
+ EFX_MAC_PDU_MIN + \
+ EFX_RX_PACKED_STREAM_ALIGNMENT, \
+ EFX_RX_PACKED_STREAM_ALIGNMENT)
/* Maximum number of credits */
#define EFX_RX_PACKED_STREAM_MAX_CREDITS 127