#include <rte_acl.h>
#include "acl.h"
-#define BIT_SIZEOF(x) (sizeof(x) * CHAR_BIT)
-
TAILQ_HEAD(rte_acl_list, rte_tailq_entry);
static struct rte_tailq_elem rte_acl_tailq = {
return -ENOTSUP;
}
+int __attribute__ ((weak))
+rte_acl_classify_sse(__rte_unused const struct rte_acl_ctx *ctx,
+ __rte_unused const uint8_t **data,
+ __rte_unused uint32_t *results,
+ __rte_unused uint32_t num,
+ __rte_unused uint32_t categories)
+{
+ return -ENOTSUP;
+}
+
+int __attribute__ ((weak))
+rte_acl_classify_neon(__rte_unused const struct rte_acl_ctx *ctx,
+ __rte_unused const uint8_t **data,
+ __rte_unused uint32_t *results,
+ __rte_unused uint32_t num,
+ __rte_unused uint32_t categories)
+{
+ return -ENOTSUP;
+}
+
+int __attribute__ ((weak))
+rte_acl_classify_altivec(__rte_unused const struct rte_acl_ctx *ctx,
+ __rte_unused const uint8_t **data,
+ __rte_unused uint32_t *results,
+ __rte_unused uint32_t num,
+ __rte_unused uint32_t categories)
+{
+ return -ENOTSUP;
+}
+
static const rte_acl_classify_t classify_fns[] = {
[RTE_ACL_CLASSIFY_DEFAULT] = rte_acl_classify_scalar,
[RTE_ACL_CLASSIFY_SCALAR] = rte_acl_classify_scalar,
[RTE_ACL_CLASSIFY_SSE] = rte_acl_classify_sse,
[RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,
+ [RTE_ACL_CLASSIFY_NEON] = rte_acl_classify_neon,
+ [RTE_ACL_CLASSIFY_ALTIVEC] = rte_acl_classify_altivec,
};
/* by default, use always available scalar code path. */
* if both conditions are met:
* at build time compiler supports AVX2 and target cpu supports AVX2.
*/
-static void __attribute__((constructor))
-rte_acl_init(void)
+RTE_INIT(rte_acl_init)
{
enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
+#if defined(RTE_ARCH_ARM64)
+ alg = RTE_ACL_CLASSIFY_NEON;
+#elif defined(RTE_ARCH_ARM)
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_NEON))
+ alg = RTE_ACL_CLASSIFY_NEON;
+#elif defined(RTE_ARCH_PPC_64)
+ alg = RTE_ACL_CLASSIFY_ALTIVEC;
+#else
#ifdef CC_AVX2_SUPPORT
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
alg = RTE_ACL_CLASSIFY_AVX2;
#endif
alg = RTE_ACL_CLASSIFY_SSE;
+#endif
rte_acl_set_default_classify(alg);
}
if ((RTE_LEN2MASK(RTE_ACL_MAX_CATEGORIES, typeof(rd->category_mask)) &
rd->category_mask) == 0 ||
rd->priority > RTE_ACL_MAX_PRIORITY ||
- rd->priority < RTE_ACL_MIN_PRIORITY ||
- rd->userdata == RTE_ACL_INVALID_USERDATA)
+ rd->priority < RTE_ACL_MIN_PRIORITY)
return -EINVAL;
return 0;
}
}
rte_rwlock_read_unlock(RTE_EAL_TAILQ_RWLOCK);
}
-
-/*
- * Support for legacy ipv4vlan rules.
- */
-
-RTE_ACL_RULE_DEF(acl_ipv4vlan_rule, RTE_ACL_IPV4VLAN_NUM_FIELDS);
-
-static int
-acl_ipv4vlan_check_rule(const struct rte_acl_ipv4vlan_rule *rule)
-{
- if (rule->src_port_low > rule->src_port_high ||
- rule->dst_port_low > rule->dst_port_high ||
- rule->src_mask_len > BIT_SIZEOF(rule->src_addr) ||
- rule->dst_mask_len > BIT_SIZEOF(rule->dst_addr))
- return -EINVAL;
-
- return acl_check_rule(&rule->data);
-}
-
-static void
-acl_ipv4vlan_convert_rule(const struct rte_acl_ipv4vlan_rule *ri,
- struct acl_ipv4vlan_rule *ro)
-{
- ro->data = ri->data;
-
- ro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].value.u8 = ri->proto;
- ro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].value.u16 = ri->vlan;
- ro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].value.u16 = ri->domain;
- ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].value.u32 = ri->src_addr;
- ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].value.u32 = ri->dst_addr;
- ro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].value.u16 = ri->src_port_low;
- ro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].value.u16 = ri->dst_port_low;
-
- ro->field[RTE_ACL_IPV4VLAN_PROTO_FIELD].mask_range.u8 = ri->proto_mask;
- ro->field[RTE_ACL_IPV4VLAN_VLAN1_FIELD].mask_range.u16 = ri->vlan_mask;
- ro->field[RTE_ACL_IPV4VLAN_VLAN2_FIELD].mask_range.u16 =
- ri->domain_mask;
- ro->field[RTE_ACL_IPV4VLAN_SRC_FIELD].mask_range.u32 =
- ri->src_mask_len;
- ro->field[RTE_ACL_IPV4VLAN_DST_FIELD].mask_range.u32 = ri->dst_mask_len;
- ro->field[RTE_ACL_IPV4VLAN_SRCP_FIELD].mask_range.u16 =
- ri->src_port_high;
- ro->field[RTE_ACL_IPV4VLAN_DSTP_FIELD].mask_range.u16 =
- ri->dst_port_high;
-}
-
-int
-rte_acl_ipv4vlan_add_rules(struct rte_acl_ctx *ctx,
- const struct rte_acl_ipv4vlan_rule *rules,
- uint32_t num)
-{
- int32_t rc;
- uint32_t i;
- struct acl_ipv4vlan_rule rv;
-
- if (ctx == NULL || rules == NULL || ctx->rule_sz != sizeof(rv))
- return -EINVAL;
-
- /* check input rules. */
- for (i = 0; i != num; i++) {
- rc = acl_ipv4vlan_check_rule(rules + i);
- if (rc != 0) {
- RTE_LOG(ERR, ACL, "%s(%s): rule #%u is invalid\n",
- __func__, ctx->name, i + 1);
- return rc;
- }
- }
-
- if (num + ctx->num_rules > ctx->max_rules)
- return -ENOMEM;
-
- /* perform conversion to the internal format and add to the context. */
- for (i = 0, rc = 0; i != num && rc == 0; i++) {
- acl_ipv4vlan_convert_rule(rules + i, &rv);
- rc = acl_add_rules(ctx, &rv, 1);
- }
-
- return rc;
-}
-
-static void
-acl_ipv4vlan_config(struct rte_acl_config *cfg,
- const uint32_t layout[RTE_ACL_IPV4VLAN_NUM],
- uint32_t num_categories)
-{
- static const struct rte_acl_field_def
- ipv4_defs[RTE_ACL_IPV4VLAN_NUM_FIELDS] = {
- {
- .type = RTE_ACL_FIELD_TYPE_BITMASK,
- .size = sizeof(uint8_t),
- .field_index = RTE_ACL_IPV4VLAN_PROTO_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_PROTO,
- },
- {
- .type = RTE_ACL_FIELD_TYPE_BITMASK,
- .size = sizeof(uint16_t),
- .field_index = RTE_ACL_IPV4VLAN_VLAN1_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_VLAN,
- },
- {
- .type = RTE_ACL_FIELD_TYPE_BITMASK,
- .size = sizeof(uint16_t),
- .field_index = RTE_ACL_IPV4VLAN_VLAN2_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_VLAN,
- },
- {
- .type = RTE_ACL_FIELD_TYPE_MASK,
- .size = sizeof(uint32_t),
- .field_index = RTE_ACL_IPV4VLAN_SRC_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_SRC,
- },
- {
- .type = RTE_ACL_FIELD_TYPE_MASK,
- .size = sizeof(uint32_t),
- .field_index = RTE_ACL_IPV4VLAN_DST_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_DST,
- },
- {
- .type = RTE_ACL_FIELD_TYPE_RANGE,
- .size = sizeof(uint16_t),
- .field_index = RTE_ACL_IPV4VLAN_SRCP_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_PORTS,
- },
- {
- .type = RTE_ACL_FIELD_TYPE_RANGE,
- .size = sizeof(uint16_t),
- .field_index = RTE_ACL_IPV4VLAN_DSTP_FIELD,
- .input_index = RTE_ACL_IPV4VLAN_PORTS,
- },
- };
-
- memcpy(&cfg->defs, ipv4_defs, sizeof(ipv4_defs));
- cfg->num_fields = RTE_DIM(ipv4_defs);
-
- cfg->defs[RTE_ACL_IPV4VLAN_PROTO_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_PROTO];
- cfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_VLAN];
- cfg->defs[RTE_ACL_IPV4VLAN_VLAN2_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_VLAN] +
- cfg->defs[RTE_ACL_IPV4VLAN_VLAN1_FIELD].size;
- cfg->defs[RTE_ACL_IPV4VLAN_SRC_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_SRC];
- cfg->defs[RTE_ACL_IPV4VLAN_DST_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_DST];
- cfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_PORTS];
- cfg->defs[RTE_ACL_IPV4VLAN_DSTP_FIELD].offset =
- layout[RTE_ACL_IPV4VLAN_PORTS] +
- cfg->defs[RTE_ACL_IPV4VLAN_SRCP_FIELD].size;
-
- cfg->num_categories = num_categories;
-}
-
-int
-rte_acl_ipv4vlan_build(struct rte_acl_ctx *ctx,
- const uint32_t layout[RTE_ACL_IPV4VLAN_NUM],
- uint32_t num_categories)
-{
- struct rte_acl_config cfg;
-
- if (ctx == NULL || layout == NULL)
- return -EINVAL;
-
- memset(&cfg, 0, sizeof(cfg));
- acl_ipv4vlan_config(&cfg, layout, num_categories);
- return rte_acl_build(ctx, &cfg);
-}