TAILQ_HEAD(rte_acl_list, rte_tailq_entry);
+static struct rte_tailq_elem rte_acl_tailq = {
+ .name = "RTE_ACL",
+};
+EAL_REGISTER_TAILQ(rte_acl_tailq)
+
+/*
+ * If the compiler doesn't support AVX2 instructions,
+ * then the dummy one would be used instead for AVX2 classify method.
+ */
+int __attribute__ ((weak))
+rte_acl_classify_avx2(__rte_unused const struct rte_acl_ctx *ctx,
+ __rte_unused const uint8_t **data,
+ __rte_unused uint32_t *results,
+ __rte_unused uint32_t num,
+ __rte_unused uint32_t categories)
+{
+ return -ENOTSUP;
+}
+
static const rte_acl_classify_t classify_fns[] = {
[RTE_ACL_CLASSIFY_DEFAULT] = rte_acl_classify_scalar,
[RTE_ACL_CLASSIFY_SCALAR] = rte_acl_classify_scalar,
[RTE_ACL_CLASSIFY_SSE] = rte_acl_classify_sse,
+ [RTE_ACL_CLASSIFY_AVX2] = rte_acl_classify_avx2,
};
/* by default, use always available scalar code path. */
return 0;
}
+/*
+ * Select highest available classify method as default one.
+ * Note that CLASSIFY_AVX2 should be set as a default only
+ * if both conditions are met:
+ * at build time compiler supports AVX2 and target cpu supports AVX2.
+ */
static void __attribute__((constructor))
rte_acl_init(void)
{
enum rte_acl_classify_alg alg = RTE_ACL_CLASSIFY_DEFAULT;
+#ifdef CC_AVX2_SUPPORT
+ if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
+ alg = RTE_ACL_CLASSIFY_AVX2;
+ else if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
+#else
if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SSE4_1))
+#endif
alg = RTE_ACL_CLASSIFY_SSE;
rte_acl_set_default_classify(alg);
struct rte_acl_list *acl_list;
struct rte_tailq_entry *te;
- /* check that we have an initialised tail queue */
- acl_list = RTE_TAILQ_LOOKUP_BY_IDX(RTE_TAILQ_ACL, rte_acl_list);
- if (acl_list == NULL) {
- rte_errno = E_RTE_NO_TAILQ;
- return NULL;
- }
+ acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
rte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);
TAILQ_FOREACH(te, acl_list, next) {
if (ctx == NULL)
return;
- /* check that we have an initialised tail queue */
- acl_list = RTE_TAILQ_LOOKUP_BY_IDX(RTE_TAILQ_ACL, rte_acl_list);
- if (acl_list == NULL) {
- rte_errno = E_RTE_NO_TAILQ;
- return;
- }
+ acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
rte_rwlock_write_lock(RTE_EAL_TAILQ_RWLOCK);
struct rte_tailq_entry *te;
char name[sizeof(ctx->name)];
- /* check that we have an initialised tail queue */
- acl_list = RTE_TAILQ_LOOKUP_BY_IDX(RTE_TAILQ_ACL, rte_acl_list);
- if (acl_list == NULL) {
- rte_errno = E_RTE_NO_TAILQ;
- return NULL;
- }
+ acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
/* check that input parameters are valid. */
if (param == NULL || param->name == NULL) {
struct rte_acl_list *acl_list;
struct rte_tailq_entry *te;
- /* check that we have an initialised tail queue */
- acl_list = RTE_TAILQ_LOOKUP_BY_IDX(RTE_TAILQ_ACL, rte_acl_list);
- if (acl_list == NULL) {
- rte_errno = E_RTE_NO_TAILQ;
- return;
- }
+ acl_list = RTE_TAILQ_CAST(rte_acl_tailq.head, rte_acl_list);
rte_rwlock_read_lock(RTE_EAL_TAILQ_RWLOCK);
TAILQ_FOREACH(te, acl_list, next) {
if (ctx == NULL || layout == NULL)
return -EINVAL;
+ memset(&cfg, 0, sizeof(cfg));
acl_ipv4vlan_config(&cfg, layout, num_categories);
return rte_acl_build(ctx, &cfg);
}