#endif
#include <rte_pci_dev_features.h>
-/**
- * MSI-X related macros, copy from linux/pci_regs.h in kernel 2.6.39,
- * but none of them in kernel 2.6.35.
- */
-#ifndef PCI_MSIX_ENTRY_SIZE
-#define PCI_MSIX_ENTRY_SIZE 16
-#define PCI_MSIX_ENTRY_LOWER_ADDR 0
-#define PCI_MSIX_ENTRY_UPPER_ADDR 4
-#define PCI_MSIX_ENTRY_DATA 8
-#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
-#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
-#endif
-
#ifdef RTE_PCI_CONFIG
#define PCI_SYS_FILE_BUF_SIZE 10
#define PCI_DEV_CAP_REG 0xA4
#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
#endif
-#define IGBUIO_NUM_MSI_VECTORS 1
-
/**
* A structure describing the private information for a uio device.
*/
struct rte_uio_pci_dev {
struct uio_info info;
struct pci_dev *pdev;
- spinlock_t lock; /* spinlock for accessing PCI config space or msix data in multi tasks/isr */
enum rte_intr_mode mode;
- struct msix_entry \
- msix_entries[IGBUIO_NUM_MSI_VECTORS]; /* pointer to the msix vectors to be allocated later */
};
static char *intr_mode = NULL;
else
return -EINVAL;
+ pci_cfg_access_lock(pci_dev);
pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
PCI_DEV_CAP_REG, &val);
- if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) /* Not supported */
+ if (!(val & PCI_DEV_CAP_EXT_TAG_MASK)) { /* Not supported */
+ pci_cfg_access_unlock(pci_dev);
return -EPERM;
+ }
val = 0;
pci_bus_read_config_dword(pci_dev->bus, pci_dev->devfn,
val &= ~PCI_DEV_CTRL_EXT_TAG_MASK;
pci_bus_write_config_dword(pci_dev->bus, pci_dev->devfn,
PCI_DEV_CTRL_REG, val);
+ pci_cfg_access_unlock(pci_dev);
return count;
}
.attrs = dev_attrs,
};
-static inline int
-pci_lock(struct pci_dev * pdev)
-{
- /* Some function names changes between 3.2.0 and 3.3.0... */
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
- pci_block_user_cfg_access(pdev);
- return 1;
-#else
- return pci_cfg_access_trylock(pdev);
-#endif
+/* Check if INTX works to control irq's.
+ * Set's INTX_DISABLE flag and reads it back
+ */
+static bool pci_intx_mask_supported(struct pci_dev *dev)
+{
+ bool mask_supported = false;
+ uint16_t orig, new
+
+ pci_block_user_cfg_access(dev);
+ pci_read_config_word(pdev, PCI_COMMAND, &orig);
+ pci_write_config_word(dev, PCI_COMMAND,
+ orig ^ PCI_COMMAND_INTX_DISABLE);
+ pci_read_config_word(dev, PCI_COMMAND, &new);
+
+ if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
+ dev_err(&dev->dev, "Command register changed from "
+ "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
+ } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
+ mask_supported = true;
+ pci_write_config_word(dev, PCI_COMMAND, orig);
+ }
+ pci_unblock_user_cfg_access(dev);
}
-static inline void
-pci_unlock(struct pci_dev * pdev)
+static bool pci_check_and_mask_intx(struct pci_dev *pdev)
{
- /* Some function names changes between 3.2.0 and 3.3.0... */
-#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0)
- pci_unblock_user_cfg_access(pdev);
-#else
- pci_cfg_access_unlock(pdev);
-#endif
+ bool pending;
+ uint32_t status;
+
+ pci_block_user_cfg_access(dev);
+ pci_read_config_dword(pdev, PCI_COMMAND, &status);
+
+ /* interrupt is not ours, goes to out */
+ pending = (((status >> 16) & PCI_STATUS_INTERRUPT) != 0);
+ if (pending) {
+ uint16_t old, new;
+
+ old = status;
+ if (state != 0)
+ new = old & (~PCI_COMMAND_INTX_DISABLE);
+ else
+ new = old | PCI_COMMAND_INTX_DISABLE;
+
+ if (old != new)
+ pci_write_config_word(pdev, PCI_COMMAND, new);
+ }
+ pci_unblock_user_cfg_access(dev);
+
+ return pending;
}
+#endif
-/**
+/*
* It masks the msix on/off of generating MSI-X messages.
*/
-static int
+static void
igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
{
- uint32_t mask_bits = desc->masked;
+ u32 mask_bits = desc->masked;
unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
PCI_MSIX_ENTRY_VECTOR_CTRL;
readl(desc->mask_base);
desc->masked = mask_bits;
}
-
- return 0;
-}
-
-/**
- * This function sets/clears the masks for generating LSC interrupts.
- *
- * @param info
- * The pointer to struct uio_info.
- * @param on
- * The on/off flag of masking LSC.
- * @return
- * -On success, zero value.
- * -On failure, a negative value.
- */
-static int
-igbuio_set_interrupt_mask(struct rte_uio_pci_dev *udev, int32_t state)
-{
- struct pci_dev *pdev = udev->pdev;
-
- if (udev->mode == RTE_INTR_MODE_MSIX) {
- struct msi_desc *desc;
-
- list_for_each_entry(desc, &pdev->msi_list, list) {
- igbuio_msix_mask_irq(desc, state);
- }
- } else if (udev->mode == RTE_INTR_MODE_LEGACY) {
- uint32_t status;
- uint16_t old, new;
-
- pci_read_config_dword(pdev, PCI_COMMAND, &status);
- old = status;
- if (state != 0)
- new = old & (~PCI_COMMAND_INTX_DISABLE);
- else
- new = old | PCI_COMMAND_INTX_DISABLE;
-
- if (old != new)
- pci_write_config_word(pdev, PCI_COMMAND, new);
- }
-
- return 0;
}
/**
static int
igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
{
- unsigned long flags;
struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
struct pci_dev *pdev = udev->pdev;
- spin_lock_irqsave(&udev->lock, flags);
- if (!pci_lock(pdev)) {
- spin_unlock_irqrestore(&udev->lock, flags);
- return -1;
- }
+ pci_cfg_access_lock(pdev);
+ if (udev->mode == RTE_INTR_MODE_LEGACY)
+ pci_intx(pdev, !!irq_state);
- igbuio_set_interrupt_mask(udev, irq_state);
+ else if (udev->mode == RTE_INTR_MODE_MSIX) {
+ struct msi_desc *desc;
- pci_unlock(pdev);
- spin_unlock_irqrestore(&udev->lock, flags);
+ list_for_each_entry(desc, &pdev->msi_list, list)
+ igbuio_msix_mask_irq(desc, irq_state);
+ }
+ pci_cfg_access_unlock(pdev);
return 0;
}
static irqreturn_t
igbuio_pci_irqhandler(int irq, struct uio_info *info)
{
- irqreturn_t ret = IRQ_NONE;
- unsigned long flags;
struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
- struct pci_dev *pdev = udev->pdev;
- uint32_t cmd_status_dword;
- uint16_t status;
-
- spin_lock_irqsave(&udev->lock, flags);
- /* block userspace PCI config reads/writes */
- if (!pci_lock(pdev))
- goto spin_unlock;
-
- /* for legacy mode, interrupt maybe shared */
- if (udev->mode == RTE_INTR_MODE_LEGACY) {
- pci_read_config_dword(pdev, PCI_COMMAND, &cmd_status_dword);
- status = cmd_status_dword >> 16;
- /* interrupt is not ours, goes to out */
- if (!(status & PCI_STATUS_INTERRUPT))
- goto done;
- }
- igbuio_set_interrupt_mask(udev, 0);
- ret = IRQ_HANDLED;
-done:
- /* unblock userspace PCI config reads/writes */
- pci_unlock(pdev);
-spin_unlock:
- spin_unlock_irqrestore(&udev->lock, flags);
- pr_info("irq 0x%x %s\n", irq, (ret == IRQ_HANDLED) ? "handled" : "not handled");
+ /* Legacy mode need to mask in hardware */
+ if (udev->mode == RTE_INTR_MODE_LEGACY &&
+ !pci_check_and_mask_intx(udev->pdev))
+ return IRQ_NONE;
- return ret;
+ /* Message signal mode, no share IRQ and automasked */
+ return IRQ_HANDLED;
}
#ifdef CONFIG_XEN_DOM0
}
}
- return ((iom != 0) ? ret : ENOENT);
+ return (iom != 0) ? ret : -ENOENT;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
struct rte_uio_pci_dev *udev;
+ struct msix_entry msix_entry;
+ int err;
udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
if (!udev)
* enable device: ask low-level code to enable I/O and
* memory
*/
- if (pci_enable_device(dev)) {
+ err = pci_enable_device(dev);
+ if (err != 0) {
dev_err(&dev->dev, "Cannot enable PCI device\n");
goto fail_free;
}
* reserve device's PCI memory regions for use by this
* module
*/
- if (pci_request_regions(dev, "igb_uio")) {
+ err = pci_request_regions(dev, "igb_uio");
+ if (err != 0) {
dev_err(&dev->dev, "Cannot request regions\n");
goto fail_disable;
}
pci_set_master(dev);
/* remap IO memory */
- if (igbuio_setup_bars(dev, &udev->info))
+ err = igbuio_setup_bars(dev, &udev->info);
+ if (err != 0)
goto fail_release_iomem;
/* set 64-bit DMA mask */
- if (pci_set_dma_mask(dev, DMA_BIT_MASK(64))) {
+ err = pci_set_dma_mask(dev, DMA_BIT_MASK(64));
+ if (err != 0) {
dev_err(&dev->dev, "Cannot set DMA mask\n");
goto fail_release_iomem;
- } else if (pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64))) {
+ }
+
+ err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
+ if (err != 0) {
dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
goto fail_release_iomem;
}
udev->info.version = "0.1";
udev->info.handler = igbuio_pci_irqhandler;
udev->info.irqcontrol = igbuio_pci_irqcontrol;
+ udev->info.irq = dev->irq;
#ifdef CONFIG_XEN_DOM0
/* check if the driver run on Xen Dom0 */
if (xen_initial_domain())
#endif
udev->info.priv = udev;
udev->pdev = dev;
- udev->mode = RTE_INTR_MODE_LEGACY;
- spin_lock_init(&udev->lock);
-
- /* check if it need to try msix first */
- if (igbuio_intr_mode_preferred == RTE_INTR_MODE_MSIX) {
- int vector;
- for (vector = 0; vector < IGBUIO_NUM_MSI_VECTORS; vector ++)
- udev->msix_entries[vector].entry = vector;
-
- if (pci_enable_msix(udev->pdev, udev->msix_entries, IGBUIO_NUM_MSI_VECTORS) == 0) {
+ switch (igbuio_intr_mode_preferred) {
+ case RTE_INTR_MODE_NONE:
+ udev->info.irq = 0;
+ break;
+ case RTE_INTR_MODE_MSIX:
+ /* Only 1 msi-x vector needed */
+ msix_entry.entry = 0;
+ if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
+ dev_dbg(&dev->dev, "using MSI-X");
+ udev->info.irq = msix_entry.vector;
udev->mode = RTE_INTR_MODE_MSIX;
+ break;
}
- else {
- pci_disable_msix(udev->pdev);
- pr_info("fail to enable pci msix, or not enough msix entries\n");
- }
- }
- switch (udev->mode) {
- case RTE_INTR_MODE_MSIX:
- udev->info.irq_flags = 0;
- udev->info.irq = udev->msix_entries[0].vector;
- break;
- case RTE_INTR_MODE_MSI:
- break;
+ /* fall back to INTX */
case RTE_INTR_MODE_LEGACY:
- udev->info.irq_flags = IRQF_SHARED;
- udev->info.irq = dev->irq;
+ if (pci_intx_mask_supported(dev)) {
+ dev_dbg(&dev->dev, "using INTX");
+ udev->info.irq_flags = IRQF_SHARED;
+ udev->mode = RTE_INTR_MODE_LEGACY;
+ } else {
+ dev_err(&dev->dev, "PCI INTX mask not supported\n");
+ err = -EIO;
+ goto fail_release_iomem;
+ }
break;
default:
- break;
+ dev_err(&dev->dev, "invalid IRQ mode %u",
+ igbuio_intr_mode_preferred);
+ err = -EINVAL;
+ goto fail_release_iomem;
}
- pci_set_drvdata(dev, udev);
- igbuio_pci_irqcontrol(&udev->info, 0);
-
- if (sysfs_create_group(&dev->dev.kobj, &dev_attr_grp))
+ err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
+ if (err != 0)
goto fail_release_iomem;
/* register uio driver */
- if (uio_register_device(&dev->dev, &udev->info))
- goto fail_release_iomem;
+ err = uio_register_device(&dev->dev, &udev->info);
+ if (err != 0)
+ goto fail_remove_group;
- pr_info("uio device registered with irq %lx\n", udev->info.irq);
+ pci_set_drvdata(dev, udev);
+
+ dev_info(&dev->dev, "uio device registered with irq %lx\n",
+ udev->info.irq);
return 0;
-fail_release_iomem:
+fail_remove_group:
sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
+fail_release_iomem:
igbuio_pci_release_iomem(&udev->info);
if (udev->mode == RTE_INTR_MODE_MSIX)
pci_disable_msix(udev->pdev);
fail_free:
kfree(udev);
- return -ENODEV;
+ return err;
}
static void
igbuio_pci_remove(struct pci_dev *dev)
{
struct uio_info *info = pci_get_drvdata(dev);
+ struct rte_uio_pci_dev *udev = igbuio_get_uio_pci_dev(info);
if (info->priv == NULL) {
pr_notice("Not igbuio device\n");
sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
uio_unregister_device(info);
igbuio_pci_release_iomem(info);
- if (((struct rte_uio_pci_dev *)info->priv)->mode ==
- RTE_INTR_MODE_MSIX)
+ if (udev->mode == RTE_INTR_MODE_MSIX)
pci_disable_msix(dev);
pci_release_regions(dev);
pci_disable_device(dev);
module_init(igbuio_pci_init_module);
module_exit(igbuio_pci_exit_module);
-module_param(intr_mode, charp, S_IRUGO | S_IWUSR);
+module_param(intr_mode, charp, S_IRUGO);
MODULE_PARM_DESC(intr_mode,
"igb_uio interrupt mode (default=msix):\n"
" " RTE_INTR_MODE_MSIX_NAME " Use MSIX interrupt\n"
git.droids-corp.org / dpdk.git / blobdiff