X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=inline;f=drivers%2Fnet%2Fi40e%2Fi40e_pf.c;h=5afd61a0746d0346f0fa7dd03dddd9075e2c8e17;hb=2a345a891917829d5eef7dc5d830131f37ec6fba;hp=b89a1e263524f3daf0920fd38ead423e57b51c35;hpb=5c9222058df7cc10fa98c13d097f85a7fa0341a3;p=dpdk.git

diff --git a/drivers/net/i40e/i40e_pf.c b/drivers/net/i40e/i40e_pf.c
index b89a1e2635..5afd61a074 100644
--- a/drivers/net/i40e/i40e_pf.c
+++ b/drivers/net/i40e/i40e_pf.c
@@ -82,8 +82,8 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
 	 * VF should use scatter range queues. So, it needn't
 	 * to set QBASE in this register.
 	 */
-	I40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id),
-	     I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
+	i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
+			  I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
 
 	/* Set to enable VFLAN_QTABLE[] registers valid */
 	I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
@@ -108,7 +108,7 @@ i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
 			q2 = qbase + 2 * i + 1;
 
 		val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
-		I40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
+		i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
 	}
 	I40E_WRITE_FLUSH(hw);
 
@@ -315,6 +315,8 @@ i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf)
 	/* As assume Vf only has single VSI now, always return 0 */
 	vf_res->vsi_res[0].vsi_id = 0;
 	vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
+	ether_addr_copy(&vf->mac_addr,
+		(struct ether_addr *)vf_res->vsi_res[0].default_mac_addr);
 
 send_msg:
 	i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
@@ -547,13 +549,10 @@ i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
 		goto send_msg;
 	}
 
-	if (irqmap->vecmap[0].vector_id == 0) {
-		PMD_DRV_LOG(ERR, "DPDK host don't support use IRQ0");
-		ret = I40E_ERR_PARAM;
-		goto send_msg;
-	}
 	/* This MSIX intr store the intr in VF range */
 	vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
+	vf->vsi->nb_msix = irqmap->num_vectors;
+	vf->vsi->nb_used_qps = vf->vsi->nb_qps;
 
 	/* Don't care how the TX/RX queue mapping with this vector.
 	 * Link all VF RX queues together. Only did mapping work.
@@ -1048,6 +1047,7 @@ i40e_pf_host_init(struct rte_eth_dev *dev)
 		ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
 		if (ret != I40E_SUCCESS)
 			goto fail;
+		eth_random_addr(pf->vfs[i].mac_addr.addr_bytes);
 	}
 
 	/* restore irq0 */
@@ -1061,3 +1061,37 @@ fail:
 
 	return ret;
 }
+
+int
+i40e_pf_host_uninit(struct rte_eth_dev *dev)
+{
+	struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
+	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
+	uint32_t val;
+
+	PMD_INIT_FUNC_TRACE();
+
+	/**
+	 * return if SRIOV not enabled, VF number not configured or
+	 * no queue assigned.
+	 */
+	if ((!hw->func_caps.sr_iov_1_1) ||
+		(pf->vf_num == 0) ||
+		(pf->vf_nb_qps == 0))
+		return I40E_SUCCESS;
+
+	/* free memory to store VF structure */
+	rte_free(pf->vfs);
+	pf->vfs = NULL;
+
+	/* Disable irq0 for VFR event */
+	i40e_pf_disable_irq0(hw);
+
+	/* Disable VF link status interrupt */
+	val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
+	val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
+	I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
+	I40E_WRITE_FLUSH(hw);
+
+	return I40E_SUCCESS;
+}