X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=inline;f=examples%2Fl3fwd-power%2Fmain.c;h=dd9e014c07f36405ee354badba6579a4b05f662a;hb=0cdee2357aed109d4d3d9cd6c874f6fbcedeb6a7;hp=ad8fd7be82f880510d977ab7fee965925d060d0c;hpb=3998e2a07220844d3f3c17f76a781ced3efe0de0;p=dpdk.git diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c index ad8fd7be82..dd9e014c07 100644 --- a/examples/l3fwd-power/main.c +++ b/examples/l3fwd-power/main.c @@ -50,8 +50,6 @@ #define MIN_ZERO_POLL_COUNT 10 -/* around 100ms at 2 Ghz */ -#define TIMER_RESOLUTION_CYCLES 200000000ULL /* 100 ms interval */ #define TIMER_NUMBER_PER_SECOND 10 /* 100000 us */ @@ -202,7 +200,6 @@ static struct rte_eth_conf port_conf = { .mq_mode = ETH_MQ_TX_NONE, }, .intr_conf = { - .lsc = 1, .rxq = 1, }, }; @@ -728,6 +725,7 @@ power_freq_scaleup_heuristic(unsigned lcore_id, uint16_t port_id, uint16_t queue_id) { + uint32_t rxq_count = rte_eth_rx_queue_count(port_id, queue_id); /** * HW Rx queue size is 128 by default, Rx burst read at maximum 32 entries * per iteration @@ -739,15 +737,12 @@ power_freq_scaleup_heuristic(unsigned lcore_id, #define FREQ_UP_TREND2_ACC 100 #define FREQ_UP_THRESHOLD 10000 - if (likely(rte_eth_rx_descriptor_done(port_id, queue_id, - FREQ_GEAR3_RX_PACKET_THRESHOLD) > 0)) { + if (likely(rxq_count > FREQ_GEAR3_RX_PACKET_THRESHOLD)) { stats[lcore_id].trend = 0; return FREQ_HIGHEST; - } else if (likely(rte_eth_rx_descriptor_done(port_id, queue_id, - FREQ_GEAR2_RX_PACKET_THRESHOLD) > 0)) + } else if (likely(rxq_count > FREQ_GEAR2_RX_PACKET_THRESHOLD)) stats[lcore_id].trend += FREQ_UP_TREND2_ACC; - else if (likely(rte_eth_rx_descriptor_done(port_id, queue_id, - FREQ_GEAR1_RX_PACKET_THRESHOLD) > 0)) + else if (likely(rxq_count > FREQ_GEAR1_RX_PACKET_THRESHOLD)) stats[lcore_id].trend += FREQ_UP_TREND1_ACC; if (likely(stats[lcore_id].trend > FREQ_UP_THRESHOLD)) { @@ -846,7 +841,7 @@ main_loop(__attribute__((unused)) void *dummy) { struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; unsigned lcore_id; - uint64_t prev_tsc, diff_tsc, cur_tsc; + uint64_t prev_tsc, diff_tsc, cur_tsc, tim_res_tsc, hz; uint64_t prev_tsc_power = 0, cur_tsc_power, diff_tsc_power; int i, j, nb_rx; uint8_t queueid; @@ -861,6 +856,8 @@ main_loop(__attribute__((unused)) void *dummy) const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US; prev_tsc = 0; + hz = rte_get_timer_hz(); + tim_res_tsc = hz/TIMER_NUMBER_PER_SECOND; lcore_id = rte_lcore_id(); qconf = &lcore_conf[lcore_id]; @@ -906,7 +903,7 @@ main_loop(__attribute__((unused)) void *dummy) } diff_tsc_power = cur_tsc_power - prev_tsc_power; - if (diff_tsc_power > TIMER_RESOLUTION_CYCLES) { + if (diff_tsc_power > tim_res_tsc) { rte_timer_manage(); prev_tsc_power = cur_tsc_power; } @@ -1022,9 +1019,11 @@ start_rx: turn_on_intr(qconf); sleep_until_rx_interrupt( qconf->n_rx_queue); + /** + * start receiving packets immediately + */ + goto start_rx; } - /* start receiving packets immediately */ - goto start_rx; } stats[lcore_id].sleep_time += lcore_idle_hint; }