X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=config%2Fcommon_base;h=c70b8f68bf23ce48fe64e13a29b7cfdafc6b6111;hb=c94366cfc641c6ae43d01c2ac4c6b8993817b356;hp=b0a2d0062cbecac4c6246aeb3050afa323fe481b;hpb=27cea11686ffcc64625cd321b500d6656b4720c6;p=dpdk.git diff --git a/config/common_base b/config/common_base index b0a2d0062c..c70b8f68bf 100644 --- a/config/common_base +++ b/config/common_base @@ -1,34 +1,19 @@ -# BSD LICENSE -# -# Copyright(c) 2010-2017 Intel Corporation. All rights reserved. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in -# the documentation and/or other materials provided with the -# distribution. -# * Neither the name of Intel Corporation nor the names of its -# contributors may be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2010-2017 Intel Corporation + +# +# String that appears before the version number +# +CONFIG_RTE_VER_PREFIX="DPDK" + +# +# Version information completed when this file is processed for a build # +CONFIG_RTE_VER_YEAR=__YEAR +CONFIG_RTE_VER_MONTH=__MONTH +CONFIG_RTE_VER_MINOR=__MINOR +CONFIG_RTE_VER_SUFFIX=__SUFFIX +CONFIG_RTE_VER_RELEASE=__RELEASE # # define executive environment @@ -64,6 +49,11 @@ CONFIG_RTE_FORCE_INTRINSICS=n # CONFIG_RTE_ARCH_STRICT_ALIGN=n +# +# Enable link time optimization +# +CONFIG_RTE_ENABLE_LTO=n + # # Compile to share library # @@ -75,14 +65,14 @@ CONFIG_RTE_BUILD_SHARED_LIB=n CONFIG_RTE_NEXT_ABI=y # -# Major ABI to overwrite library specific LIBABIVER +# Machine's cache line size # -CONFIG_RTE_MAJOR_ABI= +CONFIG_RTE_CACHE_LINE_SIZE=64 # -# Machine's cache line size +# Memory model # -CONFIG_RTE_CACHE_LINE_SIZE=64 +CONFIG_RTE_USE_C11_MEM_MODEL=n # # Compile Environment Abstraction Layer @@ -90,21 +80,42 @@ CONFIG_RTE_CACHE_LINE_SIZE=64 CONFIG_RTE_LIBRTE_EAL=y CONFIG_RTE_MAX_LCORE=128 CONFIG_RTE_MAX_NUMA_NODES=8 -CONFIG_RTE_MAX_MEMSEG=256 +CONFIG_RTE_MAX_HEAPS=32 +CONFIG_RTE_MAX_MEMSEG_LISTS=64 +# each memseg list will be limited to either RTE_MAX_MEMSEG_PER_LIST pages +# or RTE_MAX_MEM_MB_PER_LIST megabytes worth of memory, whichever is smaller +CONFIG_RTE_MAX_MEMSEG_PER_LIST=8192 +CONFIG_RTE_MAX_MEM_MB_PER_LIST=32768 +# a "type" is a combination of page size and NUMA node. total number of memseg +# lists per type will be limited to either RTE_MAX_MEMSEG_PER_TYPE pages (split +# over multiple lists of RTE_MAX_MEMSEG_PER_LIST pages), or +# RTE_MAX_MEM_MB_PER_TYPE megabytes of memory (split over multiple lists of +# RTE_MAX_MEM_MB_PER_LIST), whichever is smaller +CONFIG_RTE_MAX_MEMSEG_PER_TYPE=32768 +CONFIG_RTE_MAX_MEM_MB_PER_TYPE=131072 +# global maximum usable amount of VA, in megabytes +CONFIG_RTE_MAX_MEM_MB=524288 CONFIG_RTE_MAX_MEMZONE=2560 CONFIG_RTE_MAX_TAILQ=32 CONFIG_RTE_ENABLE_ASSERT=n CONFIG_RTE_LOG_DP_LEVEL=RTE_LOG_INFO +CONFIG_RTE_ENABLE_TRACE_FP=n CONFIG_RTE_LOG_HISTORY=256 CONFIG_RTE_BACKTRACE=y CONFIG_RTE_LIBEAL_USE_HPET=n -CONFIG_RTE_EAL_ALLOW_INV_SOCKET_ID=n CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n CONFIG_RTE_EAL_IGB_UIO=n CONFIG_RTE_EAL_VFIO=n CONFIG_RTE_MAX_VFIO_GROUPS=64 +CONFIG_RTE_MAX_VFIO_CONTAINERS=64 CONFIG_RTE_MALLOC_DEBUG=n CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_USE_LIBBSD=n +# Use WFE instructions to implement the rte_wait_for_equal_xxx APIs, +# calling these APIs put the cores in low power state while waiting +# for the memory address to become equal to the expected value. +# This is supported only by aarch64. +CONFIG_RTE_ARM_USE_WFE=n # # Recognize/ignore the AVX/AVX512 CPU flags for performance/power testing. @@ -114,6 +125,9 @@ CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n CONFIG_RTE_ENABLE_AVX=y CONFIG_RTE_ENABLE_AVX512=n +# Use ARM LSE ATOMIC instructions +CONFIG_RTE_ARM_FEATURE_ATOMICS=n + # Default driver path (or "" to disable) CONFIG_RTE_EAL_PMD_PATH="" @@ -142,7 +156,7 @@ CONFIG_RTE_MAX_QUEUES_PER_PORT=1024 CONFIG_RTE_LIBRTE_IEEE1588=n CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16 CONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y -CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n +CONFIG_RTE_ETHDEV_PROFILE_WITH_VTUNE=n # # Turn off Tx preparation stage @@ -152,6 +166,16 @@ CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n # CONFIG_RTE_ETHDEV_TX_PREPARE_NOOP=n +# +# Common libraries, before Bus/PMDs +# +CONFIG_RTE_LIBRTE_COMMON_DPAAX=n + +# +# Compile the Intel FPGA bus +# +CONFIG_RTE_LIBRTE_IFPGA_BUS=y + # # Compile PCI bus driver # @@ -172,6 +196,17 @@ CONFIG_RTE_LIBRTE_ARK_DEBUG_TX=n CONFIG_RTE_LIBRTE_ARK_DEBUG_STATS=n CONFIG_RTE_LIBRTE_ARK_DEBUG_TRACE=n +# +# Compile Aquantia Atlantic PMD driver +# +CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y + +# +# Compile AMD PMD +# +CONFIG_RTE_LIBRTE_AXGBE_PMD=y +CONFIG_RTE_LIBRTE_AXGBE_PMD_DEBUG=n + # # Compile burst-oriented Broadcom PMD driver # @@ -185,22 +220,23 @@ CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC=n # Compile burst-oriented Broadcom BNXT PMD driver # CONFIG_RTE_LIBRTE_BNXT_PMD=y +CONFIG_RTE_LIBRTE_BNXT_PMD_SYSTEM=n # # Compile burst-oriented Chelsio Terminator (CXGBE) PMD # CONFIG_RTE_LIBRTE_CXGBE_PMD=y -CONFIG_RTE_LIBRTE_CXGBE_DEBUG=n -CONFIG_RTE_LIBRTE_CXGBE_DEBUG_REG=n -CONFIG_RTE_LIBRTE_CXGBE_DEBUG_MBOX=n -CONFIG_RTE_LIBRTE_CXGBE_DEBUG_TX=n -CONFIG_RTE_LIBRTE_CXGBE_DEBUG_RX=n -CONFIG_RTE_LIBRTE_CXGBE_TPUT=y + +# +# Compile burst-oriented NXP PFE PMD driver +# +CONFIG_RTE_LIBRTE_PFE_PMD=n # NXP DPAA Bus CONFIG_RTE_LIBRTE_DPAA_BUS=n CONFIG_RTE_LIBRTE_DPAA_MEMPOOL=n CONFIG_RTE_LIBRTE_DPAA_PMD=n +CONFIG_RTE_LIBRTE_DPAA_HWDEBUG=n # # Compile NXP DPAA2 FSL-MC Bus @@ -217,11 +253,12 @@ CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=y # Compile burst-oriented NXP DPAA2 PMD driver # CONFIG_RTE_LIBRTE_DPAA2_PMD=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT=n CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_RX=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX_FREE=n + +# +# Compile NXP ENETC PMD Driver +# +CONFIG_RTE_LIBRTE_ENETC_PMD=n # # Compile burst-oriented Amazon ENA PMD driver @@ -247,6 +284,21 @@ CONFIG_RTE_LIBRTE_E1000_DEBUG_TX=n CONFIG_RTE_LIBRTE_E1000_DEBUG_TX_FREE=n CONFIG_RTE_LIBRTE_E1000_PF_DISABLE_STRIP_CRC=n +# +# Compile burst-oriented HINIC PMD driver +# +CONFIG_RTE_LIBRTE_HINIC_PMD=n + +# +# Compile burst-oriented HNS3 PMD driver +# +CONFIG_RTE_LIBRTE_HNS3_PMD=n + +# +# Compile Pensando IONIC PMD driver +# +CONFIG_RTE_LIBRTE_IONIC_PMD=y + # # Compile burst-oriented IXGBE PMD driver # @@ -255,7 +307,6 @@ CONFIG_RTE_LIBRTE_IXGBE_DEBUG_RX=n CONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX=n CONFIG_RTE_LIBRTE_IXGBE_DEBUG_TX_FREE=n CONFIG_RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC=n -CONFIG_RTE_IXGBE_INC_VECTOR=y CONFIG_RTE_LIBRTE_IXGBE_BYPASS=n # @@ -270,8 +321,6 @@ CONFIG_RTE_LIBRTE_I40E_INC_VECTOR=y CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF=64 CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4 -# interval up to 8160 us, aligned to 2 (or default value) -CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1 # # Compile burst-oriented FM10K PMD @@ -284,29 +333,62 @@ CONFIG_RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE=y CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR=y # -# Compile burst-oriented AVF PMD driver +# Compile burst-oriented ICE PMD driver +# +CONFIG_RTE_LIBRTE_ICE_PMD=y +CONFIG_RTE_LIBRTE_ICE_DEBUG_RX=n +CONFIG_RTE_LIBRTE_ICE_DEBUG_TX=n +CONFIG_RTE_LIBRTE_ICE_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=n + +# Compile burst-oriented IAVF PMD driver +# +CONFIG_RTE_LIBRTE_IAVF_PMD=y +CONFIG_RTE_LIBRTE_IAVF_DEBUG_TX=n +CONFIG_RTE_LIBRTE_IAVF_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_IAVF_DEBUG_RX=n +CONFIG_RTE_LIBRTE_IAVF_DEBUG_DUMP_DESC=n +CONFIG_RTE_LIBRTE_IAVF_16BYTE_RX_DESC=n +# +# Compile burst-oriented IPN3KE PMD driver +# +CONFIG_RTE_LIBRTE_IPN3KE_PMD=n + +# +# Compile burst-oriented IGC PMD drivers # -CONFIG_RTE_LIBRTE_AVF_PMD=y -CONFIG_RTE_LIBRTE_AVF_INC_VECTOR=y -CONFIG_RTE_LIBRTE_AVF_DEBUG_TX=n -CONFIG_RTE_LIBRTE_AVF_DEBUG_TX_FREE=n -CONFIG_RTE_LIBRTE_AVF_DEBUG_RX=n -CONFIG_RTE_LIBRTE_AVF_16BYTE_RX_DESC=n +CONFIG_RTE_LIBRTE_IGC_PMD=y +CONFIG_RTE_LIBRTE_IGC_DEBUG_RX=n +CONFIG_RTE_LIBRTE_IGC_DEBUG_TX=n # # Compile burst-oriented Mellanox ConnectX-3 (MLX4) PMD # CONFIG_RTE_LIBRTE_MLX4_PMD=n CONFIG_RTE_LIBRTE_MLX4_DEBUG=n -CONFIG_RTE_LIBRTE_MLX4_DLOPEN_DEPS=n -CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8 # -# Compile burst-oriented Mellanox ConnectX-4 & ConnectX-5 (MLX5) PMD +# Compile burst-oriented Mellanox ConnectX-4, ConnectX-5, +# ConnectX-6 & BlueField (MLX5) PMD # CONFIG_RTE_LIBRTE_MLX5_PMD=n CONFIG_RTE_LIBRTE_MLX5_DEBUG=n -CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE=8 + +# +# Compile regex-oriented Mellanox PMD +# +CONFIG_RTE_LIBRTE_MLX5_REGEX_PMD=n + +# +# Compile vdpa-oriented Mellanox ConnectX-6 & BlueField (MLX5) PMD +# +CONFIG_RTE_LIBRTE_MLX5_VDPA_PMD=n + +# Linking method for mlx4/5 dependency on ibverbs and related libraries +# Default linking is dynamic by linker. +# Other options are: dynamic by dlopen at run-time, or statically embedded. +CONFIG_RTE_IBVERBS_LINK_DLOPEN=n +CONFIG_RTE_IBVERBS_LINK_STATIC=n # # Compile burst-oriented Netronome NFP PMD driver @@ -334,11 +416,11 @@ CONFIG_RTE_LIBRTE_SFC_EFX_DEBUG=n # Compile software PMD backed by SZEDATA2 device # CONFIG_RTE_LIBRTE_PMD_SZEDATA2=n + +# +# Compile software PMD backed by NFB device # -# Defines firmware type address space. -# See documentation for supported values. -# Other values raise compile time error. -CONFIG_RTE_LIBRTE_PMD_SZEDATA2_AS=0 +CONFIG_RTE_LIBRTE_NFB_PMD=n # # Compile burst-oriented Cavium Thunderx NICVF PMD driver @@ -361,6 +443,11 @@ CONFIG_RTE_LIBRTE_LIO_DEBUG_REGS=n # CONFIG_RTE_LIBRTE_OCTEONTX_PMD=y +# +# Compile burst-oriented Marvell OCTEON TX2 network PMD driver +# +CONFIG_RTE_LIBRTE_OCTEONTX2_PMD=y + # # Compile WRS accelerated virtual port (AVP) guest PMD driver # @@ -395,6 +482,16 @@ CONFIG_RTE_LIBRTE_VMXNET3_DEBUG_TX_FREE=n # CONFIG_RTE_LIBRTE_PMD_AF_PACKET=n +# +# Compile software PMD backed by AF_XDP sockets (Linux only) +# +CONFIG_RTE_LIBRTE_PMD_AF_XDP=n + +# +# Compile Memory Interface PMD driver (Linux only) +# +CONFIG_RTE_LIBRTE_PMD_MEMIF=n + # # Compile link bonding PMD library # @@ -410,7 +507,25 @@ CONFIG_RTE_LIBRTE_PMD_FAILSAFE=y # # Compile Marvell PMD driver # -CONFIG_RTE_LIBRTE_MRVL_PMD=n +CONFIG_RTE_LIBRTE_MVPP2_PMD=n + +# +# Compile Marvell MVNETA PMD driver +# +CONFIG_RTE_LIBRTE_MVNETA_PMD=n + +# +# Compile support for VMBus library +# +CONFIG_RTE_LIBRTE_VMBUS=n + +# +# Compile native PMD for Hyper-V/Azure +# +CONFIG_RTE_LIBRTE_NETVSC_PMD=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_RX=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_TX=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_DUMP=n # # Compile virtual device driver for NetVSC on Hyper-V/Azure @@ -437,7 +552,7 @@ CONFIG_RTE_PMD_RING_MAX_TX_RINGS=16 # # Compile SOFTNIC PMD # -CONFIG_RTE_LIBRTE_PMD_SOFTNIC=y +CONFIG_RTE_LIBRTE_PMD_SOFTNIC=n # # Compile the TAP PMD @@ -454,7 +569,11 @@ CONFIG_RTE_PMD_PACKET_PREFETCH=y # EXPERIMENTAL: API may change without prior notice # CONFIG_RTE_LIBRTE_BBDEV=y +CONFIG_RTE_LIBRTE_BBDEV_DEBUG=n CONFIG_RTE_BBDEV_MAX_DEVS=128 +CONFIG_RTE_BBDEV_OFFLOAD_COST=y +CONFIG_RTE_BBDEV_SDK_AVX2=n +CONFIG_RTE_BBDEV_SDK_AVX512=n # # Compile PMD for NULL bbdev device @@ -464,68 +583,91 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_NULL=y # # Compile PMD for turbo software bbdev device # -CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=n +CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=y + +# +# Compile PMD for Intel FPGA LTE FEC bbdev device +# +CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC=y + +# +# Compile PMD for Intel FPGA 5GNR FEC bbdev device +# +CONFIG_RTE_LIBRTE_PMD_BBDEV_FPGA_5GNR_FEC=y # # Compile generic crypto device library # CONFIG_RTE_LIBRTE_CRYPTODEV=y -CONFIG_RTE_LIBRTE_CRYPTODEV_DEBUG=n CONFIG_RTE_CRYPTO_MAX_DEVS=64 # # Compile PMD for ARMv8 Crypto device # CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO=n -CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO_DEBUG=n + +# +# Compile NXP CAAM JR crypto Driver +# +CONFIG_RTE_LIBRTE_PMD_CAAM_JR=n +CONFIG_RTE_LIBRTE_PMD_CAAM_JR_BE=n # # Compile NXP DPAA2 crypto sec driver for CAAM HW # CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=n -CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n -CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n -CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n # # NXP DPAA caam - crypto driver # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n -CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_INIT=n -CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_DRIVER=n -CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_RX=n +CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4 # -# Compile PMD for QuickAssist based devices +# Compile PMD for Cavium OCTEON TX crypto device # -CONFIG_RTE_LIBRTE_PMD_QAT=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_INIT=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_TX=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_RX=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_DRIVER=n +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y + # -# Number of sessions to create in the session memory pool -# on a single QuickAssist device. +# Compile PMD for Marvell OCTEON TX2 crypto device # -CONFIG_RTE_QAT_PMD_MAX_NB_SESSIONS=2048 +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y + +# +# Compile PMD for QuickAssist based devices - see docs for details +# +CONFIG_RTE_LIBRTE_PMD_QAT=y +CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n +CONFIG_RTE_LIBRTE_PMD_QAT_ASYM=n +# +# Max. number of QuickAssist devices, which can be detected and attached +# +CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48 +CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536 + +# +# Compile PMD for virtio crypto devices +# +CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO=y +# +# Number of maximum virtio crypto devices +# +CONFIG_RTE_MAX_VIRTIO_CRYPTO=32 # # Compile PMD for AESNI backed device # CONFIG_RTE_LIBRTE_PMD_AESNI_MB=n -CONFIG_RTE_LIBRTE_PMD_AESNI_MB_DEBUG=n # # Compile PMD for Software backed device # CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -CONFIG_RTE_LIBRTE_PMD_OPENSSL_DEBUG=n # # Compile PMD for AESNI GCM device # CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=n -CONFIG_RTE_LIBRTE_PMD_AESNI_GCM_DEBUG=n # # Compile PMD for SNOW 3G device @@ -537,36 +679,74 @@ CONFIG_RTE_LIBRTE_PMD_SNOW3G_DEBUG=n # Compile PMD for KASUMI device # CONFIG_RTE_LIBRTE_PMD_KASUMI=n -CONFIG_RTE_LIBRTE_PMD_KASUMI_DEBUG=n # # Compile PMD for ZUC device # CONFIG_RTE_LIBRTE_PMD_ZUC=n -CONFIG_RTE_LIBRTE_PMD_ZUC_DEBUG=n -# # Compile PMD for Crypto Scheduler device # CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y -CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n # # Compile PMD for NULL Crypto device # CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y +# +# Compile PMD for AMD CCP crypto device +# +CONFIG_RTE_LIBRTE_PMD_CCP=n + # # Compile PMD for Marvell Crypto device # -CONFIG_RTE_LIBRTE_PMD_MRVL_CRYPTO=n -CONFIG_RTE_LIBRTE_PMD_MRVL_CRYPTO_DEBUG=n +CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n + +# +# Compile PMD for NITROX crypto device +# +CONFIG_RTE_LIBRTE_PMD_NITROX=y # # Compile generic security library # CONFIG_RTE_LIBRTE_SECURITY=y +# +# Compile generic compression device library +# +CONFIG_RTE_LIBRTE_COMPRESSDEV=y +CONFIG_RTE_COMPRESS_MAX_DEVS=64 + +# +# Compile compressdev unit test +# +CONFIG_RTE_COMPRESSDEV_TEST=n + +# +# Compile PMD for Octeontx ZIPVF compression device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF=y + +# +# Compile PMD for ISA-L compression device +# +CONFIG_RTE_LIBRTE_PMD_ISAL=n + +# +# Compile PMD for ZLIB compression device +# +CONFIG_RTE_LIBRTE_PMD_ZLIB=n + +# +# Compile RegEx device support +# +CONFIG_RTE_LIBRTE_REGEXDEV=y +CONFIG_RTE_LIBRTE_REGEXDEV_DEBUG=n +CONFIG_RTE_MAX_REGEXDEV_DEVS=32 + # # Compile generic event device library # @@ -574,6 +754,10 @@ CONFIG_RTE_LIBRTE_EVENTDEV=y CONFIG_RTE_LIBRTE_EVENTDEV_DEBUG=n CONFIG_RTE_EVENT_MAX_DEVS=16 CONFIG_RTE_EVENT_MAX_QUEUES_PER_DEV=64 +CONFIG_RTE_EVENT_TIMER_ADAPTER_NUM_MAX=32 +CONFIG_RTE_EVENT_ETH_INTR_RING_SIZE=1024 +CONFIG_RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE=32 +CONFIG_RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE=32 # # Compile PMD for skeleton event device @@ -586,11 +770,21 @@ CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV_DEBUG=n # CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV=y +# +# Compile PMD for distributed software event device +# +CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV=y + # # Compile PMD for octeontx sso event device # CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF=y +# +# Compile PMD for octeontx2 sso event device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV=y + # # Compile PMD for OPDL event device # @@ -611,14 +805,53 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=n # EXPERIMENTAL: API may change without prior notice # CONFIG_RTE_LIBRTE_RAWDEV=y -CONFIG_RTE_RAWDEV_MAX_DEVS=10 +CONFIG_RTE_RAWDEV_MAX_DEVS=64 CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV=y +# +# Compile PMD for NXP DPAA2 CMDIF raw device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV=n + +# +# Compile PMD for NXP DPAA2 QDMA raw device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n + +# +# Compile PMD for Intel FPGA raw device +# +CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=n + +# +# Compile PMD for Intel IOAT raw device +# +CONFIG_RTE_LIBRTE_PMD_IOAT_RAWDEV=y + +# +# Compile PMD for octeontx2 DMA raw device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV=y + +# +# Compile PMD for octeontx2 EP raw device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EP_RAWDEV=y + +# +# Compile PMD for NTB raw device +# +CONFIG_RTE_LIBRTE_PMD_NTB_RAWDEV=y + # # Compile librte_ring # CONFIG_RTE_LIBRTE_RING=y -CONFIG_RTE_RING_USE_C11_MEM_MODEL=n + +# +# Compile librte_stack +# +CONFIG_RTE_LIBRTE_STACK=y # # Compile librte_mempool @@ -630,6 +863,8 @@ CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=n # # Compile Mempool drivers # +CONFIG_RTE_DRIVER_MEMPOOL_BUCKET=y +CONFIG_RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB=64 CONFIG_RTE_DRIVER_MEMPOOL_RING=y CONFIG_RTE_DRIVER_MEMPOOL_STACK=y @@ -638,6 +873,11 @@ CONFIG_RTE_DRIVER_MEMPOOL_STACK=y # CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOOL=y +# +# Compile PMD for octeontx2 npa mempool device +# +CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL=y + # # Compile librte_mbuf # @@ -700,6 +940,28 @@ CONFIG_RTE_LIBRTE_BITRATE=y # CONFIG_RTE_LIBRTE_LATENCY_STATS=y +# +# Compile librte_telemetry legacy support +# +CONFIG_RTE_LIBRTE_TELEMETRY=n + +# +# Compile librte_rcu +# +CONFIG_RTE_LIBRTE_RCU=y +CONFIG_RTE_LIBRTE_RCU_DEBUG=n + +# +# Compile librte_rib +# +CONFIG_RTE_LIBRTE_RIB=y + +# +# Compile librte_fib +# +CONFIG_RTE_LIBRTE_FIB=y +CONFIG_RTE_LIBRTE_FIB_DEBUG=n + # # Compile librte_lpm # @@ -798,7 +1060,6 @@ CONFIG_RTE_PIPELINE_STATS_COLLECT=n CONFIG_RTE_LIBRTE_KNI=n CONFIG_RTE_LIBRTE_PMD_KNI=n CONFIG_RTE_KNI_KMOD=n -CONFIG_RTE_KNI_KMOD_ETHTOOL=n CONFIG_RTE_KNI_PREEMPT_DEFAULT=y # @@ -819,6 +1080,37 @@ CONFIG_RTE_LIBRTE_VHOST_DEBUG=n # CONFIG_RTE_LIBRTE_PMD_VHOST=n +# +# Compile IFC driver +# To compile, CONFIG_RTE_LIBRTE_VHOST and CONFIG_RTE_EAL_VFIO +# should be enabled. +# +CONFIG_RTE_LIBRTE_IFC_PMD=n + +# +# Compile librte_bpf +# +CONFIG_RTE_LIBRTE_BPF=y +# allow load BPF from ELF files (requires libelf) +CONFIG_RTE_LIBRTE_BPF_ELF=n + +# +# Compile librte_ipsec +# +CONFIG_RTE_LIBRTE_IPSEC=y + +# +# Compile librte_graph +# +CONFIG_RTE_LIBRTE_GRAPH=y +CONFIG_RTE_GRAPH_BURST_SIZE=256 +CONFIG_RTE_LIBRTE_GRAPH_STATS=y + +# +# Compile librte_node +# +CONFIG_RTE_LIBRTE_NODE=y + # # Compile the test application # @@ -837,11 +1129,21 @@ CONFIG_RTE_TEST_PMD=y CONFIG_RTE_TEST_PMD_RECORD_CORE_CYCLES=n CONFIG_RTE_TEST_PMD_RECORD_BURST_STATS=n +# +# Compile the rte flow perf application +# +CONFIG_RTE_TEST_FLOW_PERF=y + # # Compile the bbdev test application # CONFIG_RTE_TEST_BBDEV=y +# +# Compile the compression performance application +# +CONFIG_RTE_APP_COMPRESS_PERF=y + # # Compile the crypto performance application #