X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fbaseband%2Ffpga_5gnr_fec%2Frte_fpga_5gnr_fec.c;h=930718cd47a7043d11907c15f62da95a268eb140;hb=3cc6ecfdfe85d2577fef30e1791bb7534e3d60b3;hp=63d11ad19e746e46fbfbdd4ef8394f376b718215;hpb=4d9199e3e9cb21cfae288ef44db2ea7f38506fb3;p=dpdk.git diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 63d11ad19e..930718cd47 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -23,8 +23,11 @@ #include "fpga_5gnr_fec.h" #include "rte_pmd_fpga_5gnr_fec.h" -/* 5GNR SW PMD logging ID */ -static int fpga_5gnr_fec_logtype; +#ifdef RTE_LIBRTE_BBDEV_DEBUG +RTE_LOG_REGISTER(fpga_5gnr_fec_logtype, pmd.bb.fpga_5gnr_fec, DEBUG); +#else +RTE_LOG_REGISTER(fpga_5gnr_fec_logtype, pmd.bb.fpga_5gnr_fec, NOTICE); +#endif #ifdef RTE_LIBRTE_BBDEV_DEBUG @@ -325,6 +328,7 @@ fpga_dev_info_get(struct rte_bbdev *dev, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK | + RTE_BBDEV_LDPC_DEC_INTERRUPTS | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS, .llr_size = 6, .llr_decimals = 2, @@ -636,14 +640,152 @@ fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) return 0; } +static inline uint16_t +get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx) +{ + uint16_t queue_id; + + for (queue_id = 0; queue_id < data->num_queues; ++queue_id) { + struct fpga_queue *q = data->queues[queue_id].queue_private; + if (q != NULL && q->q_idx == q_idx) + return queue_id; + } + + return -1; +} + +/* Interrupt handler triggered by FPGA dev for handling specific interrupt */ +static void +fpga_dev_interrupt_handler(void *cb_arg) +{ + struct rte_bbdev *dev = cb_arg; + struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private; + struct fpga_queue *q; + uint64_t ring_head; + uint64_t q_idx; + uint16_t queue_id; + uint8_t i; + + /* Scan queue assigned to this device */ + for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) { + q_idx = 1ULL << i; + if (fpga_dev->q_bound_bit_map & q_idx) { + queue_id = get_queue_id(dev->data, i); + if (queue_id == (uint16_t) -1) + continue; + + /* Check if completion head was changed */ + q = dev->data->queues[queue_id].queue_private; + ring_head = *q->ring_head_addr; + if (q->shadow_completion_head != ring_head && + q->irq_enable == 1) { + q->shadow_completion_head = ring_head; + rte_bbdev_pmd_callback_process( + dev, + RTE_BBDEV_EVENT_DEQUEUE, + &queue_id); + } + } + } +} + +static int +fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + + if (!rte_intr_cap_multiple(dev->intr_handle)) + return -ENOTSUP; + + q->irq_enable = 1; + + return 0; +} + +static int +fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + q->irq_enable = 0; + + return 0; +} + +static int +fpga_intr_enable(struct rte_bbdev *dev) +{ + int ret; + uint8_t i; + + if (!rte_intr_cap_multiple(dev->intr_handle)) { + rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)", + dev->data->name); + return -ENOTSUP; + } + + /* Create event file descriptors for each of 64 queue. Event fds will be + * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where + * the IRQ number is a direct translation to the queue number. + * + * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable() + * mapped the first IRQ to already created interrupt event file + * descriptor (intr_handle->fd). + */ + if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) { + rte_bbdev_log(ERR, "Failed to create fds for %u queues", + dev->data->num_queues); + return -1; + } + + /* TODO Each event file descriptor is overwritten by interrupt event + * file descriptor. That descriptor is added to epoll observed list. + * It ensures that callback function assigned to that descriptor will + * invoked when any FPGA queue issues interrupt. + */ + for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) + dev->intr_handle->efds[i] = dev->intr_handle->fd; + + if (!dev->intr_handle->intr_vec) { + dev->intr_handle->intr_vec = rte_zmalloc("intr_vec", + dev->data->num_queues * sizeof(int), 0); + if (!dev->intr_handle->intr_vec) { + rte_bbdev_log(ERR, "Failed to allocate %u vectors", + dev->data->num_queues); + return -ENOMEM; + } + } + + ret = rte_intr_enable(dev->intr_handle); + if (ret < 0) { + rte_bbdev_log(ERR, + "Couldn't enable interrupts for device: %s", + dev->data->name); + return ret; + } + + ret = rte_intr_callback_register(dev->intr_handle, + fpga_dev_interrupt_handler, dev); + if (ret < 0) { + rte_bbdev_log(ERR, + "Couldn't register interrupt callback for device: %s", + dev->data->name); + return ret; + } + + return 0; +} + static const struct rte_bbdev_ops fpga_ops = { .setup_queues = fpga_setup_queues, + .intr_enable = fpga_intr_enable, .close = fpga_dev_close, .info_get = fpga_dev_info_get, .queue_setup = fpga_queue_setup, .queue_stop = fpga_queue_stop, .queue_start = fpga_queue_start, .queue_release = fpga_queue_release, + .queue_intr_enable = fpga_queue_intr_enable, + .queue_intr_disable = fpga_queue_intr_disable }; static inline void @@ -2035,14 +2177,3 @@ RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME, RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver); RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME, pci_id_fpga_5gnr_fec_vf_map); - -RTE_INIT(fpga_5gnr_fec_init_log) -{ - fpga_5gnr_fec_logtype = rte_log_register("pmd.bb.fpga_5gnr_fec"); - if (fpga_5gnr_fec_logtype >= 0) -#ifdef RTE_LIBRTE_BBDEV_DEBUG - rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG); -#else - rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE); -#endif -}