X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fcommon%2Fmlx5%2Fmlx5_devx_cmds.h;h=9c9d0862e80a56fc82eeb31dce45cda8a02a5ea6;hb=65be2ca6e0256836c0a74bfa27cc458f1f80b44d;hp=660e7d9c7c1b7132bfe530788970ddbd502c9385;hpb=1a2d8c3ffe50278ce8100837de2ca3f725ec4c27;p=dpdk.git diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 660e7d9c7c..9c9d0862e8 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -5,18 +5,11 @@ #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_ #define RTE_PMD_MLX5_DEVX_CMDS_H_ -#include "mlx5_glue.h" -#include "mlx5_prm.h" #include +#include -/* - * Defines the amount of retries to allocate the first UAR in the page. - * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as - * UAR base address if UAR was not the first object in the UAR page. - * It caused the PMD failure and we should try to get another UAR - * till we get the first one with non-NULL base address returned. - */ -#define MLX5_ALLOC_UAR_RETRY 32 +#include "mlx5_glue.h" +#include "mlx5_prm.h" /* This is limitation of libibverbs: in length variable type is u16. */ #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \ @@ -89,6 +82,69 @@ struct mlx5_hca_vdpa_attr { uint64_t doorbell_bar_offset; }; +struct mlx5_hca_flow_attr { + uint32_t tunnel_header_0_1; + uint32_t tunnel_header_2_3; +}; + +/** + * Accumulate port PARSE_GRAPH_NODE capabilities from + * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables + */ +__extension__ +struct mlx5_hca_flex_attr { + uint32_t node_in; + uint32_t node_out; + uint16_t header_length_mode; + uint16_t sample_offset_mode; + uint8_t max_num_arc_in; + uint8_t max_num_arc_out; + uint8_t max_num_sample; + uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ + uint8_t sample_id_in_out:1; + uint16_t max_base_header_length; + uint8_t max_sample_base_offset; + uint16_t max_next_header_offset; + uint8_t header_length_mask_width; +}; + +/* ISO C restricts enumerator values to range of 'int' */ +__extension__ +enum { + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12), + PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31) +}; + +enum { + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0), + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1), + PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2) +}; + +/* + * DWORD shift is the base for calculating header_length_field_mask + * value in the MLX5_GRAPH_NODE_LEN_FIELD mode. + */ +#define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02 + +static inline uint32_t +mlx5_hca_parse_graph_node_base_hdr_len_mask + (const struct mlx5_hca_flex_attr *attr) +{ + return (1 << attr->header_length_mask_width) - 1; +} + /* HCA supports this number of time periods for LRO. */ #define MLX5_LRO_NUM_SUPP_PERIODS 4 @@ -102,14 +158,23 @@ struct mlx5_hca_attr { uint32_t eth_net_offloads:1; uint32_t eth_virt:1; uint32_t wqe_vlan_insert:1; + uint32_t csum_cap:1; + uint32_t vlan_cap:1; uint32_t wqe_inline_mode:2; uint32_t vport_inline_mode:3; uint32_t tunnel_stateless_geneve_rx:1; uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */ uint32_t tunnel_stateless_gtp:1; + uint32_t max_lso_cap; + uint32_t scatter_fcs:1; uint32_t lro_cap:1; uint32_t tunnel_lro_gre:1; uint32_t tunnel_lro_vxlan:1; + uint32_t tunnel_stateless_gre:1; + uint32_t tunnel_stateless_vxlan:1; + uint32_t swp:1; + uint32_t swp_csum:1; + uint32_t swp_lso:1; uint32_t lro_max_msg_sz_mode:2; uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; uint16_t lro_min_mss_size; @@ -135,9 +200,12 @@ struct mlx5_hca_attr { uint32_t roce:1; uint32_t rq_ts_format:2; uint32_t sq_ts_format:2; + uint32_t steering_format_version:4; uint32_t qp_ts_format:2; - uint32_t regex:1; + uint32_t regexp_params:1; + uint32_t regexp_version:3; uint32_t reg_c_preserve:1; + uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */ uint32_t crypto:1; /* Crypto engine is supported. */ uint32_t aes_xts:1; /* AES-XTS crypto is supported. */ uint32_t dek:1; /* General obj type DEK is supported. */ @@ -146,12 +214,17 @@ struct mlx5_hca_attr { uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */ uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; + uint32_t inner_ipv4_ihl:1; + uint32_t outer_ipv4_ihl:1; uint32_t geneve_tlv_opt; uint32_t cqe_compression:1; uint32_t mini_cqe_resp_flow_tag:1; uint32_t mini_cqe_resp_l3_l4_tag:1; + uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */ struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; + struct mlx5_hca_flow_attr flow; + struct mlx5_hca_flex_attr flex; int log_max_qp_sz; int log_max_cq_sz; int log_max_qp; @@ -161,9 +234,14 @@ struct mlx5_hca_attr { uint32_t log_max_srq; uint32_t log_max_srq_sz; uint32_t rss_ind_tbl_cap; - uint32_t mmo_dma_en:1; - uint32_t mmo_compress_en:1; - uint32_t mmo_decompress_en:1; + uint32_t mmo_dma_sq_en:1; + uint32_t mmo_compress_sq_en:1; + uint32_t mmo_decompress_sq_en:1; + uint32_t mmo_dma_qp_en:1; + uint32_t mmo_compress_qp_en:1; + uint32_t mmo_decompress_qp_en:1; + uint32_t mmo_regex_qp_en:1; + uint32_t mmo_regex_sq_en:1; uint32_t compress_min_block_size:4; uint32_t log_max_mmo_dma:5; uint32_t log_max_mmo_compress:5; @@ -172,6 +250,15 @@ struct mlx5_hca_attr { uint32_t umr_indirect_mkey_disabled:1; }; +/* LAG Context. */ +struct mlx5_devx_lag_context { + uint32_t fdb_selection_mode:1; + uint32_t port_select_mode:3; + uint32_t lag_state:3; + uint32_t tx_remap_affinity_1:4; + uint32_t tx_remap_affinity_2:4; +}; + struct mlx5_devx_wq_attr { uint32_t wq_type:4; uint32_t wq_signature:1; @@ -385,6 +472,8 @@ struct mlx5_devx_qp_attr { uint64_t dbr_address; uint32_t wq_umem_id; uint64_t wq_umem_offset; + uint32_t user_index:24; + uint32_t mmo:1; }; struct mlx5_devx_virtio_q_couners_attr { @@ -558,8 +647,9 @@ int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, uint32_t ids[], uint32_t num); __rte_internal -struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx, - struct mlx5_devx_graph_node_attr *data); +struct mlx5_devx_obj * +mlx5_devx_cmd_create_flex_parser(void *ctx, + struct mlx5_devx_graph_node_attr *data); __rte_internal int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, @@ -614,6 +704,10 @@ struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx); __rte_internal int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear, uint32_t *out_of_buffers); +__rte_internal +struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx, + uint32_t pd, uint32_t log_obj_size); + /** * Create general object of type FLOW_METER_ASO using DevX API.. * @@ -650,4 +744,8 @@ struct mlx5_devx_obj * mlx5_devx_cmd_create_crypto_login_obj(void *ctx, struct mlx5_devx_crypto_login_attr *attr); +__rte_internal +int +mlx5_devx_cmd_query_lag(void *ctx, + struct mlx5_devx_lag_context *lag_ctx); #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */