X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fevent%2Focteontx%2Fssovf_evdev.h;h=10163151cdf982f2d4f3fa0f9d408d020bd39c35;hb=3ca55dac6d2c631dc98d4e0d1de99e8117d5c1ab;hp=aa5acf246faf16c5c5113381fbb830b6b095fe57;hpb=cf55f04a0c99fc8571afbb7a1a3133af9d33c0e1;p=dpdk.git

diff --git a/drivers/event/octeontx/ssovf_evdev.h b/drivers/event/octeontx/ssovf_evdev.h
index aa5acf246f..10163151cd 100644
--- a/drivers/event/octeontx/ssovf_evdev.h
+++ b/drivers/event/octeontx/ssovf_evdev.h
@@ -86,8 +86,6 @@
 #define SSO_GRP_GET_PRIORITY              0x7
 #define SSO_GRP_SET_PRIORITY              0x8
 
-#define SSOVF_SELFTEST_ARG               ("selftest")
-
 /*
  * In Cavium OCTEON TX SoC, all accesses to the device registers are
  * implictly strongly ordered. So, The relaxed version of IO operation is
@@ -146,6 +144,12 @@ struct ssovf_evdev {
 	uint32_t min_deq_timeout_ns;
 	uint32_t max_deq_timeout_ns;
 	int32_t max_num_events;
+	uint32_t available_events;
+	uint16_t rxq_pools;
+	uint64_t *rxq_pool_array;
+	uint8_t *rxq_pool_rcnt;
+	uint16_t tim_ring_cnt;
+	uint16_t *tim_ring_ids;
 } __rte_cache_aligned;
 
 /* Event port aka HWS */