X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fark%2Fark_ddm.h;h=84beeb063af9b9e226e2945d155106e6f8e0648f;hb=38e9762be16a8ff210e4c4e83bae8dfe7fb45984;hp=b37d1e090b610af4b1cfcf38ff21e89e57c09210;hpb=540914bc7ad88bae5ac5a4ea4acf4ddc5f4799e5;p=dpdk.git

diff --git a/drivers/net/ark/ark_ddm.h b/drivers/net/ark/ark_ddm.h
index b37d1e090b..84beeb063a 100644
--- a/drivers/net/ark/ark_ddm.h
+++ b/drivers/net/ark/ark_ddm.h
@@ -16,17 +16,22 @@
  * there is minimal documentation.
  */
 
-/* struct defining Tx meta data --  fixed in FPGA -- 16 bytes */
-struct ark_tx_meta {
+/* struct defining Tx meta data --  fixed in FPGA -- 8 bytes */
+union ark_tx_meta {
 	uint64_t physaddr;
-	uint32_t delta_ns;
-	uint16_t data_len;		/* of this MBUF */
+	struct {
+		uint32_t usermeta0;
+		uint32_t usermeta1;
+	};
+	struct {
+		uint16_t data_len;	/* of this MBUF */
 #define   ARK_DDM_EOP   0x01
 #define   ARK_DDM_SOP   0x02
-	uint8_t flags;		/* bit 0 indicates last mbuf in chain. */
-	uint8_t reserved[1];
-};
-
+		uint8_t  flags;
+		uint8_t  meta_cnt;
+		uint32_t user1;
+	};
+} __rte_packed;
 
 /*
  * DDM core hardware structures
@@ -34,14 +39,25 @@ struct ark_tx_meta {
  * structs will never be instantiated in ram memory
  */
 #define ARK_DDM_CFG 0x0000
-#define ARK_DDM_CONST 0xfacecafe
+/* Set unique HW ID for hardware version */
+#define ARK_DDM_MODID 0x204d4444
+#define ARK_DDM_MODVER 0x37313232
+
 struct ark_ddm_cfg_t {
+	union {
+		char id[4];
+		uint32_t idnum;
+	};
+	union {
+		char ver[4];
+		uint32_t vernum;
+		volatile uint32_t tlp_stats_clear;
+	};
 	uint32_t r0;
-	volatile uint32_t tlp_stats_clear;
-	uint32_t const0;
 	volatile uint32_t tag_max;
 	volatile uint32_t command;
-	volatile uint32_t stop_flushed;
+	uint32_t write_index_interval;	/* 4ns each */
+	volatile uint64_t qflow;
 };
 
 #define ARK_DDM_STATS 0x0020
@@ -51,34 +67,6 @@ struct ark_ddm_stats_t {
 	volatile uint64_t tx_mbuf_count;
 };
 
-#define ARK_DDM_MRDQ 0x0040
-struct ark_ddm_mrdq_t {
-	volatile uint32_t mrd_q1;
-	volatile uint32_t mrd_q2;
-	volatile uint32_t mrd_q3;
-	volatile uint32_t mrd_q4;
-	volatile uint32_t mrd_full;
-};
-
-#define ARK_DDM_CPLDQ 0x0068
-struct ark_ddm_cpldq_t {
-	volatile uint32_t cpld_q1;
-	volatile uint32_t cpld_q2;
-	volatile uint32_t cpld_q3;
-	volatile uint32_t cpld_q4;
-	volatile uint32_t cpld_full;
-};
-
-#define ARK_DDM_MRD_PS 0x0090
-struct ark_ddm_mrd_ps_t {
-	volatile uint32_t mrd_ps_min;
-	volatile uint32_t mrd_ps_max;
-	volatile uint32_t mrd_full_ps_min;
-	volatile uint32_t mrd_full_ps_max;
-	volatile uint32_t mrd_dw_ps_min;
-	volatile uint32_t mrd_dw_ps_max;
-};
-
 #define ARK_DDM_QUEUE_STATS 0x00a8
 struct ark_ddm_qstats_t {
 	volatile uint64_t byte_count;
@@ -86,20 +74,10 @@ struct ark_ddm_qstats_t {
 	volatile uint64_t mbuf_count;
 };
 
-#define ARK_DDM_CPLD_PS 0x00c0
-struct ark_ddm_cpld_ps_t {
-	volatile uint32_t cpld_ps_min;
-	volatile uint32_t cpld_ps_max;
-	volatile uint32_t cpld_full_ps_min;
-	volatile uint32_t cpld_full_ps_max;
-	volatile uint32_t cpld_dw_ps_min;
-	volatile uint32_t cpld_dw_ps_max;
-};
-
 #define ARK_DDM_SETUP  0x00e0
 struct ark_ddm_setup_t {
 	rte_iova_t cons_write_index_addr;
-	uint32_t write_index_interval;	/* 4ns each */
+	volatile uint32_t qcommand;
 	volatile uint32_t cons_index;
 };
 
@@ -110,39 +88,28 @@ struct ark_ddm_t {
 	struct ark_ddm_cfg_t cfg;
 	uint8_t reserved0[(ARK_DDM_STATS - ARK_DDM_CFG) -
 			  sizeof(struct ark_ddm_cfg_t)];
+
 	struct ark_ddm_stats_t stats;
-	uint8_t reserved1[(ARK_DDM_MRDQ - ARK_DDM_STATS) -
+	uint8_t reserved1[(ARK_DDM_QUEUE_STATS - ARK_DDM_STATS) -
 			  sizeof(struct ark_ddm_stats_t)];
-	struct ark_ddm_mrdq_t mrdq;
-	uint8_t reserved2[(ARK_DDM_CPLDQ - ARK_DDM_MRDQ) -
-			  sizeof(struct ark_ddm_mrdq_t)];
-	struct ark_ddm_cpldq_t cpldq;
-	uint8_t reserved3[(ARK_DDM_MRD_PS - ARK_DDM_CPLDQ) -
-			  sizeof(struct ark_ddm_cpldq_t)];
-	struct ark_ddm_mrd_ps_t mrd_ps;
+
 	struct ark_ddm_qstats_t queue_stats;
-	struct ark_ddm_cpld_ps_t cpld_ps;
-	uint8_t reserved5[(ARK_DDM_SETUP - ARK_DDM_CPLD_PS) -
-			  sizeof(struct ark_ddm_cpld_ps_t)];
+	uint8_t reserved5[(ARK_DDM_SETUP - ARK_DDM_QUEUE_STATS) -
+			  sizeof(struct ark_ddm_qstats_t)];
+
 	struct ark_ddm_setup_t setup;
 	uint8_t reserved_p[(ARK_DDM_EXPECTED_SIZE - ARK_DDM_SETUP) -
 			   sizeof(struct ark_ddm_setup_t)];
 };
 
-
 /* DDM function prototype */
 int ark_ddm_verify(struct ark_ddm_t *ddm);
-void ark_ddm_start(struct ark_ddm_t *ddm);
-int ark_ddm_stop(struct ark_ddm_t *ddm, const int wait);
-void ark_ddm_reset(struct ark_ddm_t *ddm);
 void ark_ddm_stats_reset(struct ark_ddm_t *ddm);
-void ark_ddm_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr,
-		   uint32_t interval);
+void ark_ddm_queue_setup(struct ark_ddm_t *ddm, rte_iova_t cons_addr);
 void ark_ddm_dump_stats(struct ark_ddm_t *ddm, const char *msg);
-void ark_ddm_dump(struct ark_ddm_t *ddm, const char *msg);
-int ark_ddm_is_stopped(struct ark_ddm_t *ddm);
 uint64_t ark_ddm_queue_byte_count(struct ark_ddm_t *ddm);
 uint64_t ark_ddm_queue_pkt_count(struct ark_ddm_t *ddm);
 void ark_ddm_queue_reset_stats(struct ark_ddm_t *ddm);
+void ark_ddm_queue_enable(struct ark_ddm_t *ddm, int enable);
 
 #endif