X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Faxgbe%2Faxgbe_common.h;h=fdb037dd5a8da9737f0f09e25efddedbee484a07;hb=6645b283eb66de465692b8c7563b7f5ecbe1cc67;hp=64c7a7fa18dd341163b36b5efb6d835c8c298095;hpb=7784d0d3d0d9807c3db1a786b0190e660ec3fd86;p=dpdk.git diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 64c7a7fa18..fdb037dd5a 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include @@ -842,6 +841,8 @@ #define PCS_V1_WINDOW_SELECT 0x03fc #define PCS_V2_WINDOW_DEF 0x9060 #define PCS_V2_WINDOW_SELECT 0x9064 +#define PCS_V2_RV_WINDOW_DEF 0x1060 +#define PCS_V2_RV_WINDOW_SELECT 0x1064 /* PCS register entry bit positions and sizes */ #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6 @@ -1247,6 +1248,10 @@ #define MDIO_VEND2_AN_STAT 0x8002 #endif +#ifndef MDIO_VEND2_PMA_CDR_CONTROL +#define MDIO_VEND2_PMA_CDR_CONTROL 0x8056 +#endif + #ifndef MDIO_CTRL1_SPEED1G #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100) #endif @@ -1293,6 +1298,11 @@ #define AXGBE_AN_CL37_PCS_MODE_BASEX 0x00 #define AXGBE_AN_CL37_PCS_MODE_SGMII 0x04 #define AXGBE_AN_CL37_TX_CONFIG_MASK 0x08 +#define AXGBE_AN_CL37_MII_CTRL_8BIT 0x0100 + +#define AXGBE_PMA_CDR_TRACK_EN_MASK 0x01 +#define AXGBE_PMA_CDR_TRACK_EN_OFF 0x00 +#define AXGBE_PMA_CDR_TRACK_EN_ON 0x01 /*generic*/ #define __iomem @@ -1344,9 +1354,9 @@ do { \ #define SET_BITS_LE(_var, _index, _width, _val) \ do { \ - (_var) &= rte_cpu_to_le_32(~(((0x1 << (_width)) - 1) << (_index)));\ + (_var) &= rte_cpu_to_le_32(~(((0x1U << (_width)) - 1) << (_index)));\ (_var) |= rte_cpu_to_le_32((((_val) & \ - ((0x1 << (_width)) - 1)) << (_index))); \ + ((0x1U << (_width)) - 1)) << (_index))); \ } while (0) /* Bit setting and getting macros based on register fields