X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fhns3%2Fhns3_dcb.h;h=cd8d0b7bc862827e26623b83899ba1f26e3ef8a3;hb=c9a63bb64e79ab5fa6b5bd298df5b5695067d1e5;hp=9ec4e704b3b0f91b2c614275edca7655a59f49fd;hpb=62e3ccc2b94c625d4b3ce55044b135c4ab0793db;p=dpdk.git

diff --git a/drivers/net/hns3/hns3_dcb.h b/drivers/net/hns3/hns3_dcb.h
index 9ec4e704b3..cd8d0b7bc8 100644
--- a/drivers/net/hns3/hns3_dcb.h
+++ b/drivers/net/hns3/hns3_dcb.h
@@ -1,10 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2018-2019 Hisilicon Limited.
+ * Copyright(c) 2018-2021 HiSilicon Limited.
  */
 
 #ifndef _HNS3_DCB_H_
 #define _HNS3_DCB_H_
 
+#include <stdint.h>
+
+#include "hns3_cmd.h"
+
+#define HNS3_ETHER_MAX_RATE		100000
+
 /* MAC Pause */
 #define HNS3_TX_MAC_PAUSE_EN_MSK	BIT(0)
 #define HNS3_RX_MAC_PAUSE_EN_MSK	BIT(1)
@@ -14,7 +20,7 @@
 
 /* SP or DWRR */
 #define HNS3_DCB_TX_SCHD_DWRR_MSK	BIT(0)
-#define HNS3_DCB_TX_SCHD_SP_MSK		(0xFE)
+#define HNS3_DCB_TX_SCHD_SP_MSK		0xFE
 
 enum hns3_shap_bucket {
 	HNS3_DCB_SHAP_C_BUCKET = 0,
@@ -24,16 +30,19 @@ enum hns3_shap_bucket {
 struct hns3_priority_weight_cmd {
 	uint8_t pri_id;
 	uint8_t dwrr;
+	uint8_t rsvd[22];
 };
 
 struct hns3_qs_weight_cmd {
 	uint16_t qs_id;
 	uint8_t dwrr;
+	uint8_t rsvd[21];
 };
 
 struct hns3_pg_weight_cmd {
 	uint8_t pg_id;
 	uint8_t dwrr;
+	uint8_t rsvd[22];
 };
 
 struct hns3_ets_tc_weight_cmd {
@@ -47,7 +56,14 @@ struct hns3_qs_to_pri_link_cmd {
 	uint16_t rsvd;
 	uint8_t priority;
 #define HNS3_DCB_QS_PRI_LINK_VLD_MSK	BIT(0)
+#define HNS3_DCB_QS_ID_L_MSK		GENMASK(9, 0)
+#define HNS3_DCB_QS_ID_L_S		0
+#define HNS3_DCB_QS_ID_H_MSK		GENMASK(14, 10)
+#define HNS3_DCB_QS_ID_H_S		10
+#define HNS3_DCB_QS_ID_H_EXT_S		11
+#define HNS3_DCB_QS_ID_H_EXT_MSK	GENMASK(15, 11)
 	uint8_t link_vld;
+	uint8_t rsvd1[18];
 };
 
 struct hns3_nq_to_qs_link_cmd {
@@ -55,6 +71,7 @@ struct hns3_nq_to_qs_link_cmd {
 	uint16_t rsvd;
 #define HNS3_DCB_Q_QS_LINK_VLD_MSK	BIT(10)
 	uint16_t qset_id;
+	uint8_t rsvd1[18];
 };
 
 #define HNS3_DCB_SHAP_IR_B_MSK  GENMASK(7, 0)
@@ -68,38 +85,66 @@ struct hns3_nq_to_qs_link_cmd {
 #define HNS3_DCB_SHAP_BS_S_MSK  GENMASK(25, 21)
 #define HNS3_DCB_SHAP_BS_S_LSH	21
 
+/*
+ * For more flexible selection of shapping algorithm in different network
+ * engine, the algorithm calculating shapping parameter is moved to firmware to
+ * execute. Bit HNS3_TM_RATE_VLD_B of flag field in hns3_pri_shapping_cmd,
+ * hns3_pg_shapping_cmd or hns3_port_shapping_cmd is set to 1 to require
+ * firmware to recalculate shapping parameters. However, whether the parameters
+ * are recalculated depends on the firmware version. If firmware doesn't support
+ * the calculation of shapping parameters, such as on network engine with
+ * revision id 0x21, the value driver calculated will be used to configure to
+ * hardware. On the contrary, firmware ignores configuration of driver
+ * and recalculates the parameter.
+ */
+#define HNS3_TM_RATE_VLD_B	0
+
 struct hns3_pri_shapping_cmd {
 	uint8_t pri_id;
 	uint8_t rsvd[3];
 	uint32_t pri_shapping_para;
+	uint8_t flag;
+	uint8_t rsvd1[3];
+	uint32_t pri_rate;  /* Unit Mbps */
+	uint8_t rsvd2[8];
 };
 
 struct hns3_pg_shapping_cmd {
 	uint8_t pg_id;
 	uint8_t rsvd[3];
 	uint32_t pg_shapping_para;
+	uint8_t flag;
+	uint8_t rsvd1[3];
+	uint32_t pg_rate; /* Unit Mbps */
+	uint8_t rsvd2[8];
 };
 
-#define HNS3_BP_GRP_NUM		32
+struct hns3_port_shapping_cmd {
+	uint32_t port_shapping_para;
+	uint8_t flag;
+	uint8_t rsvd[3];
+	uint32_t port_rate;   /* Unit Mbps */
+	uint8_t rsvd1[12];
+};
+
+#define HNS3_BP_GRP_NUM			32
 #define HNS3_BP_SUB_GRP_ID_S		0
 #define HNS3_BP_SUB_GRP_ID_M		GENMASK(4, 0)
 #define HNS3_BP_GRP_ID_S		5
 #define HNS3_BP_GRP_ID_M		GENMASK(9, 5)
+
 struct hns3_bp_to_qs_map_cmd {
 	uint8_t tc_id;
 	uint8_t rsvd[2];
 	uint8_t qs_group_id;
 	uint32_t qs_bit_map;
-	uint32_t rsvd1;
+	uint32_t rsvd1[4];
 };
 
 struct hns3_pfc_en_cmd {
 	uint8_t tx_rx_en_bitmap;
 	uint8_t pri_en_bitmap;
-};
-
-struct hns3_port_shapping_cmd {
-	uint32_t port_shapping_para;
+	uint8_t rsvd[22];
 };
 
 struct hns3_cfg_pause_param_cmd {
@@ -117,6 +162,7 @@ struct hns3_pg_to_pri_link_cmd {
 	uint8_t pg_id;
 	uint8_t rsvd1[3];
 	uint8_t pri_bit_map;
+	uint8_t rsvd2[19];
 };
 
 enum hns3_shaper_level {
@@ -153,14 +199,18 @@ int hns3_dcb_init_hw(struct hns3_hw *hw);
 
 int hns3_dcb_info_init(struct hns3_hw *hw);
 
-int
-hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
+int hns3_fc_enable(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
 
-int
-hns3_dcb_pfc_enable(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf);
+int hns3_dcb_pfc_enable(struct rte_eth_dev *dev,
+			struct rte_eth_pfc_conf *pfc_conf);
 
-void hns3_tc_queue_mapping_cfg(struct hns3_hw *hw);
+int hns3_queue_to_tc_mapping(struct hns3_hw *hw, uint16_t nb_rx_q,
+			     uint16_t nb_tx_q);
 
 int hns3_dcb_cfg_update(struct hns3_adapter *hns);
+int hns3_port_shaper_update(struct hns3_hw *hw, uint32_t speed);
+int hns3_pg_shaper_rate_cfg(struct hns3_hw *hw, uint8_t pg_id, uint32_t rate);
+int hns3_pri_shaper_rate_cfg(struct hns3_hw *hw, uint8_t tc_no, uint32_t rate);
+uint8_t hns3_txq_mapped_tc_get(struct hns3_hw *hw, uint16_t txq_no);
 
 #endif /* _HNS3_DCB_H_ */