X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fi40e%2Fi40e_ethdev.h;h=ce945fef61581c7a461dd255927435068bc9face;hb=5b7bb2bda5519b7800f814df64d4e015282140e5;hp=de3b9d9cb807ec81535ac9c1fb5c86a521455b1d;hpb=647d1eaf758b97311ab3692770acac72144eea87;p=dpdk.git diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index de3b9d9cb8..ce945fef61 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -35,6 +35,7 @@ #define _I40E_ETHDEV_H_ #include +#include #define I40E_VLAN_TAG_SIZE 4 @@ -52,6 +53,9 @@ #define I40E_DEFAULT_QP_NUM_FDIR 1 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t)) #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE) +/* Maximun number of MAC addresses */ +#define I40E_NUM_MACADDR_MAX 64 + /* * vlan_id is a 12 bit number. * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. @@ -107,6 +111,7 @@ enum i40e_flxpld_layer_idx { #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */ #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */ #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */ +#define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */ /* i40e flags */ #define I40E_FLAG_RSS (1ULL << 0) @@ -158,6 +163,14 @@ enum i40e_flxpld_layer_idx { (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \ (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD)) +#define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET +#define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET + +/* Default queue interrupt throttling time in microseconds */ +#define I40E_ITR_INDEX_DEFAULT 0 +#define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */ +#define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */ + struct i40e_adapter; /** @@ -189,6 +202,19 @@ struct i40e_vsi_list { struct i40e_rx_queue; struct i40e_tx_queue; +/* Bandwidth limit information */ +struct i40e_bw_info { + uint16_t bw_limit; /* BW Limit (0 = disabled) */ + uint8_t bw_max; /* Max BW limit if enabled */ + + /* Relative credits within same TC with respect to other VSIs or Comps */ + uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; + /* Bandwidth limit per TC */ + uint8_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS]; + /* Max bandwidth limit per TC */ + uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS]; +}; + /* Structure that defines a VEB */ struct i40e_veb { struct i40e_vsi_list_head head; @@ -197,6 +223,8 @@ struct i40e_veb { uint16_t uplink_seid; /* The uplink seid of this VEB */ uint16_t stats_idx; struct i40e_eth_stats stats; + uint8_t enabled_tc; /* The traffic class enabled */ + struct i40e_bw_info bw_info; /* VEB bandwidth information */ }; /* i40e MACVLAN filter structure */ @@ -206,19 +234,6 @@ struct i40e_macvlan_filter { uint16_t vlan_id; }; -/* Bandwidth limit information */ -struct i40e_bw_info { - uint16_t bw_limit; /* BW Limit (0 = disabled) */ - uint8_t bw_max_quanta; /* Max Quanta when BW limit is enabled */ - - /* Relative TC credits across VSIs */ - uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS]; - /* TC BW limit credits within VSI */ - uint8_t bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS]; - /* TC BW limit max quanta within VSI */ - uint8_t bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS]; -}; - /* * Structure that defines a VSI, associated with a adapter. */ @@ -255,6 +270,7 @@ struct i40e_vsi { uint16_t seid; /* The seid of VSI itself */ uint16_t uplink_seid; /* The uplink seid of this VSI */ uint16_t nb_qps; /* Number of queue pairs VSI can occupy */ + uint16_t nb_used_qps; /* Number of queue pairs VSI uses */ uint16_t max_macaddrs; /* Maximum number of MAC addresses */ uint16_t base_queue; /* The first queue index of this VSI */ /* @@ -263,6 +279,7 @@ struct i40e_vsi { */ uint16_t vsi_id; uint16_t msix_intr; /* The MSIX interrupt binds to VSI */ + uint16_t nb_msix; /* The max number of msix vector */ uint8_t enabled_tc; /* The traffic class enabled */ struct i40e_bw_info bw_info; /* VSI bandwidth information */ }; @@ -300,6 +317,7 @@ struct i40e_pf_vf { uint16_t vf_idx; /* VF index in pf->vfs */ uint16_t lan_nb_qps; /* Actual queues allocated */ uint16_t reset_cnt; /* Total vf reset times */ + struct ether_addr mac_addr; /* Default MAC address */ }; /* @@ -349,6 +367,8 @@ struct i40e_fdir_info { struct i40e_rx_queue *rxq; void *prg_pkt; /* memory for fdir program packet */ uint64_t dma_addr; /* physic address of packet memory*/ + /* input set bits for each pctype */ + uint64_t input_set[I40E_FILTER_PCTYPE_MAX]; /* * the rule how bytes stream is extracted as flexible payload * for each payload layer, the setting can up to three elements @@ -396,17 +416,27 @@ struct i40e_pf { struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ struct ether_addr dev_addr; /* PF device mac address */ - uint64_t flags; /* PF featuer flags */ + uint64_t flags; /* PF feature flags */ /* All kinds of queue pair setting for different VSIs */ struct i40e_pf_vf *vfs; uint16_t vf_num; /* Each of below queue pairs should be power of 2 since it's the precondition after TC configuration applied */ + uint16_t lan_nb_qp_max; uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ + uint16_t lan_qp_offset; + uint16_t vmdq_nb_qp_max; uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */ + uint16_t vmdq_qp_offset; + uint16_t vf_nb_qp_max; uint16_t vf_nb_qps; /* The number of queue pairs of VF */ + uint16_t vf_qp_offset; uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ + uint16_t fdir_qp_offset; + uint16_t hash_lut_size; /* The size of hash lookup table */ + /* input set bits for each pctype */ + uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX]; /* store VXLAN UDP ports */ uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS]; uint16_t vxlan_bitmap; /* Vxlan bit mask */ @@ -474,7 +504,9 @@ struct i40e_vf { bool link_up; bool vf_reset; volatile uint32_t pend_cmd; /* pending command not finished yet */ + uint32_t cmd_retval; /* return value of the cmd response from PF */ u16 pend_msg; /* flags indicates events from pf not handled yet */ + uint8_t *aq_resp; /* buffer to store the adminq response from PF */ /* VSI info */ struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */ @@ -497,11 +529,16 @@ struct i40e_adapter { struct i40e_vf vf; }; - /* for vector PMD */ + /* For vector PMD */ bool rx_bulk_alloc_allowed; bool rx_vec_allowed; bool tx_simple_allowed; bool tx_vec_allowed; + + /* For PTP */ + struct rte_timecounter systime_tc; + struct rte_timecounter rx_tstamp_tc; + struct rte_timecounter tx_tstamp_tc; }; int i40e_dev_switch_queues(struct i40e_pf *pf, bool on); @@ -526,6 +563,7 @@ void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi); int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi, struct i40e_vsi_vlan_pvid_info *info); int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on); +int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on); uint64_t i40e_config_hena(uint64_t flags); uint64_t i40e_parse_hena(uint64_t flags); enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf); @@ -541,6 +579,13 @@ uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype); int i40e_fdir_ctrl_func(struct rte_eth_dev *dev, enum rte_filter_op filter_op, void *arg); +int i40e_select_filter_input_set(struct i40e_hw *hw, + struct rte_eth_input_set_conf *conf, + enum rte_filter_type filter); +int i40e_hash_filter_inset_select(struct i40e_hw *hw, + struct rte_eth_input_set_conf *conf); +int i40e_fdir_filter_inset_select(struct i40e_pf *pf, + struct rte_eth_input_set_conf *conf); void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_rxq_info *qinfo); @@ -568,7 +613,7 @@ i40e_get_vsi_from_adapter(struct i40e_adapter *adapter) return NULL; hw = I40E_DEV_PRIVATE_TO_HW(adapter); - if (hw->mac.type == I40E_MAC_VF) { + if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) { struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter); return &vf->vsi; } else { @@ -618,6 +663,16 @@ i40e_align_floor(int n) return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); } +static inline uint16_t +i40e_calc_itr_interval(int16_t interval) +{ + if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX) + interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT; + + /* Convert to hardware count, as writing each 1 represents 2 us */ + return interval / 2; +} + #define I40E_VALID_FLOW(flow_type) \ ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \ (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \