X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fice%2Fice_ethdev.h;h=f9f4a1c71b1f6499f9675179c0c5e4c24c051f4f;hb=ed665c3e6aafae95361a16653f3d25ec5930bb75;hp=3cefa5b5bf16e6a99f6e7a85f00c42c719e774d5;hpb=ff963bfa7cb1078c53e0e094c8f6ac84a7775198;p=dpdk.git diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 3cefa5b5bf..f9f4a1c71b 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -6,20 +6,25 @@ #define _ICE_ETHDEV_H_ #include +#include + +#include +#include #include "base/ice_common.h" #include "base/ice_adminq_cmd.h" - -#define ICE_VLAN_TAG_SIZE 4 +#include "base/ice_flow.h" +#include "base/ice_sched.h" #define ICE_ADMINQ_LEN 32 #define ICE_SBIOQ_LEN 32 #define ICE_MAILBOXQ_LEN 32 +#define ICE_SBQ_LEN 64 #define ICE_ADMINQ_BUF_SZ 4096 #define ICE_SBIOQ_BUF_SZ 4096 #define ICE_MAILBOXQ_BUF_SZ 4096 -/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */ -#define ICE_MAX_Q_PER_TC 64 +/* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64, 128, 256 */ +#define ICE_MAX_Q_PER_TC 256 #define ICE_NUM_DESC_DEFAULT 512 #define ICE_BUF_SIZE_MIN 1024 #define ICE_FRAME_SIZE_MAX 9728 @@ -40,6 +45,15 @@ #define ICE_MAX_PKT_TYPE 1024 +/* DDP package search path */ +#define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg" +#define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg" +#define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/" +#define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/" +#define ICE_MAX_PKG_FILENAME_SIZE 256 + +#define MAX_ACL_NORMAL_ENTRIES 256 + /** * vlan_id is a 12 bit number. * The VFTA array is actually a 4096 bit array, 128 of 32bit elements. @@ -103,17 +117,77 @@ ICE_FLAG_VF_MAC_BY_PF) #define ICE_RSS_OFFLOAD_ALL ( \ - ETH_RSS_FRAG_IPV4 | \ - ETH_RSS_NONFRAG_IPV4_TCP | \ - ETH_RSS_NONFRAG_IPV4_UDP | \ - ETH_RSS_NONFRAG_IPV4_SCTP | \ - ETH_RSS_NONFRAG_IPV4_OTHER | \ - ETH_RSS_FRAG_IPV6 | \ - ETH_RSS_NONFRAG_IPV6_TCP | \ - ETH_RSS_NONFRAG_IPV6_UDP | \ - ETH_RSS_NONFRAG_IPV6_SCTP | \ - ETH_RSS_NONFRAG_IPV6_OTHER | \ - ETH_RSS_L2_PAYLOAD) + RTE_ETH_RSS_IPV4 | \ + RTE_ETH_RSS_FRAG_IPV4 | \ + RTE_ETH_RSS_NONFRAG_IPV4_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV4_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \ + RTE_ETH_RSS_IPV6 | \ + RTE_ETH_RSS_FRAG_IPV6 | \ + RTE_ETH_RSS_NONFRAG_IPV6_TCP | \ + RTE_ETH_RSS_NONFRAG_IPV6_UDP | \ + RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \ + RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \ + RTE_ETH_RSS_L2_PAYLOAD) + +/** + * The overhead from MTU to max frame size. + * Considering QinQ packet, the VLAN tag needs to be counted twice. + */ +#define ICE_ETH_OVERHEAD \ + (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2) +#define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD) + +#define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) +#define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) + +/* Max number of flexible descriptor rxdid */ +#define ICE_FLEX_DESC_RXDID_MAX_NUM 64 + +#define ICE_I2C_EEPROM_DEV_ADDR 0xA0 +#define ICE_I2C_EEPROM_DEV_ADDR2 0xA2 +#define ICE_MODULE_TYPE_SFP 0x03 +#define ICE_MODULE_TYPE_QSFP_PLUS 0x0D +#define ICE_MODULE_TYPE_QSFP28 0x11 +#define ICE_MODULE_SFF_ADDR_MODE 0x04 +#define ICE_MODULE_SFF_DIAG_CAPAB 0x40 +#define ICE_MODULE_REVISION_ADDR 0x01 +#define ICE_MODULE_SFF_8472_COMP 0x5E +#define ICE_MODULE_SFF_8472_SWAP 0x5C +#define ICE_MODULE_QSFP_MAX_LEN 640 + +/* EEPROM Standards for plug in modules */ +#define ICE_MODULE_SFF_8079 0x1 +#define ICE_MODULE_SFF_8079_LEN 256 +#define ICE_MODULE_SFF_8472 0x2 +#define ICE_MODULE_SFF_8472_LEN 512 +#define ICE_MODULE_SFF_8636 0x3 +#define ICE_MODULE_SFF_8636_LEN 256 +#define ICE_MODULE_SFF_8636_MAX_LEN 640 +#define ICE_MODULE_SFF_8436 0x4 +#define ICE_MODULE_SFF_8436_LEN 256 +#define ICE_MODULE_SFF_8436_MAX_LEN 640 + + +/* Per-channel register definitions */ +#define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) +#define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) +#define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) +#define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) + +/* DDP package type */ +enum ice_pkg_type { + ICE_PKG_TYPE_UNKNOWN, + ICE_PKG_TYPE_OS_DEFAULT, + ICE_PKG_TYPE_COMMS, +}; + +enum pps_type { + PPS_NONE, + PPS_PIN, + PPS_MAX, +}; struct ice_adapter; @@ -121,7 +195,7 @@ struct ice_adapter; * MAC filter structure */ struct ice_mac_filter_info { - struct ether_addr mac_addr; + struct rte_ether_addr mac_addr; }; TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter); @@ -132,11 +206,19 @@ struct ice_mac_filter { struct ice_mac_filter_info mac_info; }; +struct ice_vlan { + uint16_t tpid; + uint16_t vid; +}; + +#define ICE_VLAN(tpid, vid) \ + ((struct ice_vlan){ tpid, vid }) + /** * VLAN filter structure */ struct ice_vlan_filter_info { - uint16_t vlan_id; + struct ice_vlan vlan; }; TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter); @@ -187,7 +269,7 @@ struct ice_vsi { * needs to add, HW needs to know the layout that VSIs are organized. * Besides that, VSI isan element and can't switch packets, which needs * to add new component VEB to perform switching. So, a new VSI needs - * to specify the the uplink VSI (Parent VSI) before created. The + * to specify the uplink VSI (Parent VSI) before created. The * uplink VSI will check whether it had a VEB to switch packets. If no, * it will try to create one. Then, uplink VSI will move the new VSI * into its' sib_vsi_list to manage all the downlink VSI. @@ -223,6 +305,203 @@ struct ice_vsi { struct ice_eth_stats eth_stats_offset; struct ice_eth_stats eth_stats; bool offset_loaded; + uint64_t old_rx_bytes; + uint64_t old_tx_bytes; +}; + +enum proto_xtr_type { + PROTO_XTR_NONE, + PROTO_XTR_VLAN, + PROTO_XTR_IPV4, + PROTO_XTR_IPV6, + PROTO_XTR_IPV6_FLOW, + PROTO_XTR_TCP, + PROTO_XTR_IP_OFFSET, + PROTO_XTR_MAX /* The last one */ +}; + +enum ice_fdir_tunnel_type { + ICE_FDIR_TUNNEL_TYPE_NONE = 0, + ICE_FDIR_TUNNEL_TYPE_VXLAN, + ICE_FDIR_TUNNEL_TYPE_GTPU, + ICE_FDIR_TUNNEL_TYPE_GTPU_EH, +}; + +struct rte_flow; +TAILQ_HEAD(ice_flow_list, rte_flow); + +struct ice_flow_parser_node; +TAILQ_HEAD(ice_parser_list, ice_flow_parser_node); + +struct ice_fdir_filter_conf { + struct ice_fdir_fltr input; + enum ice_fdir_tunnel_type tunnel_type; + + struct ice_fdir_counter *counter; /* flow specific counter context */ + struct rte_flow_action_count act_count; + + uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */ + uint64_t input_set_i; /* only for tunnel inner fields */ + uint32_t mark_flag; + + struct ice_parser_profile *prof; + bool parser_ena; + u8 *pkt_buf; + u8 pkt_len; +}; + +#define ICE_MAX_FDIR_FILTER_NUM (1024 * 16) + +struct ice_fdir_fltr_pattern { + enum ice_fltr_ptype flow_type; + + union { + struct ice_fdir_v4 v4; + struct ice_fdir_v6 v6; + } ip, mask; + + struct ice_fdir_udp_gtp gtpu_data; + struct ice_fdir_udp_gtp gtpu_mask; + + struct ice_fdir_extra ext_data; + struct ice_fdir_extra ext_mask; + + enum ice_fdir_tunnel_type tunnel_type; +}; + +#define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1 +#define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32 +#define ICE_FDIR_COUNTERS_PER_BLOCK 256 +#define ICE_FDIR_COUNTER_INDEX(base_idx) \ + ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK) +struct ice_fdir_counter_pool; + +struct ice_fdir_counter { + TAILQ_ENTRY(ice_fdir_counter) next; + struct ice_fdir_counter_pool *pool; + uint8_t shared; + uint32_t ref_cnt; + uint32_t id; + uint64_t hits; + uint64_t bytes; + uint32_t hw_index; +}; + +TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter); + +struct ice_fdir_counter_pool { + TAILQ_ENTRY(ice_fdir_counter_pool) next; + struct ice_fdir_counter_list counter_list; + struct ice_fdir_counter counters[0]; +}; + +TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool); + +struct ice_fdir_counter_pool_container { + struct ice_fdir_counter_pool_list pool_list; + struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE]; + uint8_t index_free; +}; + +/** + * A structure used to define fields of a FDIR related info. + */ +struct ice_fdir_info { + struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */ + struct ice_tx_queue *txq; + struct ice_rx_queue *rxq; + void *prg_pkt; /* memory for fdir program packet */ + uint64_t dma_addr; /* physic address of packet memory*/ + const struct rte_memzone *mz; + struct ice_fdir_filter_conf conf; + + struct ice_fdir_filter_conf **hash_map; + struct rte_hash *hash_table; + + struct ice_fdir_counter_pool_container counter; +}; + +#define ICE_HASH_GTPU_CTX_EH_IP 0 +#define ICE_HASH_GTPU_CTX_EH_IP_UDP 1 +#define ICE_HASH_GTPU_CTX_EH_IP_TCP 2 +#define ICE_HASH_GTPU_CTX_UP_IP 3 +#define ICE_HASH_GTPU_CTX_UP_IP_UDP 4 +#define ICE_HASH_GTPU_CTX_UP_IP_TCP 5 +#define ICE_HASH_GTPU_CTX_DW_IP 6 +#define ICE_HASH_GTPU_CTX_DW_IP_UDP 7 +#define ICE_HASH_GTPU_CTX_DW_IP_TCP 8 +#define ICE_HASH_GTPU_CTX_MAX 9 + +struct ice_hash_gtpu_ctx { + struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX]; +}; + +struct ice_hash_ctx { + struct ice_hash_gtpu_ctx gtpu4; + struct ice_hash_gtpu_ctx gtpu6; +}; + +struct ice_acl_conf { + struct ice_fdir_fltr input; + uint64_t input_set; +}; + +/** + * A structure used to define fields of ACL related info. + */ +struct ice_acl_info { + struct ice_acl_conf conf; + struct rte_bitmap *slots; + uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES]; +}; + +TAILQ_HEAD(ice_shaper_profile_list, ice_tm_shaper_profile); +TAILQ_HEAD(ice_tm_node_list, ice_tm_node); + +struct ice_tm_shaper_profile { + TAILQ_ENTRY(ice_tm_shaper_profile) node; + uint32_t shaper_profile_id; + uint32_t reference_count; + struct rte_tm_shaper_params profile; +}; + +/* Struct to store Traffic Manager node configuration. */ +struct ice_tm_node { + TAILQ_ENTRY(ice_tm_node) node; + uint32_t id; + uint32_t tc; + uint32_t priority; + uint32_t weight; + uint32_t reference_count; + struct ice_tm_node *parent; + struct ice_tm_node **children; + struct ice_tm_shaper_profile *shaper_profile; + struct rte_tm_node_params params; +}; + +/* node type of Traffic Manager */ +enum ice_tm_node_type { + ICE_TM_NODE_TYPE_PORT, + ICE_TM_NODE_TYPE_TC, + ICE_TM_NODE_TYPE_VSI, + ICE_TM_NODE_TYPE_QGROUP, + ICE_TM_NODE_TYPE_QUEUE, + ICE_TM_NODE_TYPE_MAX, +}; + +/* Struct to store all the Traffic Manager configuration. */ +struct ice_tm_conf { + struct ice_shaper_profile_list shaper_profile_list; + struct ice_tm_node *root; /* root node - port */ + struct ice_tm_node_list tc_list; /* node list for all the TCs */ + struct ice_tm_node_list vsi_list; /* node list for all the VSIs */ + struct ice_tm_node_list qgroup_list; /* node list for all the queue groups */ + struct ice_tm_node_list queue_list; /* node list for all the queues */ + uint32_t nb_tc_node; + uint32_t nb_vsi_node; + uint32_t nb_qgroup_node; + uint32_t nb_queue_node; + bool committed; }; struct ice_pf { @@ -238,11 +517,20 @@ struct ice_pf { struct ice_res_pool_info qp_pool; /*Queue pair pool */ struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */ struct rte_eth_dev_data *dev_data; /* Pointer to the device data */ - struct ether_addr dev_addr; /* PF device mac address */ + struct rte_ether_addr dev_addr; /* PF device mac address */ uint64_t flags; /* PF feature flags */ uint16_t hash_lut_size; /* The size of hash lookup table */ uint16_t lan_nb_qp_max; uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ + uint16_t base_queue; /* The base queue pairs index in the device */ + uint8_t *proto_xtr; /* Protocol extraction type for all queues */ + uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */ + uint16_t fdir_qp_offset; + struct ice_fdir_info fdir; /* flow director info */ + struct ice_acl_info acl; /* ACL info */ + struct ice_hash_ctx hash_ctx; + uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; + uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX]; struct ice_hw_port_stats stats_offset; struct ice_hw_port_stats stats; /* internal packet statistics, it should be excluded from the total */ @@ -250,6 +538,49 @@ struct ice_pf { struct ice_eth_stats internal_stats; bool offset_loaded; bool adapter_stopped; + struct ice_flow_list flow_list; + rte_spinlock_t flow_ops_lock; + struct ice_parser_list rss_parser_list; + struct ice_parser_list perm_parser_list; + struct ice_parser_list dist_parser_list; + bool init_link_up; + uint64_t old_rx_bytes; + uint64_t old_tx_bytes; + uint64_t supported_rxdid; /* bitmap for supported RXDID */ + uint64_t rss_hf; + struct ice_tm_conf tm_conf; +}; + +#define ICE_MAX_QUEUE_NUM 2048 +#define ICE_MAX_PIN_NUM 4 + +/** + * Cache devargs parse result. + */ +struct ice_devargs { + int rx_low_latency; + int safe_mode_support; + uint8_t proto_xtr_dflt; + int pipe_mode_support; + uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; + uint8_t pin_idx; + uint8_t pps_out_ena; +}; + +/** + * Structure to store fdir fv entry. + */ +struct ice_fdir_prof_info { + struct ice_parser_profile prof; + u64 fdir_actived_cnt; +}; + +/** + * Structure to store rss fv entry. + */ +struct ice_rss_prof_info { + struct ice_parser_profile prof; + bool symm; }; /** @@ -258,12 +589,38 @@ struct ice_pf { struct ice_adapter { /* Common for both PF and VF */ struct ice_hw hw; - struct rte_eth_dev *eth_dev; struct ice_pf pf; bool rx_bulk_alloc_allowed; + bool rx_vec_allowed; + bool tx_vec_allowed; bool tx_simple_allowed; /* ptype mapping table */ uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned; + bool is_safe_mode; + struct ice_devargs devargs; + enum ice_pkg_type active_pkg_type; /* loaded ddp package type */ + uint16_t fdir_ref_cnt; + /* For PTP */ + struct rte_timecounter systime_tc; + struct rte_timecounter rx_tstamp_tc; + struct rte_timecounter tx_tstamp_tc; + bool ptp_ena; + uint64_t time_hw; + uint32_t hw_time_high; /* high 32 bits of timestamp */ + uint32_t hw_time_low; /* low 32 bits of timestamp */ + uint64_t hw_time_update; /* SW time of HW record updating */ + struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS]; + struct ice_rss_prof_info rss_prof_info[ICE_MAX_PTGS]; + /* True if DCF state of the associated PF is on */ + bool dcf_state_on; + struct ice_parser *psr; +#ifdef RTE_ARCH_X86 + bool rx_use_avx2; + bool rx_use_avx512; + bool tx_use_avx2; + bool tx_use_avx512; + bool rx_vec_offload_support; +#endif }; struct ice_vsi_vlan_pvid_info { @@ -297,8 +654,6 @@ struct ice_vsi_vlan_pvid_info { (&(((struct ice_vsi *)vsi)->adapter->hw)) #define ICE_VSI_TO_PF(vsi) \ (&(((struct ice_vsi *)vsi)->adapter->pf)) -#define ICE_VSI_TO_ETH_DEV(vsi) \ - (((struct ice_vsi *)vsi)->adapter->eth_dev) /* ICE_PF_TO */ #define ICE_PF_TO_HW(pf) \ @@ -308,6 +663,23 @@ struct ice_vsi_vlan_pvid_info { #define ICE_PF_TO_ETH_DEV(pf) \ (((struct ice_pf *)pf)->adapter->eth_dev) +int +ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn); +struct ice_vsi * +ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type); +int +ice_release_vsi(struct ice_vsi *vsi); +void ice_vsi_enable_queues_intr(struct ice_vsi *vsi); +void ice_vsi_disable_queues_intr(struct ice_vsi *vsi); +void ice_vsi_queues_bind_intr(struct ice_vsi *vsi); +int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, + struct ice_rss_hash_cfg *cfg); +int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id, + struct ice_rss_hash_cfg *cfg); +void ice_tm_conf_init(struct rte_eth_dev *dev); +void ice_tm_conf_uninit(struct rte_eth_dev *dev); +extern const struct rte_tm_ops ice_tm_ops; + static inline int ice_align_floor(int n) { @@ -315,4 +687,44 @@ ice_align_floor(int n) return 0; return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n)); } + +#define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \ + (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1)) + +#define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \ + (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \ + ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR)) + +#define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \ + (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \ + ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \ + ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \ + ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2)) + #endif /* _ICE_ETHDEV_H_ */