X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fixgbe%2Fbase%2Fixgbe_x550.c;h=e4e8cff84a228e9d79dc022a8a6ac9a17f3c61e9;hb=55c64cee04d36b65493601cb66b8a583c9d61c22;hp=bc0ca53e0c0bc7fb9f463d18fdb85fa7e7e6a228;hpb=54128402f47eff4b74162c252992651699302c8a;p=dpdk.git diff --git a/drivers/net/ixgbe/base/ixgbe_x550.c b/drivers/net/ixgbe/base/ixgbe_x550.c index bc0ca53e0c..e4e8cff84a 100644 --- a/drivers/net/ixgbe/base/ixgbe_x550.c +++ b/drivers/net/ixgbe/base/ixgbe_x550.c @@ -118,6 +118,7 @@ STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) { s32 status; u16 value = 0; + u16 reg_slice, reg_val; u8 retry; for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) { @@ -132,6 +133,77 @@ STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) if (value != IXGBE_CS4227_GLOBAL_ID_VALUE) return IXGBE_ERR_PHY; + status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); + if (status != IXGBE_SUCCESS) + return status; + + /* If this is the first time after power-on, check the ucode. + * Otherwise, this will disrupt link on all ports. Because we + * can only do this the first time, we must check all ports, + * not just our own. + */ + if (value != IXGBE_CS4227_SCRATCH_VALUE) { + reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; + reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; + status = ixgbe_write_cs4227(hw, reg_slice, reg_val); + if (status != IXGBE_SUCCESS) + return status; + + reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; + reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; + status = ixgbe_write_cs4227(hw, reg_slice, reg_val); + if (status != IXGBE_SUCCESS) + return status; + + reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); + reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; + status = ixgbe_write_cs4227(hw, reg_slice, reg_val); + if (status != IXGBE_SUCCESS) + return status; + + reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); + reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; + status = ixgbe_write_cs4227(hw, reg_slice, reg_val); + if (status != IXGBE_SUCCESS) + return status; + + msec_delay(10); + } + + /* Verify that the ucode is operational on all ports. */ + reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; + reg_val = 0xFFFF; + status = ixgbe_read_cs4227(hw, reg_slice, ®_val); + if (status != IXGBE_SUCCESS) + return status; + if (reg_val != 0) + return IXGBE_ERR_PHY; + + reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; + reg_val = 0xFFFF; + status = ixgbe_read_cs4227(hw, reg_slice, ®_val); + if (status != IXGBE_SUCCESS) + return status; + if (reg_val != 0) + return IXGBE_ERR_PHY; + + reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); + reg_val = 0xFFFF; + status = ixgbe_read_cs4227(hw, reg_slice, ®_val); + if (status != IXGBE_SUCCESS) + return status; + if (reg_val != 0) + return IXGBE_ERR_PHY; + + reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); + reg_val = 0xFFFF; + status = ixgbe_read_cs4227(hw, reg_slice, ®_val); + if (status != IXGBE_SUCCESS) + return status; + if (reg_val != 0) + return IXGBE_ERR_PHY; + + /* Set scratch indicating that the diagnostic was successful. */ status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, IXGBE_CS4227_SCRATCH_VALUE); if (status != IXGBE_SUCCESS) @@ -141,6 +213,7 @@ STATIC s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) return status; if (value != IXGBE_CS4227_SCRATCH_VALUE) return IXGBE_ERR_PHY; + return IXGBE_SUCCESS; } @@ -382,10 +455,17 @@ s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) mac->ops.get_supported_physical_layer = ixgbe_get_supported_physical_layer_X550em; + if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) + mac->ops.setup_fc = ixgbe_setup_fc_generic; + else mac->ops.setup_fc = ixgbe_setup_fc_X550em; + mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; + if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR) + mac->ops.setup_eee = NULL; + /* PHY */ phy->ops.init = ixgbe_init_phy_ops_X550em; phy->ops.identify = ixgbe_identify_phy_x550em; @@ -613,6 +693,10 @@ s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX; + /* Must disable FEC when EEE is enabled. */ + link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | + IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); + status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); @@ -643,6 +727,10 @@ s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX); + /* Enable FEC when EEE is disabled. */ + link_reg |= (IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | + IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); + status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); @@ -707,6 +795,39 @@ void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); } +/** + * ixgbe_iosf_wait - Wait for IOSF command completion + * @hw: pointer to hardware structure + * @ctrl: pointer to location to receive final IOSF control value + * + * Returns failing status on timeout + * + * Note: ctrl can be NULL if the IOSF control register value is not needed + **/ +STATIC s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) +{ + u32 i, command = 0; + + /* Check every 10 usec to see if the address cycle completed. + * The SB IOSF BUSY bit will clear when the operation is + * complete + */ + for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { + command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); + if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) + break; + usec_delay(10); + } + if (ctrl) + *ctrl = command; + if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { + ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); + return IXGBE_ERR_PHY; + } + + return IXGBE_SUCCESS; +} + /** * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF * device @@ -718,7 +839,17 @@ void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 data) { - u32 i, command, error; + u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; + u32 command, error; + s32 ret; + + ret = ixgbe_acquire_swfw_semaphore(hw, gssr); + if (ret != IXGBE_SUCCESS) + return ret; + + ret = ixgbe_iosf_wait(hw, NULL); + if (ret != IXGBE_SUCCESS) + goto out; command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); @@ -728,33 +859,20 @@ s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, /* Write IOSF data register */ IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); - /* - * Check every 10 usec to see if the address cycle completed. - * The SB IOSF BUSY bit will clear when the operation is - * complete - */ - for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { - usec_delay(10); - command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); - if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) - break; - } + ret = ixgbe_iosf_wait(hw, &command); if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; ERROR_REPORT2(IXGBE_ERROR_POLLING, "Failed to write, error %x\n", error); - return IXGBE_ERR_PHY; - } - - if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { - ERROR_REPORT1(IXGBE_ERROR_POLLING, "Write timed out\n"); - return IXGBE_ERR_PHY; + ret = IXGBE_ERR_PHY; } - return IXGBE_SUCCESS; +out: + ixgbe_release_swfw_semaphore(hw, gssr); + return ret; } /** @@ -768,7 +886,17 @@ s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, u32 *data) { - u32 i, command, error; + u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; + u32 command, error; + s32 ret; + + ret = ixgbe_acquire_swfw_semaphore(hw, gssr); + if (ret != IXGBE_SUCCESS) + return ret; + + ret = ixgbe_iosf_wait(hw, NULL); + if (ret != IXGBE_SUCCESS) + goto out; command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); @@ -776,35 +904,22 @@ s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, /* Write IOSF control register */ IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); - /* - * Check every 10 usec to see if the address cycle completed. - * The SB IOSF BUSY bit will clear when the operation is - * complete - */ - for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { - usec_delay(10); - - command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); - if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) - break; - } + ret = ixgbe_iosf_wait(hw, &command); if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; ERROR_REPORT2(IXGBE_ERROR_POLLING, "Failed to read, error %x\n", error); - return IXGBE_ERR_PHY; - } - - if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { - ERROR_REPORT1(IXGBE_ERROR_POLLING, "Read timed out\n"); - return IXGBE_ERR_PHY; + ret = IXGBE_ERR_PHY; } - *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); + if (ret == IXGBE_SUCCESS) + *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); - return IXGBE_SUCCESS; +out: + ixgbe_release_swfw_semaphore(hw, gssr); + return ret; } /** @@ -983,25 +1098,20 @@ enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) } /** - * ixgbe_setup_sfp_modules_X550em - Setup SFP module + * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported * @hw: pointer to hardware structure + * @linear: true if SFP module is linear */ -s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) +STATIC s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) { - bool setup_linear; - u16 reg_slice, edc_mode; - s32 ret_val; - - DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); + DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); switch (hw->phy.sfp_type) { - case ixgbe_sfp_type_unknown: - return IXGBE_SUCCESS; case ixgbe_sfp_type_not_present: return IXGBE_ERR_SFP_NOT_PRESENT; case ixgbe_sfp_type_da_cu_core0: case ixgbe_sfp_type_da_cu_core1: - setup_linear = true; + *linear = true; break; case ixgbe_sfp_type_srlr_core0: case ixgbe_sfp_type_srlr_core1: @@ -1011,34 +1121,63 @@ s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) case ixgbe_sfp_type_1g_sx_core1: case ixgbe_sfp_type_1g_lx_core0: case ixgbe_sfp_type_1g_lx_core1: - setup_linear = false; + *linear = false; break; + case ixgbe_sfp_type_unknown: + case ixgbe_sfp_type_1g_cu_core0: + case ixgbe_sfp_type_1g_cu_core1: default: return IXGBE_ERR_SFP_NOT_SUPPORTED; } - ixgbe_init_mac_link_ops_X550em(hw); - hw->phy.ops.reset = NULL; + return IXGBE_SUCCESS; +} - /* The CS4227 slice address is the base address + the port-pair reg - * offset. I.e. Slice 0 = 0x12B0 and slice 1 = 0x22B0. - */ - reg_slice = IXGBE_CS4227_SPARE24_LSB + (hw->bus.lan_id << 12); +/** + * ixgbe_identify_sfp_module_X550em - Identifies SFP modules + * @hw: pointer to hardware structure + * + * Searches for and identifies the SFP module and assigns appropriate PHY type. + **/ +s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) +{ + s32 status; + bool linear; - if (setup_linear) - edc_mode = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; - else - edc_mode = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; + DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); - /* Configure CS4227 for connection type. */ - ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, - edc_mode); + status = ixgbe_identify_module_generic(hw); - if (ret_val != IXGBE_SUCCESS) - ret_val = ixgbe_write_i2c_combined(hw, 0x80, reg_slice, - edc_mode); + if (status != IXGBE_SUCCESS) + return status; - return ret_val; + /* Check if SFP module is supported */ + status = ixgbe_supported_sfp_modules_X550em(hw, &linear); + + return status; +} + +/** + * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops + * @hw: pointer to hardware structure + */ +s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) +{ + s32 status; + bool linear; + + DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); + + /* Check if SFP module is supported */ + status = ixgbe_supported_sfp_modules_X550em(hw, &linear); + + if (status != IXGBE_SUCCESS) + return status; + + ixgbe_init_mac_link_ops_X550em(hw); + hw->phy.ops.reset = NULL; + + return IXGBE_SUCCESS; } /** @@ -1051,10 +1190,11 @@ void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); - /* CS4227 does not support autoneg, so disable the laser control - * functions for SFP+ fiber - */ - if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { + switch (hw->mac.ops.get_media_type(hw)) { + case ixgbe_media_type_fiber: + /* CS4227 does not support autoneg, so disable the laser control + * functions for SFP+ fiber + */ mac->ops.disable_tx_laser = NULL; mac->ops.enable_tx_laser = NULL; mac->ops.flap_tx_laser = NULL; @@ -1062,6 +1202,13 @@ void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; mac->ops.set_rate_select_speed = ixgbe_set_soft_rate_select_speed; + break; + case ixgbe_media_type_copper: + mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; + mac->ops.check_link = ixgbe_check_link_t_X550em; + break; + default: + break; } } @@ -1107,6 +1254,166 @@ s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, return IXGBE_SUCCESS; } +/** + * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause + * @hw: pointer to hardware structure + * @lsc: pointer to boolean flag which indicates whether external Base T + * PHY interrupt is lsc + * + * Determime if external Base T PHY interrupt cause is high temperature + * failure alarm or link status change. + * + * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature + * failure alarm, else return PHY access status. + */ +STATIC s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) +{ + u32 status; + u16 reg; + + *lsc = false; + + /* Vendor alarm triggered */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); + + if (status != IXGBE_SUCCESS || + !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) + return status; + + /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); + + if (status != IXGBE_SUCCESS || + !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | + IXGBE_MDIO_GLOBAL_ALARM_1_INT))) + return status; + + /* High temperature failure alarm triggered */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); + + if (status != IXGBE_SUCCESS) + return status; + + /* If high temperature failure, then return over temp error and exit */ + if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { + /* power down the PHY in case the PHY FW didn't already */ + ixgbe_set_copper_phy_power(hw, false); + return IXGBE_ERR_OVERTEMP; + } + + /* Vendor alarm 2 triggered */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); + + if (status != IXGBE_SUCCESS || + !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) + return status; + + /* link connect/disconnect event occurred */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); + + if (status != IXGBE_SUCCESS) + return status; + + /* Indicate LSC */ + if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) + *lsc = true; + + return IXGBE_SUCCESS; +} + +/** + * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts + * @hw: pointer to hardware structure + * + * Enable link status change and temperature failure alarm for the external + * Base T PHY + * + * Returns PHY access status + */ +STATIC s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) +{ + u32 status; + u16 reg; + bool lsc; + + /* Clear interrupt flags */ + status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); + + /* Enable link status change alarm */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); + + if (status != IXGBE_SUCCESS) + return status; + + reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; + + status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); + + if (status != IXGBE_SUCCESS) + return status; + + /* Enables high temperature failure alarm */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); + + if (status != IXGBE_SUCCESS) + return status; + + reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; + + status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + reg); + + if (status != IXGBE_SUCCESS) + return status; + + /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); + + if (status != IXGBE_SUCCESS) + return status; + + reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | + IXGBE_MDIO_GLOBAL_ALARM_1_INT); + + status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + reg); + + if (status != IXGBE_SUCCESS) + return status; + + /* Enable chip-wide vendor alarm */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + ®); + + if (status != IXGBE_SUCCESS) + return status; + + reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; + + status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, + IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, + reg); + + return status; +} + /** * ixgbe_init_phy_ops_X550em - PHY/SFP specific init * @hw: pointer to hardware structure @@ -1122,9 +1429,13 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) DEBUGFUNC("ixgbe_init_phy_ops_X550em"); + hw->mac.ops.set_lan_id(hw); + if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; ixgbe_setup_mux_ctl(hw); + + phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; } /* Identify the PHY or SFP module */ @@ -1132,7 +1443,7 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) return ret_val; - /* Setup function pointers based on detected SFP module and speeds */ + /* Setup function pointers based on detected hardware */ ixgbe_init_mac_link_ops_X550em(hw); if (phy->sfp_type != ixgbe_sfp_type_unknown) phy->ops.reset = NULL; @@ -1153,6 +1464,8 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) phy->ops.setup_internal_link = ixgbe_setup_internal_phy_t_x550em; phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; + phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; + phy->ops.reset = ixgbe_reset_phy_t_X550em; break; default: break; @@ -1170,7 +1483,6 @@ s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) */ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) { - struct ixgbe_hic_hdr fw_cmd; ixgbe_link_speed link_speed; s32 status; u32 ctrl = 0; @@ -1179,22 +1491,6 @@ s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) DEBUGFUNC("ixgbe_reset_hw_X550em"); - fw_cmd.cmd = FW_PHY_MGMT_REQ_CMD; - fw_cmd.buf_len = 0; - fw_cmd.cmd_or_resp.cmd_resv = 0; - fw_cmd.checksum = FW_DEFAULT_CHECKSUM; - status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, - sizeof(fw_cmd), - IXGBE_HI_PHY_MGMT_REQ_TIMEOUT, - true); - if (status) - ERROR_REPORT2(IXGBE_ERROR_CAUTION, - "PHY mgmt command failed with %d\n", status); - else if (fw_cmd.cmd_or_resp.ret_status != FW_CEM_RESP_STATUS_SUCCESS) - ERROR_REPORT2(IXGBE_ERROR_CAUTION, - "PHY mgmt command returned %d\n", - fw_cmd.cmd_or_resp.ret_status); - /* Call adapter stop to disable Tx/Rx and clear interrupts */ status = hw->mac.ops.stop_adapter(hw); if (status != IXGBE_SUCCESS) @@ -1350,8 +1646,6 @@ s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) return status; reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; - reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | - IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); @@ -1384,7 +1678,7 @@ s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) u32 reg_val; status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, - IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, ®_val); + IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val); if (status) return status; @@ -1404,7 +1698,7 @@ s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) /* Restart auto-negotiation. */ reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, - IXGBE_SB_IOSF_TARGET_KX4_PCS0 + hw->bus.lan_id, reg_val); + IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val); return status; } @@ -1523,18 +1817,65 @@ STATIC s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) } /** - * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP. + * ixgbe_setup_mac_link_sfp_x550em - Configure the CS4227 & KR PHY for SFP * @hw: pointer to hardware structure * - * Configures the integrated KR PHY for SFP support. + * Configure the external CS4227 PHY and the integrated KR PHY for SFP support. **/ s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, ixgbe_link_speed speed, bool autoneg_wait_to_complete) { + s32 ret_val; + u16 reg_slice, reg_val; + bool setup_linear = false; UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); - return ixgbe_setup_ixfi_x550em(hw, &speed); + /* Check if SFP module is supported and linear */ + ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); + + /* If no SFP module present, then return success. Return success since + * there is no reason to configure CS4227 and SFP not present error is + * not excepted in the setup MAC link flow. + */ + if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) + return IXGBE_SUCCESS; + + if (ret_val != IXGBE_SUCCESS) + return ret_val; + + /* Configure CS4227 for LINE connection rate then type. */ + reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12); + reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; + ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, + reg_val); + + reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); + if (setup_linear) + reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; + else + reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; + ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, + reg_val); + + /* Configure CS4227 for HOST connection rate then type. */ + reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12); + reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; + ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, + reg_val); + + reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12); + if (setup_linear) + reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; + else + reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; + ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, + reg_val); + + /* Configure the internal PHY. */ + ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); + + return ret_val; } /** @@ -2243,6 +2584,8 @@ s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) hw->bus.width = ixgbe_bus_width_unknown; hw->bus.speed = ixgbe_bus_speed_unknown; + hw->mac.ops.set_lan_id(hw); + return IXGBE_SUCCESS; } @@ -2303,6 +2646,7 @@ s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) u16 autoneg_status, an_10g_cntl_reg, autoneg_reg, speed; s32 status; ixgbe_link_speed lcd_speed; + u32 save_autoneg; /* If blocked by MNG FW, then don't restart AN */ if (ixgbe_check_reset_blocked(hw)) @@ -2378,48 +2722,13 @@ s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) if (status != IXGBE_SUCCESS) return status; - /* Set AN advertizement to only include LCD */ - if (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL) { - an_10g_cntl_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; - autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; - } - - if (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL) { - an_10g_cntl_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; - autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; - } - - status = hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - an_10g_cntl_reg); - - if (status != IXGBE_SUCCESS) - return status; - - status = hw->phy.ops.write_reg(hw, - IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, - autoneg_reg); - - if (status != IXGBE_SUCCESS) - return status; - - /* Restart PHY auto-negotiation. */ - status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); - - if (status != IXGBE_SUCCESS) - return status; - - autoneg_reg |= IXGBE_MII_RESTART; - - status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, - IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); + save_autoneg = hw->phy.autoneg_advertised; - if (status != IXGBE_SUCCESS) - return status; + /* Setup link at least common link speed */ + status = hw->mac.ops.setup_link(hw, lcd_speed, false); - status = ixgbe_setup_ixfi_x550em(hw, &lcd_speed); + /* restore autoneg from before setting lplu speed */ + hw->phy.autoneg_advertised = save_autoneg; return status; } @@ -2603,3 +2912,132 @@ void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) ixgbe_release_swfw_sync_X540(hw, mask); } + +/** + * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt + * @hw: pointer to hardware structure + * + * Handle external Base T PHY interrupt. If high temperature + * failure alarm then return error, else if link status change + * then setup internal/external PHY link + * + * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature + * failure alarm, else return PHY access status. + */ +s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) +{ + bool lsc; + u32 status; + + status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); + + if (status != IXGBE_SUCCESS) + return status; + + if (lsc) + return ixgbe_setup_internal_phy_t_x550em(hw); + + return IXGBE_SUCCESS; +} + +/** + * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed + * @hw: pointer to hardware structure + * @speed: new link speed + * @autoneg_wait_to_complete: true when waiting for completion is needed + * + * Setup internal/external PHY link speed based on link speed, then set + * external PHY auto advertised link speed. + * + * Returns error status for any failure + **/ +s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, + ixgbe_link_speed speed, + bool autoneg_wait_to_complete) +{ + s32 status; + ixgbe_link_speed force_speed; + + DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); + + /* Setup internal/external PHY link speed to iXFI (10G), unless + * only 1G is auto advertised then setup KX link. + */ + if (speed & IXGBE_LINK_SPEED_10GB_FULL) + force_speed = IXGBE_LINK_SPEED_10GB_FULL; + else + force_speed = IXGBE_LINK_SPEED_1GB_FULL; + + status = ixgbe_setup_ixfi_x550em(hw, &force_speed); + + if (status != IXGBE_SUCCESS) + return status; + + return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); +} + +/** + * ixgbe_check_link_t_X550em - Determine link and speed status + * @hw: pointer to hardware structure + * @speed: pointer to link speed + * @link_up: true when link is up + * @link_up_wait_to_complete: bool used to wait for link up or not + * + * Check that both the MAC and X557 external PHY have link. + **/ +s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, + bool *link_up, bool link_up_wait_to_complete) +{ + u32 status; + u16 autoneg_status; + + if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) + return IXGBE_ERR_CONFIG; + + status = ixgbe_check_mac_link_generic(hw, speed, link_up, + link_up_wait_to_complete); + + /* If check link fails or MAC link is not up, then return */ + if (status != IXGBE_SUCCESS || !(*link_up)) + return status; + + /* MAC link is up, so check external PHY link. + * Read this twice back to back to indicate current status. + */ + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_status); + + if (status != IXGBE_SUCCESS) + return status; + + status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, + IXGBE_MDIO_AUTO_NEG_DEV_TYPE, + &autoneg_status); + + if (status != IXGBE_SUCCESS) + return status; + + /* If external PHY link is not up, then indicate link not up */ + if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) + *link_up = false; + + return IXGBE_SUCCESS; +} + +/** + * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI + * @hw: pointer to hardware structure + **/ +s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) +{ + s32 status; + + status = ixgbe_reset_phy_generic(hw); + + if (status != IXGBE_SUCCESS) + return status; + + /* Configure Link Status Alarm and Temperature Threshold interrupts */ + return ixgbe_enable_lasi_ext_t_x550em(hw); +}