X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fmrvl%2Fmrvl_ethdev.c;h=705c4bd8b32f9c76ab66982cc227f63638ee8864;hb=e940646b20fa;hp=7bd0dadae659631f98e927727a6c4fc67921f5e9;hpb=d9e7317e1bdd10581ff29732fb32df9fe18d5591;p=dpdk.git diff --git a/drivers/net/mrvl/mrvl_ethdev.c b/drivers/net/mrvl/mrvl_ethdev.c index 7bd0dadae6..705c4bd8b3 100644 --- a/drivers/net/mrvl/mrvl_ethdev.c +++ b/drivers/net/mrvl/mrvl_ethdev.c @@ -1,7 +1,9 @@ /*- * BSD LICENSE * - * Copyright(c) 2017 Semihalf. All rights reserved. + * Copyright(c) 2017 Marvell International Ltd. + * Copyright(c) 2017 Semihalf. + * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -30,11 +32,11 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include +#include #include #include #include -#include +#include /* Unluckily, container_of is defined by both DPDK and MUSDK, * we'll declare only one version. @@ -45,10 +47,6 @@ #undef container_of #endif -#include -#include -#include - #include #include #include @@ -66,13 +64,16 @@ #define MRVL_MUSDK_HIFS_RESERVED 0x0F /* bitmask with reserved bpools */ #define MRVL_MUSDK_BPOOLS_RESERVED 0x07 +/* bitmask with reserved kernel RSS tables */ +#define MRVL_MUSDK_RSS_RESERVED 0x01 /* maximum number of available hifs */ #define MRVL_MUSDK_HIFS_MAX 9 -#define MRVL_MAC_ADDRS_MAX 1 /* prefetch shift */ #define MRVL_MUSDK_PREFETCH_SHIFT 2 +/* TCAM has 25 entries reserved for uc/mc filter entries */ +#define MRVL_MAC_ADDRS_MAX 25 #define MRVL_MATCH_LEN 16 #define MRVL_PKT_EFFEC_OFFS (MRVL_PKT_OFFS + MV_MH_SIZE) /* Maximum allowable packet size */ @@ -90,6 +91,20 @@ #define MRVL_COOKIE_HIGH_ADDR_SHIFT (sizeof(pp2_cookie_t) * 8) #define MRVL_COOKIE_HIGH_ADDR_MASK (~0ULL << MRVL_COOKIE_HIGH_ADDR_SHIFT) +/* Memory size (in bytes) for MUSDK dma buffers */ +#define MRVL_MUSDK_DMA_MEMSIZE 41943040 + +/** Port Rx offload capabilities */ +#define MRVL_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_FILTER | \ + DEV_RX_OFFLOAD_JUMBO_FRAME | \ + DEV_RX_OFFLOAD_CRC_STRIP | \ + DEV_RX_OFFLOAD_CHECKSUM) + +/** Port Tx offloads capabilities */ +#define MRVL_TX_OFFLOADS (DEV_TX_OFFLOAD_IPV4_CKSUM | \ + DEV_TX_OFFLOAD_UDP_CKSUM | \ + DEV_TX_OFFLOAD_TCP_CKSUM) + static const char * const valid_args[] = { MRVL_IFACE_NAME_ARG, MRVL_CFG_ARG, @@ -107,6 +122,11 @@ struct pp2_bpool *mrvl_port_to_bpool_lookup[RTE_MAX_ETHPORTS]; int mrvl_port_bpool_size[PP2_NUM_PKT_PROC][PP2_BPOOL_NUM_POOLS][RTE_MAX_LCORE]; uint64_t cookie_addr_high = MRVL_COOKIE_ADDR_INVALID; +struct mrvl_ifnames { + const char *names[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; + int idx; +}; + /* * To use buffer harvesting based on loopback port shadow queue structure * was introduced for buffers information bookkeeping. @@ -131,27 +151,27 @@ struct mrvl_rxq { struct rte_mempool *mp; int queue_id; int port_id; + int cksum_enabled; + uint64_t bytes_recv; + uint64_t drop_mac; }; struct mrvl_txq { struct mrvl_priv *priv; int queue_id; int port_id; + uint64_t bytes_sent; + struct mrvl_shadow_txq shadow_txqs[RTE_MAX_LCORE]; }; -/* - * Every tx queue should have dedicated shadow tx queue. - * - * Ports assigned by DPDK might not start at zero or be continuous so - * as a workaround define shadow queues for each possible port so that - * we eventually fit somewhere. - */ -struct mrvl_shadow_txq shadow_txqs[RTE_MAX_ETHPORTS][RTE_MAX_LCORE]; - -/** Number of ports configured. */ -int mrvl_ports_nb; static int mrvl_lcore_first; static int mrvl_lcore_last; +static int mrvl_dev_num; + +static int mrvl_fill_bpool(struct mrvl_rxq *rxq, int num); +static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, + struct pp2_hif *hif, unsigned int core_id, + struct mrvl_shadow_txq *sq, int qid, int force); static inline int mrvl_get_bpool_size(int pp2_id, int pool_id) @@ -178,10 +198,101 @@ mrvl_reserve_bit(int *bitmap, int max) return n; } +static int +mrvl_init_hif(int core_id) +{ + struct pp2_hif_params params; + char match[MRVL_MATCH_LEN]; + int ret; + + ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); + if (ret < 0) { + RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id); + return ret; + } + + snprintf(match, sizeof(match), "hif-%d", ret); + memset(¶ms, 0, sizeof(params)); + params.match = match; + params.out_size = MRVL_PP2_AGGR_TXQD_MAX; + ret = pp2_hif_init(¶ms, &hifs[core_id]); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", core_id); + return ret; + } + + return 0; +} + +static inline struct pp2_hif* +mrvl_get_hif(struct mrvl_priv *priv, int core_id) +{ + int ret; + + if (likely(hifs[core_id] != NULL)) + return hifs[core_id]; + + rte_spinlock_lock(&priv->lock); + + ret = mrvl_init_hif(core_id); + if (ret < 0) { + RTE_LOG(ERR, PMD, "Failed to allocate hif %d\n", core_id); + goto out; + } + + if (core_id < mrvl_lcore_first) + mrvl_lcore_first = core_id; + + if (core_id > mrvl_lcore_last) + mrvl_lcore_last = core_id; +out: + rte_spinlock_unlock(&priv->lock); + + return hifs[core_id]; +} + +/** + * Configure rss based on dpdk rss configuration. + * + * @param priv + * Pointer to private structure. + * @param rss_conf + * Pointer to RSS configuration. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_configure_rss(struct mrvl_priv *priv, struct rte_eth_rss_conf *rss_conf) +{ + if (rss_conf->rss_key) + RTE_LOG(WARNING, PMD, "Changing hash key is not supported\n"); + + if (rss_conf->rss_hf == 0) { + priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; + } else if (rss_conf->rss_hf & ETH_RSS_IPV4) { + priv->ppio_params.inqs_params.hash_type = + PP2_PPIO_HASH_T_2_TUPLE; + } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) { + priv->ppio_params.inqs_params.hash_type = + PP2_PPIO_HASH_T_5_TUPLE; + priv->rss_hf_tcp = 1; + } else if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) { + priv->ppio_params.inqs_params.hash_type = + PP2_PPIO_HASH_T_5_TUPLE; + priv->rss_hf_tcp = 0; + } else { + return -EINVAL; + } + + return 0; +} + /** * Ethernet device configuration. * - * Prepare the driver for a given number of TX and RX queues. + * Prepare the driver for a given number of TX and RX queues and + * configure RSS. * * @param dev * Pointer to Ethernet device structure. @@ -195,19 +306,20 @@ mrvl_dev_configure(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; - if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE) { + if (dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_NONE && + dev->data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) { RTE_LOG(INFO, PMD, "Unsupported rx multi queue mode %d\n", dev->data->dev_conf.rxmode.mq_mode); return -EINVAL; } - if (!dev->data->dev_conf.rxmode.hw_strip_crc) { + if (!(dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { RTE_LOG(INFO, PMD, "L2 CRC stripping is always enabled in hw\n"); - dev->data->dev_conf.rxmode.hw_strip_crc = 1; + dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP; } - if (dev->data->dev_conf.rxmode.hw_vlan_strip) { + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { RTE_LOG(INFO, PMD, "VLAN stripping not supported\n"); return -EINVAL; } @@ -217,25 +329,74 @@ mrvl_dev_configure(struct rte_eth_dev *dev) return -EINVAL; } - if (dev->data->dev_conf.rxmode.enable_scatter) { + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) { RTE_LOG(INFO, PMD, "RX Scatter/Gather not supported\n"); return -EINVAL; } - if (dev->data->dev_conf.rxmode.enable_lro) { + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) { RTE_LOG(INFO, PMD, "LRO not supported\n"); return -EINVAL; } + if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) + dev->data->mtu = dev->data->dev_conf.rxmode.max_rx_pkt_len - + ETHER_HDR_LEN - ETHER_CRC_LEN; + ret = mrvl_configure_rxqs(priv, dev->data->port_id, dev->data->nb_rx_queues); if (ret < 0) return ret; priv->ppio_params.outqs_params.num_outqs = dev->data->nb_tx_queues; + priv->ppio_params.maintain_stats = 1; priv->nb_rx_queues = dev->data->nb_rx_queues; - return 0; + if (dev->data->nb_rx_queues == 1 && + dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) { + RTE_LOG(WARNING, PMD, "Disabling hash for 1 rx queue\n"); + priv->ppio_params.inqs_params.hash_type = PP2_PPIO_HASH_T_NONE; + + return 0; + } + + return mrvl_configure_rss(priv, + &dev->data->dev_conf.rx_adv_conf.rss_conf); +} + +/** + * DPDK callback to change the MTU. + * + * Setting the MTU affects hardware MRU (packets larger than the MRU + * will be dropped). + * + * @param dev + * Pointer to Ethernet device structure. + * @param mtu + * New MTU. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) +{ + struct mrvl_priv *priv = dev->data->dev_private; + /* extra MV_MH_SIZE bytes are required for Marvell tag */ + uint16_t mru = mtu + MV_MH_SIZE + ETHER_HDR_LEN + ETHER_CRC_LEN; + int ret; + + if (mtu < ETHER_MIN_MTU || mru > MRVL_PKT_SIZE_MAX) + return -EINVAL; + + if (!priv->ppio) + return 0; + + ret = pp2_ppio_set_mru(priv->ppio, mru); + if (ret) + return ret; + + return pp2_ppio_set_mtu(priv->ppio, mtu); } /** @@ -253,11 +414,23 @@ mrvl_dev_set_link_up(struct rte_eth_dev *dev) struct mrvl_priv *priv = dev->data->dev_private; int ret; + if (!priv->ppio) + return -EPERM; + ret = pp2_ppio_enable(priv->ppio); if (ret) return ret; - dev->data->dev_link.link_status = ETH_LINK_UP; + /* + * mtu/mru can be updated if pp2_ppio_enable() was called at least once + * as pp2_ppio_enable() changes port->t_mode from default 0 to + * PP2_TRAFFIC_INGRESS_EGRESS. + * + * Set mtu to default DPDK value here. + */ + ret = mrvl_mtu_set(dev, dev->data->mtu); + if (ret) + pp2_ppio_disable(priv->ppio); return ret; } @@ -275,15 +448,11 @@ static int mrvl_dev_set_link_down(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; - int ret; - ret = pp2_ppio_disable(priv->ppio); - if (ret) - return ret; + if (!priv->ppio) + return -EPERM; - dev->data->dev_link.link_status = ETH_LINK_DOWN; - - return ret; + return pp2_ppio_disable(priv->ppio); } /** @@ -300,19 +469,12 @@ mrvl_dev_start(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; char match[MRVL_MATCH_LEN]; - int ret; + int ret = 0, def_init_size; snprintf(match, sizeof(match), "ppio-%d:%d", priv->pp_id, priv->ppio_id); priv->ppio_params.match = match; - /* - * Calculate the maximum bpool size for refill feature to 1.5 of the - * configured size. In case the bpool size will exceed this value, - * superfluous buffers will be removed - */ - priv->bpool_max_size = priv->bpool_init_size + - (priv->bpool_init_size >> 1); /* * Calculate the minimum bpool size for refill feature as follows: * 2 default burst sizes multiply by number of rx queues. @@ -321,25 +483,82 @@ mrvl_dev_start(struct rte_eth_dev *dev) */ priv->bpool_min_size = priv->nb_rx_queues * MRVL_BURST_SIZE * 2; + /* In case initial bpool size configured in queues setup is + * smaller than minimum size add more buffers + */ + def_init_size = priv->bpool_min_size + MRVL_BURST_SIZE * 2; + if (priv->bpool_init_size < def_init_size) { + int buffs_to_add = def_init_size - priv->bpool_init_size; + + priv->bpool_init_size += buffs_to_add; + ret = mrvl_fill_bpool(dev->data->rx_queues[0], buffs_to_add); + if (ret) + RTE_LOG(ERR, PMD, "Failed to add buffers to bpool\n"); + } + + /* + * Calculate the maximum bpool size for refill feature as follows: + * maximum number of descriptors in rx queue multiply by number + * of rx queues plus minimum bpool size. + * In case the bpool size will exceed this value, superfluous buffers + * will be removed + */ + priv->bpool_max_size = (priv->nb_rx_queues * MRVL_PP2_RXD_MAX) + + priv->bpool_min_size; + ret = pp2_ppio_init(&priv->ppio_params, &priv->ppio); - if (ret) + if (ret) { + RTE_LOG(ERR, PMD, "Failed to init ppio\n"); return ret; + } + + /* + * In case there are some some stale uc/mc mac addresses flush them + * here. It cannot be done during mrvl_dev_close() as port information + * is already gone at that point (due to pp2_ppio_deinit() in + * mrvl_dev_stop()). + */ + if (!priv->uc_mc_flushed) { + ret = pp2_ppio_flush_mac_addrs(priv->ppio, 1, 1); + if (ret) { + RTE_LOG(ERR, PMD, + "Failed to flush uc/mc filter list\n"); + goto out; + } + priv->uc_mc_flushed = 1; + } + + if (!priv->vlan_flushed) { + ret = pp2_ppio_flush_vlan(priv->ppio); + if (ret) { + RTE_LOG(ERR, PMD, "Failed to flush vlan list\n"); + /* + * TODO + * once pp2_ppio_flush_vlan() is supported jump to out + * goto out; + */ + } + priv->vlan_flushed = 1; + } /* For default QoS config, don't start classifier. */ if (mrvl_qos_cfg) { ret = mrvl_start_qos_mapping(priv); if (ret) { - pp2_ppio_deinit(priv->ppio); - return ret; + RTE_LOG(ERR, PMD, "Failed to setup QoS mapping\n"); + goto out; } } ret = mrvl_dev_set_link_up(dev); - if (ret) + if (ret) { + RTE_LOG(ERR, PMD, "Failed to set link up\n"); goto out; + } return 0; out: + RTE_LOG(ERR, PMD, "Failed to start device\n"); pp2_ppio_deinit(priv->ppio); return ret; } @@ -381,21 +600,32 @@ mrvl_flush_rx_queues(struct rte_eth_dev *dev) static void mrvl_flush_tx_shadow_queues(struct rte_eth_dev *dev) { - int i; + int i, j; + struct mrvl_txq *txq; RTE_LOG(INFO, PMD, "Flushing tx shadow queues\n"); - for (i = 0; i < RTE_MAX_LCORE; i++) { - struct mrvl_shadow_txq *sq = - &shadow_txqs[dev->data->port_id][i]; + for (i = 0; i < dev->data->nb_tx_queues; i++) { + txq = (struct mrvl_txq *)dev->data->tx_queues[i]; + + for (j = 0; j < RTE_MAX_LCORE; j++) { + struct mrvl_shadow_txq *sq; - while (sq->tail != sq->head) { - uint64_t addr = cookie_addr_high | + if (!hifs[j]) + continue; + + sq = &txq->shadow_txqs[j]; + mrvl_free_sent_buffers(txq->priv->ppio, + hifs[j], j, sq, txq->queue_id, 1); + while (sq->tail != sq->head) { + uint64_t addr = cookie_addr_high | sq->ent[sq->tail].buff.cookie; - rte_pktmbuf_free((struct rte_mbuf *)addr); - sq->tail = (sq->tail + 1) & MRVL_PP2_TX_SHADOWQ_MASK; + rte_pktmbuf_free( + (struct rte_mbuf *)addr); + sq->tail = (sq->tail + 1) & + MRVL_PP2_TX_SHADOWQ_MASK; + } + memset(sq, 0, sizeof(*sq)); } - - memset(sq, 0, sizeof(*sq)); } } @@ -409,8 +639,15 @@ static void mrvl_flush_bpool(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; + struct pp2_hif *hif; uint32_t num; int ret; + unsigned int core_id = rte_lcore_id(); + + if (core_id == LCORE_ID_ANY) + core_id = 0; + + hif = mrvl_get_hif(priv, core_id); ret = pp2_bpool_get_num_buffs(priv->bpool, &num); if (ret) { @@ -422,8 +659,7 @@ mrvl_flush_bpool(struct rte_eth_dev *dev) struct pp2_buff_inf inf; uint64_t addr; - ret = pp2_bpool_get_buff(hifs[rte_lcore_id()], priv->bpool, - &inf); + ret = pp2_bpool_get_buff(hif, priv->bpool, &inf); if (ret) break; @@ -446,8 +682,10 @@ mrvl_dev_stop(struct rte_eth_dev *dev) mrvl_dev_set_link_down(dev); mrvl_flush_rx_queues(dev); mrvl_flush_tx_shadow_queues(dev); - if (priv->qos_tbl) + if (priv->qos_tbl) { pp2_cls_qos_tbl_deinit(priv->qos_tbl); + priv->qos_tbl = NULL; + } pp2_ppio_deinit(priv->ppio); priv->ppio = NULL; } @@ -495,9 +733,13 @@ mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) * TODO * once MUSDK provides necessary API use it here */ + struct mrvl_priv *priv = dev->data->dev_private; struct ethtool_cmd edata; struct ifreq req; - int ret, fd; + int ret, fd, link_up; + + if (!priv->ppio) + return -EPERM; edata.cmd = ETHTOOL_GSET; @@ -533,35 +775,335 @@ mrvl_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) dev->data->dev_link.link_speed = ETH_SPEED_NUM_NONE; } - dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : - ETH_LINK_HALF_DUPLEX; - dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : - ETH_LINK_FIXED; + dev->data->dev_link.link_duplex = edata.duplex ? ETH_LINK_FULL_DUPLEX : + ETH_LINK_HALF_DUPLEX; + dev->data->dev_link.link_autoneg = edata.autoneg ? ETH_LINK_AUTONEG : + ETH_LINK_FIXED; + pp2_ppio_get_link_state(priv->ppio, &link_up); + dev->data->dev_link.link_status = link_up ? ETH_LINK_UP : ETH_LINK_DOWN; + + return 0; +} + +/** + * DPDK callback to enable promiscuous mode. + * + * @param dev + * Pointer to Ethernet device structure. + */ +static void +mrvl_promiscuous_enable(struct rte_eth_dev *dev) +{ + struct mrvl_priv *priv = dev->data->dev_private; + int ret; + + if (!priv->ppio) + return; + + ret = pp2_ppio_set_promisc(priv->ppio, 1); + if (ret) + RTE_LOG(ERR, PMD, "Failed to enable promiscuous mode\n"); +} + +/** + * DPDK callback to enable allmulti mode. + * + * @param dev + * Pointer to Ethernet device structure. + */ +static void +mrvl_allmulticast_enable(struct rte_eth_dev *dev) +{ + struct mrvl_priv *priv = dev->data->dev_private; + int ret; + + if (!priv->ppio) + return; + + ret = pp2_ppio_set_mc_promisc(priv->ppio, 1); + if (ret) + RTE_LOG(ERR, PMD, "Failed enable all-multicast mode\n"); +} + +/** + * DPDK callback to disable promiscuous mode. + * + * @param dev + * Pointer to Ethernet device structure. + */ +static void +mrvl_promiscuous_disable(struct rte_eth_dev *dev) +{ + struct mrvl_priv *priv = dev->data->dev_private; + int ret; + + if (!priv->ppio) + return; + + ret = pp2_ppio_set_promisc(priv->ppio, 0); + if (ret) + RTE_LOG(ERR, PMD, "Failed to disable promiscuous mode\n"); +} + +/** + * DPDK callback to disable allmulticast mode. + * + * @param dev + * Pointer to Ethernet device structure. + */ +static void +mrvl_allmulticast_disable(struct rte_eth_dev *dev) +{ + struct mrvl_priv *priv = dev->data->dev_private; + int ret; + + if (!priv->ppio) + return; + + ret = pp2_ppio_set_mc_promisc(priv->ppio, 0); + if (ret) + RTE_LOG(ERR, PMD, "Failed to disable all-multicast mode\n"); +} + +/** + * DPDK callback to remove a MAC address. + * + * @param dev + * Pointer to Ethernet device structure. + * @param index + * MAC address index. + */ +static void +mrvl_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index) +{ + struct mrvl_priv *priv = dev->data->dev_private; + char buf[ETHER_ADDR_FMT_SIZE]; + int ret; + + if (!priv->ppio) + return; + + ret = pp2_ppio_remove_mac_addr(priv->ppio, + dev->data->mac_addrs[index].addr_bytes); + if (ret) { + ether_format_addr(buf, sizeof(buf), + &dev->data->mac_addrs[index]); + RTE_LOG(ERR, PMD, "Failed to remove mac %s\n", buf); + } +} + +/** + * DPDK callback to add a MAC address. + * + * @param dev + * Pointer to Ethernet device structure. + * @param mac_addr + * MAC address to register. + * @param index + * MAC address index. + * @param vmdq + * VMDq pool index to associate address with (unused). + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac_addr, + uint32_t index, uint32_t vmdq __rte_unused) +{ + struct mrvl_priv *priv = dev->data->dev_private; + char buf[ETHER_ADDR_FMT_SIZE]; + int ret; + + if (index == 0) + /* For setting index 0, mrvl_mac_addr_set() should be used.*/ + return -1; + + if (!priv->ppio) + return 0; + + /* + * Maximum number of uc addresses can be tuned via kernel module mvpp2x + * parameter uc_filter_max. Maximum number of mc addresses is then + * MRVL_MAC_ADDRS_MAX - uc_filter_max. Currently it defaults to 4 and + * 21 respectively. + * + * If more than uc_filter_max uc addresses were added to filter list + * then NIC will switch to promiscuous mode automatically. + * + * If more than MRVL_MAC_ADDRS_MAX - uc_filter_max number mc addresses + * were added to filter list then NIC will switch to all-multicast mode + * automatically. + */ + ret = pp2_ppio_add_mac_addr(priv->ppio, mac_addr->addr_bytes); + if (ret) { + ether_format_addr(buf, sizeof(buf), mac_addr); + RTE_LOG(ERR, PMD, "Failed to add mac %s\n", buf); + return -1; + } + + return 0; +} + +/** + * DPDK callback to set the primary MAC address. + * + * @param dev + * Pointer to Ethernet device structure. + * @param mac_addr + * MAC address to register. + */ +static void +mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) +{ + struct mrvl_priv *priv = dev->data->dev_private; + int ret; + + if (!priv->ppio) + return; + + ret = pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); + if (ret) { + char buf[ETHER_ADDR_FMT_SIZE]; + ether_format_addr(buf, sizeof(buf), mac_addr); + RTE_LOG(ERR, PMD, "Failed to set mac to %s\n", buf); + } +} + +/** + * DPDK callback to get device statistics. + * + * @param dev + * Pointer to Ethernet device structure. + * @param stats + * Stats structure output buffer. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats) +{ + struct mrvl_priv *priv = dev->data->dev_private; + struct pp2_ppio_statistics ppio_stats; + uint64_t drop_mac = 0; + unsigned int i, idx, ret; + + if (!priv->ppio) + return -EPERM; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + struct mrvl_rxq *rxq = dev->data->rx_queues[i]; + struct pp2_ppio_inq_statistics rx_stats; + + if (!rxq) + continue; + + idx = rxq->queue_id; + if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { + RTE_LOG(ERR, PMD, + "rx queue %d stats out of range (0 - %d)\n", + idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); + continue; + } + + ret = pp2_ppio_inq_get_statistics(priv->ppio, + priv->rxq_map[idx].tc, + priv->rxq_map[idx].inq, + &rx_stats, 0); + if (unlikely(ret)) { + RTE_LOG(ERR, PMD, + "Failed to update rx queue %d stats\n", idx); + break; + } + + stats->q_ibytes[idx] = rxq->bytes_recv; + stats->q_ipackets[idx] = rx_stats.enq_desc - rxq->drop_mac; + stats->q_errors[idx] = rx_stats.drop_early + + rx_stats.drop_fullq + + rx_stats.drop_bm + + rxq->drop_mac; + stats->ibytes += rxq->bytes_recv; + drop_mac += rxq->drop_mac; + } + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + struct mrvl_txq *txq = dev->data->tx_queues[i]; + struct pp2_ppio_outq_statistics tx_stats; + + if (!txq) + continue; + + idx = txq->queue_id; + if (unlikely(idx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)) { + RTE_LOG(ERR, PMD, + "tx queue %d stats out of range (0 - %d)\n", + idx, RTE_ETHDEV_QUEUE_STAT_CNTRS - 1); + } + + ret = pp2_ppio_outq_get_statistics(priv->ppio, idx, + &tx_stats, 0); + if (unlikely(ret)) { + RTE_LOG(ERR, PMD, + "Failed to update tx queue %d stats\n", idx); + break; + } + + stats->q_opackets[idx] = tx_stats.deq_desc; + stats->q_obytes[idx] = txq->bytes_sent; + stats->obytes += txq->bytes_sent; + } + + ret = pp2_ppio_get_statistics(priv->ppio, &ppio_stats, 0); + if (unlikely(ret)) { + RTE_LOG(ERR, PMD, "Failed to update port statistics\n"); + return ret; + } + + stats->ipackets += ppio_stats.rx_packets - drop_mac; + stats->opackets += ppio_stats.tx_packets; + stats->imissed += ppio_stats.rx_fullq_dropped + + ppio_stats.rx_bm_dropped + + ppio_stats.rx_early_dropped + + ppio_stats.rx_fifo_dropped + + ppio_stats.rx_cls_dropped; + stats->ierrors = drop_mac; return 0; } /** - * DPDK callback to set the primary MAC address. + * DPDK callback to clear device statistics. * * @param dev * Pointer to Ethernet device structure. - * @param mac_addr - * MAC address to register. */ static void -mrvl_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr) +mrvl_stats_reset(struct rte_eth_dev *dev) { struct mrvl_priv *priv = dev->data->dev_private; + int i; - pp2_ppio_set_mac_addr(priv->ppio, mac_addr->addr_bytes); - /* - * TODO - * Port stops sending packets if pp2_ppio_set_mac_addr() - * was called after pp2_ppio_enable(). As a quick fix issue - * enable port once again. - */ - pp2_ppio_enable(priv->ppio); + if (!priv->ppio) + return; + + for (i = 0; i < dev->data->nb_rx_queues; i++) { + struct mrvl_rxq *rxq = dev->data->rx_queues[i]; + + pp2_ppio_inq_get_statistics(priv->ppio, priv->rxq_map[i].tc, + priv->rxq_map[i].inq, NULL, 1); + rxq->bytes_recv = 0; + rxq->drop_mac = 0; + } + + for (i = 0; i < dev->data->nb_tx_queues; i++) { + struct mrvl_txq *txq = dev->data->tx_queues[i]; + + pp2_ppio_outq_get_statistics(priv->ppio, i, NULL, 1); + txq->bytes_sent = 0; + } + + pp2_ppio_get_statistics(priv->ppio, NULL, 1); } /** @@ -593,12 +1135,50 @@ mrvl_dev_infos_get(struct rte_eth_dev *dev __rte_unused, info->tx_desc_lim.nb_min = MRVL_PP2_TXD_MIN; info->tx_desc_lim.nb_align = MRVL_PP2_TXD_ALIGN; + info->rx_offload_capa = MRVL_RX_OFFLOADS; + info->rx_queue_offload_capa = MRVL_RX_OFFLOADS; + + info->tx_offload_capa = MRVL_TX_OFFLOADS; + info->tx_queue_offload_capa = MRVL_TX_OFFLOADS; + + info->flow_type_rss_offloads = ETH_RSS_IPV4 | + ETH_RSS_NONFRAG_IPV4_TCP | + ETH_RSS_NONFRAG_IPV4_UDP; + /* By default packets are dropped if no descriptors are available */ info->default_rxconf.rx_drop_en = 1; + info->default_rxconf.offloads = DEV_RX_OFFLOAD_CRC_STRIP; info->max_rx_pktlen = MRVL_PKT_SIZE_MAX; } +/** + * Return supported packet types. + * + * @param dev + * Pointer to Ethernet device structure (unused). + * + * @return + * Const pointer to the table with supported packet types. + */ +static const uint32_t * +mrvl_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) +{ + static const uint32_t ptypes[] = { + RTE_PTYPE_L2_ETHER, + RTE_PTYPE_L3_IPV4, + RTE_PTYPE_L3_IPV4_EXT, + RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, + RTE_PTYPE_L3_IPV6, + RTE_PTYPE_L3_IPV6_EXT, + RTE_PTYPE_L2_ETHER_ARP, + RTE_PTYPE_L4_TCP, + RTE_PTYPE_L4_UDP + }; + + return ptypes; +} + /** * DPDK callback to get information about specific receive queue. * @@ -642,6 +1222,31 @@ static void mrvl_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id, priv->ppio_params.outqs_params.outqs_params[tx_queue_id].size; } +/** + * DPDK callback to Configure a VLAN filter. + * + * @param dev + * Pointer to Ethernet device structure. + * @param vlan_id + * VLAN ID to filter. + * @param on + * Toggle filter. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) +{ + struct mrvl_priv *priv = dev->data->dev_private; + + if (!priv->ppio) + return -EPERM; + + return on ? pp2_ppio_add_vlan(priv->ppio, vlan_id) : + pp2_ppio_remove_vlan(priv->ppio, vlan_id); +} + /** * Release buffers to hardware bpool (buffer-pool) * @@ -659,9 +1264,19 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) struct buff_release_entry entries[MRVL_PP2_TXD_MAX]; struct rte_mbuf *mbufs[MRVL_PP2_TXD_MAX]; int i, ret; - unsigned int core_id = rte_lcore_id(); - struct pp2_hif *hif = hifs[core_id]; - struct pp2_bpool *bpool = rxq->priv->bpool; + unsigned int core_id; + struct pp2_hif *hif; + struct pp2_bpool *bpool; + + core_id = rte_lcore_id(); + if (core_id == LCORE_ID_ANY) + core_id = 0; + + hif = mrvl_get_hif(rxq->priv, core_id); + if (!hif) + return -1; + + bpool = rxq->priv->bpool; ret = rte_pktmbuf_alloc_bulk(rxq->mp, mbufs, num); if (ret) @@ -681,7 +1296,7 @@ mrvl_fill_bpool(struct mrvl_rxq *rxq, int num) } entries[i].buff.addr = - rte_mbuf_data_dma_addr_default(mbufs[i]); + rte_mbuf_data_iova_default(mbufs[i]); entries[i].buff.cookie = (pp2_cookie_t)(uint64_t)mbufs[i]; entries[i].bpool = bpool; } @@ -700,6 +1315,42 @@ out: return -1; } +/** + * Check whether requested rx queue offloads match port offloads. + * + * @param + * dev Pointer to the device. + * @param + * requested Bitmap of the requested offloads. + * + * @return + * 1 if requested offloads are okay, 0 otherwise. + */ +static int +mrvl_rx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested) +{ + uint64_t mandatory = dev->data->dev_conf.rxmode.offloads; + uint64_t supported = MRVL_RX_OFFLOADS; + uint64_t unsupported = requested & ~supported; + uint64_t missing = mandatory & ~requested; + + if (unsupported) { + RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. " + "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n", + requested, supported); + return 0; + } + + if (missing) { + RTE_LOG(ERR, PMD, "Some Rx offloads are missing. " + "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n", + requested, missing); + return 0; + } + + return 1; +} + /** * DPDK callback to configure the receive queue. * @@ -712,7 +1363,7 @@ out: * @param socket * NUMA socket on which memory must be allocated. * @param conf - * Thresholds parameters (unused_). + * Thresholds parameters. * @param mp * Memory pool for buffer allocations. * @@ -722,7 +1373,7 @@ out: static int mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, - const struct rte_eth_rxconf *conf __rte_unused, + const struct rte_eth_rxconf *conf, struct rte_mempool *mp) { struct mrvl_priv *priv = dev->data->dev_private; @@ -731,6 +1382,9 @@ mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, max_rx_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; int ret, tc, inq; + if (!mrvl_rx_queue_offloads_okay(dev, conf->offloads)) + return -ENOTSUP; + if (priv->rxq_map[idx].tc == MRVL_UNKNOWN_TC) { /* * Unknown TC mapping, mapping will not have a correct queue. @@ -762,6 +1416,8 @@ mrvl_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, rxq->priv = priv; rxq->mp = mp; + rxq->cksum_enabled = + dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_IPV4_CKSUM; rxq->queue_id = idx; rxq->port_id = dev->data->port_id; mrvl_port_to_bpool_lookup[rxq->port_id] = priv->bpool; @@ -796,8 +1452,15 @@ mrvl_rx_queue_release(void *rxq) struct mrvl_rxq *q = rxq; struct pp2_ppio_tc_params *tc_params; int i, num, tc, inq; + struct pp2_hif *hif; + unsigned int core_id = rte_lcore_id(); - if (!q) + if (core_id == LCORE_ID_ANY) + core_id = 0; + + hif = mrvl_get_hif(q->priv, core_id); + + if (!q || !hif) return; tc = q->priv->rxq_map[q->queue_id].tc; @@ -808,7 +1471,7 @@ mrvl_rx_queue_release(void *rxq) struct pp2_buff_inf inf; uint64_t addr; - pp2_bpool_get_buff(hifs[rte_lcore_id()], q->priv->bpool, &inf); + pp2_bpool_get_buff(hif, q->priv->bpool, &inf); addr = cookie_addr_high | inf.cookie; rte_pktmbuf_free((struct rte_mbuf *)addr); } @@ -816,6 +1479,42 @@ mrvl_rx_queue_release(void *rxq) rte_free(q); } +/** + * Check whether requested tx queue offloads match port offloads. + * + * @param + * dev Pointer to the device. + * @param + * requested Bitmap of the requested offloads. + * + * @return + * 1 if requested offloads are okay, 0 otherwise. + */ +static int +mrvl_tx_queue_offloads_okay(struct rte_eth_dev *dev, uint64_t requested) +{ + uint64_t mandatory = dev->data->dev_conf.txmode.offloads; + uint64_t supported = MRVL_TX_OFFLOADS; + uint64_t unsupported = requested & ~supported; + uint64_t missing = mandatory & ~requested; + + if (unsupported) { + RTE_LOG(ERR, PMD, "Some Rx offloads are not supported. " + "Requested 0x%" PRIx64 " supported 0x%" PRIx64 ".\n", + requested, supported); + return 0; + } + + if (missing) { + RTE_LOG(ERR, PMD, "Some Rx offloads are missing. " + "Requested 0x%" PRIx64 " missing 0x%" PRIx64 ".\n", + requested, missing); + return 0; + } + + return 1; +} + /** * DPDK callback to configure the transmit queue. * @@ -828,7 +1527,7 @@ mrvl_rx_queue_release(void *rxq) * @param socket * NUMA socket on which memory must be allocated. * @param conf - * Thresholds parameters (unused). + * Thresholds parameters. * * @return * 0 on success, negative error value otherwise. @@ -836,11 +1535,14 @@ mrvl_rx_queue_release(void *rxq) static int mrvl_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, unsigned int socket, - const struct rte_eth_txconf *conf __rte_unused) + const struct rte_eth_txconf *conf) { struct mrvl_priv *priv = dev->data->dev_private; struct mrvl_txq *txq; + if (!mrvl_tx_queue_offloads_okay(dev, conf->offloads)) + return -ENOTSUP; + if (dev->data->tx_queues[idx]) { rte_free(dev->data->tx_queues[idx]); dev->data->tx_queues[idx] = NULL; @@ -878,6 +1580,59 @@ mrvl_tx_queue_release(void *txq) rte_free(q); } +/** + * Update RSS hash configuration + * + * @param dev + * Pointer to Ethernet device structure. + * @param rss_conf + * Pointer to RSS configuration. + * + * @return + * 0 on success, negative error value otherwise. + */ +static int +mrvl_rss_hash_update(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct mrvl_priv *priv = dev->data->dev_private; + + return mrvl_configure_rss(priv, rss_conf); +} + +/** + * DPDK callback to get RSS hash configuration. + * + * @param dev + * Pointer to Ethernet device structure. + * @rss_conf + * Pointer to RSS configuration. + * + * @return + * Always 0. + */ +static int +mrvl_rss_hash_conf_get(struct rte_eth_dev *dev, + struct rte_eth_rss_conf *rss_conf) +{ + struct mrvl_priv *priv = dev->data->dev_private; + enum pp2_ppio_hash_type hash_type = + priv->ppio_params.inqs_params.hash_type; + + rss_conf->rss_key = NULL; + + if (hash_type == PP2_PPIO_HASH_T_NONE) + rss_conf->rss_hf = 0; + else if (hash_type == PP2_PPIO_HASH_T_2_TUPLE) + rss_conf->rss_hf = ETH_RSS_IPV4; + else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && priv->rss_hf_tcp) + rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_TCP; + else if (hash_type == PP2_PPIO_HASH_T_5_TUPLE && !priv->rss_hf_tcp) + rss_conf->rss_hf = ETH_RSS_NONFRAG_IPV4_UDP; + + return 0; +} + static const struct eth_dev_ops mrvl_ops = { .dev_configure = mrvl_dev_configure, .dev_start = mrvl_dev_start, @@ -886,16 +1641,130 @@ static const struct eth_dev_ops mrvl_ops = { .dev_set_link_down = mrvl_dev_set_link_down, .dev_close = mrvl_dev_close, .link_update = mrvl_link_update, + .promiscuous_enable = mrvl_promiscuous_enable, + .allmulticast_enable = mrvl_allmulticast_enable, + .promiscuous_disable = mrvl_promiscuous_disable, + .allmulticast_disable = mrvl_allmulticast_disable, + .mac_addr_remove = mrvl_mac_addr_remove, + .mac_addr_add = mrvl_mac_addr_add, .mac_addr_set = mrvl_mac_addr_set, + .mtu_set = mrvl_mtu_set, + .stats_get = mrvl_stats_get, + .stats_reset = mrvl_stats_reset, .dev_infos_get = mrvl_dev_infos_get, + .dev_supported_ptypes_get = mrvl_dev_supported_ptypes_get, .rxq_info_get = mrvl_rxq_info_get, .txq_info_get = mrvl_txq_info_get, + .vlan_filter_set = mrvl_vlan_filter_set, .rx_queue_setup = mrvl_rx_queue_setup, .rx_queue_release = mrvl_rx_queue_release, .tx_queue_setup = mrvl_tx_queue_setup, .tx_queue_release = mrvl_tx_queue_release, + .rss_hash_update = mrvl_rss_hash_update, + .rss_hash_conf_get = mrvl_rss_hash_conf_get, }; +/** + * Return packet type information and l3/l4 offsets. + * + * @param desc + * Pointer to the received packet descriptor. + * @param l3_offset + * l3 packet offset. + * @param l4_offset + * l4 packet offset. + * + * @return + * Packet type information. + */ +static inline uint64_t +mrvl_desc_to_packet_type_and_offset(struct pp2_ppio_desc *desc, + uint8_t *l3_offset, uint8_t *l4_offset) +{ + enum pp2_inq_l3_type l3_type; + enum pp2_inq_l4_type l4_type; + uint64_t packet_type; + + pp2_ppio_inq_desc_get_l3_info(desc, &l3_type, l3_offset); + pp2_ppio_inq_desc_get_l4_info(desc, &l4_type, l4_offset); + + packet_type = RTE_PTYPE_L2_ETHER; + + switch (l3_type) { + case PP2_INQ_L3_TYPE_IPV4_NO_OPTS: + packet_type |= RTE_PTYPE_L3_IPV4; + break; + case PP2_INQ_L3_TYPE_IPV4_OK: + packet_type |= RTE_PTYPE_L3_IPV4_EXT; + break; + case PP2_INQ_L3_TYPE_IPV4_TTL_ZERO: + packet_type |= RTE_PTYPE_L3_IPV4_EXT_UNKNOWN; + break; + case PP2_INQ_L3_TYPE_IPV6_NO_EXT: + packet_type |= RTE_PTYPE_L3_IPV6; + break; + case PP2_INQ_L3_TYPE_IPV6_EXT: + packet_type |= RTE_PTYPE_L3_IPV6_EXT; + break; + case PP2_INQ_L3_TYPE_ARP: + packet_type |= RTE_PTYPE_L2_ETHER_ARP; + /* + * In case of ARP l4_offset is set to wrong value. + * Set it to proper one so that later on mbuf->l3_len can be + * calculated subtracting l4_offset and l3_offset. + */ + *l4_offset = *l3_offset + MRVL_ARP_LENGTH; + break; + default: + RTE_LOG(DEBUG, PMD, "Failed to recognise l3 packet type\n"); + break; + } + + switch (l4_type) { + case PP2_INQ_L4_TYPE_TCP: + packet_type |= RTE_PTYPE_L4_TCP; + break; + case PP2_INQ_L4_TYPE_UDP: + packet_type |= RTE_PTYPE_L4_UDP; + break; + default: + RTE_LOG(DEBUG, PMD, "Failed to recognise l4 packet type\n"); + break; + } + + return packet_type; +} + +/** + * Get offload information from the received packet descriptor. + * + * @param desc + * Pointer to the received packet descriptor. + * + * @return + * Mbuf offload flags. + */ +static inline uint64_t +mrvl_desc_to_ol_flags(struct pp2_ppio_desc *desc) +{ + uint64_t flags; + enum pp2_inq_desc_status status; + + status = pp2_ppio_inq_desc_get_l3_pkt_error(desc); + if (unlikely(status != PP2_DESC_ERR_OK)) + flags = PKT_RX_IP_CKSUM_BAD; + else + flags = PKT_RX_IP_CKSUM_GOOD; + + status = pp2_ppio_inq_desc_get_l4_pkt_error(desc); + if (unlikely(status != PP2_DESC_ERR_OK)) + flags |= PKT_RX_L4_CKSUM_BAD; + else + flags |= PKT_RX_L4_CKSUM_GOOD; + + return flags; +} + /** * DPDK callback for receive. * @@ -917,9 +1786,12 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) struct pp2_bpool *bpool; int i, ret, rx_done = 0; int num; + struct pp2_hif *hif; unsigned int core_id = rte_lcore_id(); - if (unlikely(!q->priv->ppio)) + hif = mrvl_get_hif(q->priv, core_id); + + if (unlikely(!q->priv->ppio || !hif)) return 0; bpool = q->priv->bpool; @@ -934,6 +1806,7 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) for (i = 0; i < nb_pkts; i++) { struct rte_mbuf *mbuf; + uint8_t l3_offset, l4_offset; enum pp2_inq_desc_status status; uint64_t addr; @@ -957,13 +1830,14 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) status = pp2_ppio_inq_desc_get_l2_pkt_error(&descs[i]); if (unlikely(status != PP2_DESC_ERR_OK)) { struct pp2_buff_inf binf = { - .addr = rte_mbuf_data_dma_addr_default(mbuf), + .addr = rte_mbuf_data_iova_default(mbuf), .cookie = (pp2_cookie_t)(uint64_t)mbuf, }; - pp2_bpool_put_buff(hifs[core_id], bpool, &binf); + pp2_bpool_put_buff(hif, bpool, &binf); mrvl_port_bpool_size [bpool->pp2_id][bpool->id][core_id]++; + q->drop_mac++; continue; } @@ -971,8 +1845,18 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) mbuf->pkt_len = pp2_ppio_inq_desc_get_pkt_len(&descs[i]); mbuf->data_len = mbuf->pkt_len; mbuf->port = q->port_id; + mbuf->packet_type = + mrvl_desc_to_packet_type_and_offset(&descs[i], + &l3_offset, + &l4_offset); + mbuf->l2_len = l3_offset; + mbuf->l3_len = l4_offset - l3_offset; + + if (likely(q->cksum_enabled)) + mbuf->ol_flags = mrvl_desc_to_ol_flags(&descs[i]); rx_pkts[rx_done++] = mbuf; + q->bytes_recv += mbuf->pkt_len; } if (rte_spinlock_trylock(&q->priv->lock) == 1) { @@ -996,14 +1880,15 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) q->priv->bpool_init_size); for (i = 0; i < pkt_to_remove; i++) { - pp2_bpool_get_buff(hifs[core_id], bpool, &buff); + ret = pp2_bpool_get_buff(hif, bpool, &buff); + if (ret) + break; mbuf = (struct rte_mbuf *) (cookie_addr_high | buff.cookie); rte_pktmbuf_free(mbuf); } mrvl_port_bpool_size - [bpool->pp2_id][bpool->id][core_id] -= - pkt_to_remove; + [bpool->pp2_id][bpool->id][core_id] -= i; } rte_spinlock_unlock(&q->priv->lock); } @@ -1011,6 +1896,67 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) return rx_done; } +/** + * Prepare offload information. + * + * @param ol_flags + * Offload flags. + * @param packet_type + * Packet type bitfield. + * @param l3_type + * Pointer to the pp2_ouq_l3_type structure. + * @param l4_type + * Pointer to the pp2_outq_l4_type structure. + * @param gen_l3_cksum + * Will be set to 1 in case l3 checksum is computed. + * @param l4_cksum + * Will be set to 1 in case l4 checksum is computed. + * + * @return + * 0 on success, negative error value otherwise. + */ +static inline int +mrvl_prepare_proto_info(uint64_t ol_flags, uint32_t packet_type, + enum pp2_outq_l3_type *l3_type, + enum pp2_outq_l4_type *l4_type, + int *gen_l3_cksum, + int *gen_l4_cksum) +{ + /* + * Based on ol_flags prepare information + * for pp2_ppio_outq_desc_set_proto_info() which setups descriptor + * for offloading. + */ + if (ol_flags & PKT_TX_IPV4) { + *l3_type = PP2_OUTQ_L3_TYPE_IPV4; + *gen_l3_cksum = ol_flags & PKT_TX_IP_CKSUM ? 1 : 0; + } else if (ol_flags & PKT_TX_IPV6) { + *l3_type = PP2_OUTQ_L3_TYPE_IPV6; + /* no checksum for ipv6 header */ + *gen_l3_cksum = 0; + } else { + /* if something different then stop processing */ + return -1; + } + + ol_flags &= PKT_TX_L4_MASK; + if ((packet_type & RTE_PTYPE_L4_TCP) && + ol_flags == PKT_TX_TCP_CKSUM) { + *l4_type = PP2_OUTQ_L4_TYPE_TCP; + *gen_l4_cksum = 1; + } else if ((packet_type & RTE_PTYPE_L4_UDP) && + ol_flags == PKT_TX_UDP_CKSUM) { + *l4_type = PP2_OUTQ_L4_TYPE_UDP; + *gen_l4_cksum = 1; + } else { + *l4_type = PP2_OUTQ_L4_TYPE_OTHER; + /* no checksum for other type */ + *gen_l4_cksum = 0; + } + + return 0; +} + /** * Release already sent buffers to bpool (buffer-pool). * @@ -1027,11 +1973,12 @@ mrvl_rx_pkt_burst(void *rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) */ static inline void mrvl_free_sent_buffers(struct pp2_ppio *ppio, struct pp2_hif *hif, - struct mrvl_shadow_txq *sq, int qid, int force) + unsigned int core_id, struct mrvl_shadow_txq *sq, + int qid, int force) { struct buff_release_entry *entry; uint16_t nb_done = 0, num = 0, skip_bufs = 0; - int i, core_id = rte_lcore_id(); + int i; pp2_ppio_get_num_outq_done(ppio, hif, qid, &nb_done); @@ -1078,6 +2025,7 @@ skip: sq->tail = (sq->tail + num) & MRVL_PP2_TX_SHADOWQ_MASK; sq->size -= num; num = 0; + skip_bufs = 0; } if (likely(num)) { @@ -1104,17 +2052,23 @@ static uint16_t mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) { struct mrvl_txq *q = txq; - struct mrvl_shadow_txq *sq = &shadow_txqs[q->port_id][rte_lcore_id()]; - struct pp2_hif *hif = hifs[rte_lcore_id()]; + struct mrvl_shadow_txq *sq; + struct pp2_hif *hif; struct pp2_ppio_desc descs[nb_pkts]; - int i; + unsigned int core_id = rte_lcore_id(); + int i, ret, bytes_sent = 0; uint16_t num, sq_free_size; + uint64_t addr; + + hif = mrvl_get_hif(q->priv, core_id); + sq = &q->shadow_txqs[core_id]; - if (unlikely(!q->priv->ppio)) + if (unlikely(!q->priv->ppio || !hif)) return 0; if (sq->size) - mrvl_free_sent_buffers(q->priv->ppio, hif, sq, q->queue_id, 0); + mrvl_free_sent_buffers(q->priv->ppio, hif, core_id, + sq, q->queue_id, 0); sq_free_size = MRVL_PP2_TX_SHADOWQ_SIZE - sq->size - 1; if (unlikely(nb_pkts > sq_free_size)) { @@ -1126,6 +2080,9 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) for (i = 0; i < nb_pkts; i++) { struct rte_mbuf *mbuf = tx_pkts[i]; + int gen_l3_cksum, gen_l4_cksum; + enum pp2_outq_l3_type l3_type; + enum pp2_outq_l4_type l4_type; if (likely(nb_pkts - i > MRVL_MUSDK_PREFETCH_SHIFT)) { struct rte_mbuf *pref_pkt_hdr; @@ -1137,19 +2094,36 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) sq->ent[sq->head].buff.cookie = (pp2_cookie_t)(uint64_t)mbuf; sq->ent[sq->head].buff.addr = - rte_mbuf_data_dma_addr_default(mbuf); + rte_mbuf_data_iova_default(mbuf); sq->ent[sq->head].bpool = - (unlikely(mbuf->port == 0xff || mbuf->refcnt > 1)) ? - NULL : mrvl_port_to_bpool_lookup[mbuf->port]; + (unlikely(mbuf->port >= RTE_MAX_ETHPORTS || + mbuf->refcnt > 1)) ? NULL : + mrvl_port_to_bpool_lookup[mbuf->port]; sq->head = (sq->head + 1) & MRVL_PP2_TX_SHADOWQ_MASK; sq->size++; pp2_ppio_outq_desc_reset(&descs[i]); pp2_ppio_outq_desc_set_phys_addr(&descs[i], - rte_pktmbuf_mtophys(mbuf)); + rte_pktmbuf_iova(mbuf)); pp2_ppio_outq_desc_set_pkt_offset(&descs[i], 0); pp2_ppio_outq_desc_set_pkt_len(&descs[i], rte_pktmbuf_pkt_len(mbuf)); + + bytes_sent += rte_pktmbuf_pkt_len(mbuf); + /* + * in case unsupported ol_flags were passed + * do not update descriptor offload information + */ + ret = mrvl_prepare_proto_info(mbuf->ol_flags, mbuf->packet_type, + &l3_type, &l4_type, &gen_l3_cksum, + &gen_l4_cksum); + if (unlikely(ret)) + continue; + + pp2_ppio_outq_desc_set_proto_info(&descs[i], l3_type, l4_type, + mbuf->l2_len, + mbuf->l2_len + mbuf->l3_len, + gen_l3_cksum, gen_l4_cksum); } num = nb_pkts; @@ -1159,10 +2133,15 @@ mrvl_tx_pkt_burst(void *txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts) for (i = nb_pkts; i < num; i++) { sq->head = (MRVL_PP2_TX_SHADOWQ_SIZE + sq->head - 1) & MRVL_PP2_TX_SHADOWQ_MASK; + addr = cookie_addr_high | sq->ent[sq->head].buff.cookie; + bytes_sent -= + rte_pktmbuf_pkt_len((struct rte_mbuf *)addr); } sq->size -= num - nb_pkts; } + q->bytes_sent += bytes_sent; + return nb_pkts; } @@ -1180,6 +2159,7 @@ mrvl_init_pp2(void) memset(&init_params, 0, sizeof(init_params)); init_params.hif_reserved_map = MRVL_MUSDK_HIFS_RESERVED; init_params.bm_pool_reserved_map = MRVL_MUSDK_BPOOLS_RESERVED; + init_params.rss_tbl_reserved_map = MRVL_MUSDK_RSS_RESERVED; return pp2_init(&init_params); } @@ -1295,6 +2275,7 @@ mrvl_eth_dev_create(struct rte_vdev_device *vdev, const char *name) eth_dev->rx_pkt_burst = mrvl_rx_pkt_burst; eth_dev->tx_pkt_burst = mrvl_tx_pkt_burst; + eth_dev->data->kdrv = RTE_KDRV_NONE; eth_dev->data->dev_private = priv; eth_dev->device = &vdev->device; eth_dev->dev_ops = &mrvl_ops; @@ -1328,6 +2309,7 @@ mrvl_eth_dev_destroy(const char *name) priv = eth_dev->data->dev_private; pp2_bpool_deinit(priv->bpool); + used_bpools[priv->pp_id] &= ~(1 << priv->bpool_bit); rte_free(priv); rte_free(eth_dev->data->mac_addrs); rte_eth_dev_release_port(eth_dev); @@ -1351,41 +2333,9 @@ static int mrvl_get_ifnames(const char *key __rte_unused, const char *value, void *extra_args) { - const char **ifnames = extra_args; - - ifnames[mrvl_ports_nb++] = value; - - return 0; -} - -/** - * Initialize per-lcore MUSDK hardware interfaces (hifs). - * - * @return - * 0 on success, negative error value otherwise. - */ -static int -mrvl_init_hifs(void) -{ - struct pp2_hif_params params; - char match[MRVL_MATCH_LEN]; - int i, ret; + struct mrvl_ifnames *ifnames = extra_args; - RTE_LCORE_FOREACH(i) { - ret = mrvl_reserve_bit(&used_hifs, MRVL_MUSDK_HIFS_MAX); - if (ret < 0) - return ret; - - snprintf(match, sizeof(match), "hif-%d", ret); - memset(¶ms, 0, sizeof(params)); - params.match = match; - params.out_size = MRVL_PP2_AGGR_TXQD_MAX; - ret = pp2_hif_init(¶ms, &hifs[i]); - if (ret) { - RTE_LOG(ERR, PMD, "Failed to initialize hif %d\n", i); - return ret; - } - } + ifnames->names[ifnames->idx++] = value; return 0; } @@ -1398,19 +2348,12 @@ mrvl_deinit_hifs(void) { int i; - RTE_LCORE_FOREACH(i) { + for (i = mrvl_lcore_first; i <= mrvl_lcore_last; i++) { if (hifs[i]) pp2_hif_deinit(hifs[i]); } -} - -static void mrvl_set_first_last_cores(int core_id) -{ - if (core_id < mrvl_lcore_first) - mrvl_lcore_first = core_id; - - if (core_id > mrvl_lcore_last) - mrvl_lcore_last = core_id; + used_hifs = MRVL_MUSDK_HIFS_RESERVED; + memset(hifs, 0, sizeof(hifs)); } /** @@ -1426,9 +2369,9 @@ static int rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) { struct rte_kvargs *kvlist; - const char *ifnames[PP2_NUM_ETH_PPIO * PP2_NUM_PKT_PROC]; + struct mrvl_ifnames ifnames; int ret = -EINVAL; - uint32_t i, ifnum, cfgnum, core_id; + uint32_t i, ifnum, cfgnum; const char *params; params = rte_vdev_device_args(vdev); @@ -1440,28 +2383,46 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) return -EINVAL; ifnum = rte_kvargs_count(kvlist, MRVL_IFACE_NAME_ARG); - if (ifnum > RTE_DIM(ifnames)) + if (ifnum > RTE_DIM(ifnames.names)) goto out_free_kvlist; + ifnames.idx = 0; rte_kvargs_process(kvlist, MRVL_IFACE_NAME_ARG, mrvl_get_ifnames, &ifnames); - cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); - if (cfgnum > 1) { - RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n"); - goto out_free_kvlist; - } else if (cfgnum == 1) { - rte_kvargs_process(kvlist, MRVL_CFG_ARG, - mrvl_get_qoscfg, &mrvl_qos_cfg); + + /* + * The below system initialization should be done only once, + * on the first provided configuration file + */ + if (!mrvl_qos_cfg) { + cfgnum = rte_kvargs_count(kvlist, MRVL_CFG_ARG); + RTE_LOG(INFO, PMD, "Parsing config file!\n"); + if (cfgnum > 1) { + RTE_LOG(ERR, PMD, "Cannot handle more than one config file!\n"); + goto out_free_kvlist; + } else if (cfgnum == 1) { + rte_kvargs_process(kvlist, MRVL_CFG_ARG, + mrvl_get_qoscfg, &mrvl_qos_cfg); + } } + if (mrvl_dev_num) + goto init_devices; + + RTE_LOG(INFO, PMD, "Perform MUSDK initializations\n"); /* * ret == -EEXIST is correct, it means DMA * has been already initialized (by another PMD). */ - ret = mv_sys_dma_mem_init(RTE_MRVL_MUSDK_DMA_MEMSIZE); - if (ret < 0 && ret != -EEXIST) - goto out_free_kvlist; + ret = mv_sys_dma_mem_init(MRVL_MUSDK_DMA_MEMSIZE); + if (ret < 0) { + if (ret != -EEXIST) + goto out_free_kvlist; + else + RTE_LOG(INFO, PMD, + "DMA memory has been already initialized by a different driver.\n"); + } ret = mrvl_init_pp2(); if (ret) { @@ -1469,37 +2430,33 @@ rte_pmd_mrvl_probe(struct rte_vdev_device *vdev) goto out_deinit_dma; } - ret = mrvl_init_hifs(); - if (ret) - goto out_deinit_hifs; + memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); + memset(mrvl_port_to_bpool_lookup, 0, sizeof(mrvl_port_to_bpool_lookup)); + mrvl_lcore_first = RTE_MAX_LCORE; + mrvl_lcore_last = 0; + +init_devices: for (i = 0; i < ifnum; i++) { - RTE_LOG(INFO, PMD, "Creating %s\n", ifnames[i]); - ret = mrvl_eth_dev_create(vdev, ifnames[i]); + RTE_LOG(INFO, PMD, "Creating %s\n", ifnames.names[i]); + ret = mrvl_eth_dev_create(vdev, ifnames.names[i]); if (ret) goto out_cleanup; } + mrvl_dev_num += ifnum; rte_kvargs_free(kvlist); - memset(mrvl_port_bpool_size, 0, sizeof(mrvl_port_bpool_size)); - - mrvl_lcore_first = RTE_MAX_LCORE; - mrvl_lcore_last = 0; - - RTE_LCORE_FOREACH(core_id) { - mrvl_set_first_last_cores(core_id); - } - return 0; out_cleanup: for (; i > 0; i--) - mrvl_eth_dev_destroy(ifnames[i]); -out_deinit_hifs: - mrvl_deinit_hifs(); - mrvl_deinit_pp2(); + mrvl_eth_dev_destroy(ifnames.names[i]); + + if (mrvl_dev_num == 0) + mrvl_deinit_pp2(); out_deinit_dma: - mv_sys_dma_mem_destroy(); + if (mrvl_dev_num == 0) + mv_sys_dma_mem_destroy(); out_free_kvlist: rte_kvargs_free(kvlist); @@ -1532,11 +2489,15 @@ rte_pmd_mrvl_remove(struct rte_vdev_device *vdev) rte_eth_dev_get_name_by_port(i, ifname); mrvl_eth_dev_destroy(ifname); + mrvl_dev_num--; } - mrvl_deinit_hifs(); - mrvl_deinit_pp2(); - mv_sys_dma_mem_destroy(); + if (mrvl_dev_num == 0) { + RTE_LOG(INFO, PMD, "Perform MUSDK deinit\n"); + mrvl_deinit_hifs(); + mrvl_deinit_pp2(); + mv_sys_dma_mem_destroy(); + } return 0; }