X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fqede%2Fbase%2Fmcp_public.h;h=98b9723dd421c381ddbac0e8546253e0c110db1a;hb=23bdcedcd8caa0d268b615df3bdb08411f97856e;hp=7ac28202c09d4fcaddd3c7a85a06f21e468e5bdb;hpb=cb051eb251e2d71f30819093038843851af90ff3;p=dpdk.git diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h index 7ac28202c0..98b9723dd4 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -1,9 +1,7 @@ -/* - * Copyright (c) 2016 QLogic Corporation. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2016 - 2018 Cavium Inc. * All rights reserved. - * www.qlogic.com - * - * See LICENSE.qede_pmd for copyright and licensing details. + * www.cavium.com */ /**************************************************************************** @@ -20,6 +18,15 @@ #define MCP_PUBLIC_H #define VF_MAX_STATIC 192 /* In case of AH */ +#define VF_BITMAP_SIZE_IN_DWORDS (VF_MAX_STATIC / 32) +#define VF_BITMAP_SIZE_IN_BYTES (VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32)) + +/* Extended array size to support for 240 VFs 8 dwords */ +#define EXT_VF_MAX_STATIC 240 +#define EXT_VF_BITMAP_SIZE_IN_DWORDS (((EXT_VF_MAX_STATIC - 1) / 32) + 1) +#define EXT_VF_BITMAP_SIZE_IN_BYTES (EXT_VF_BITMAP_SIZE_IN_DWORDS * \ + sizeof(u32)) +#define ADDED_VF_BITMAP_SIZE 2 #define MCP_GLOB_PATH_MAX 2 #define MCP_PORT_MAX 2 /* Global */ @@ -264,11 +271,11 @@ struct couple_mode_teaming { /************************************** * LLDP and DCBX HSI structures **************************************/ -#define LLDP_CHASSIS_ID_STAT_LEN 4 -#define LLDP_PORT_ID_STAT_LEN 4 +#define LLDP_CHASSIS_ID_STAT_LEN 4 +#define LLDP_PORT_ID_STAT_LEN 4 #define DCBX_MAX_APP_PROTOCOL 32 -#define MAX_SYSTEM_LLDP_TLV_DATA 32 - +#define MAX_SYSTEM_LLDP_TLV_DATA 32 /* In dwords. 128 in bytes*/ +#define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ typedef enum _lldp_agent_e { LLDP_NEAREST_BRIDGE = 0, LLDP_NEAREST_NON_TPMR_BRIDGE, @@ -440,6 +447,8 @@ struct dcbx_local_params { #define DCBX_CONFIG_VERSION_DISABLED 0 #define DCBX_CONFIG_VERSION_IEEE 1 #define DCBX_CONFIG_VERSION_CEE 2 +#define DCBX_CONFIG_VERSION_DYNAMIC \ + (DCBX_CONFIG_VERSION_IEEE | DCBX_CONFIG_VERSION_CEE) #define DCBX_CONFIG_VERSION_STATIC 4 u32 flags; @@ -462,11 +471,29 @@ struct dcbx_mib { }; struct lldp_system_tlvs_buffer_s { - u16 valid; - u16 length; + u32 flags; +#define LLDP_SYSTEM_TLV_VALID_MASK 0x1 +#define LLDP_SYSTEM_TLV_VALID_OFFSET 0 +/* This bit defines if system TLVs are instead of mandatory TLVS or in + * addition to them. Set 1 for replacing mandatory TLVs + */ +#define LLDP_SYSTEM_TLV_MANDATORY_MASK 0x2 +#define LLDP_SYSTEM_TLV_MANDATORY_OFFSET 1 +#define LLDP_SYSTEM_TLV_LENGTH_MASK 0xffff0000 +#define LLDP_SYSTEM_TLV_LENGTH_OFFSET 16 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; }; +/* Since this struct is written by MFW and read by driver need to add + * sequence guards (as in case of DCBX MIB) + */ +struct lldp_received_tlvs_s { + u32 prefix_seq_num; + u32 length; + u32 tlvs_buffer[MAX_TLV_BUFFER]; + u32 suffix_seq_num; +}; + struct dcb_dscp_map { u32 flags; #define DCB_DSCP_ENABLE_MASK 0x1 @@ -475,6 +502,18 @@ struct dcb_dscp_map { u32 dscp_pri_map[8]; }; +/************************************** + * Attributes commands + **************************************/ + +enum _attribute_commands_e { + ATTRIBUTE_CMD_READ = 0, + ATTRIBUTE_CMD_WRITE, + ATTRIBUTE_CMD_READ_CLEAR, + ATTRIBUTE_CMD_CLEAR, + ATTRIBUTE_NUM_OF_COMMANDS +}; + /**************************************/ /* */ /* P U B L I C G L O B A L */ @@ -561,6 +600,8 @@ struct public_path { #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) + /*Added to support E5 240 VFs*/ + u32 mcp_vf_disabled2[ADDED_VF_BITMAP_SIZE]; }; /**************************************/ @@ -767,6 +808,8 @@ struct public_port { #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 +#define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 +#define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 @@ -814,6 +857,20 @@ struct public_port { #define ETH_TRANSCEIVER_HAS_DIAGNOSTIC (1 << 6) #define ETH_TRANSCEIVER_IDENT_MASK 0x0000ff00 #define ETH_TRANSCEIVER_IDENT_OFFSET 8 + + u32 oem_cfg_port; +#define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 +#define OEM_CFG_CHANNEL_TYPE_OFFSET 0 +#define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 +#define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 + +#define OEM_CFG_SCHED_TYPE_MASK 0x0000000C +#define OEM_CFG_SCHED_TYPE_OFFSET 2 +#define OEM_CFG_SCHED_TYPE_ETS 0x1 +#define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 + + struct lldp_received_tlvs_s lldp_received_tlvs[LLDP_MAX_LLDP_AGENTS]; + u32 system_lldp_tlvs_buf2[MAX_SYSTEM_LLDP_TLV_DATA]; }; /**************************************/ @@ -873,7 +930,9 @@ struct public_func { #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 u32 status; -#define FUNC_STATUS_VLINK_DOWN 0x00000001 +#define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 +#define FUNC_STATUS_LOGICAL_LINK_UP 0x00000002 +#define FUNC_STATUS_FORCED_LINK 0x00000004 u32 mac_upper; /* MAC */ #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff @@ -930,6 +989,23 @@ struct public_func { #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 #define DRV_ID_DRV_INIT_HW_OFFSET 31 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_OFFSET) + + u32 oem_cfg_func; +#define OEM_CFG_FUNC_TC_MASK 0x0000000F +#define OEM_CFG_FUNC_TC_OFFSET 0 +#define OEM_CFG_FUNC_TC_0 0x0 +#define OEM_CFG_FUNC_TC_1 0x1 +#define OEM_CFG_FUNC_TC_2 0x2 +#define OEM_CFG_FUNC_TC_3 0x3 +#define OEM_CFG_FUNC_TC_4 0x4 +#define OEM_CFG_FUNC_TC_5 0x5 +#define OEM_CFG_FUNC_TC_6 0x6 +#define OEM_CFG_FUNC_TC_7 0x7 + +#define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 +#define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 +#define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 +#define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 }; /**************************************/ @@ -1121,6 +1197,12 @@ struct mdump_retain_data_stc { u32 status; }; +struct attribute_cmd_write_stc { + u32 val; + u32 mask; + u32 offset; +}; + union drv_union_data { struct mcp_mac wol_mac; /* UNLOAD_DONE */ @@ -1152,6 +1234,7 @@ union drv_union_data { struct load_req_stc load_req; struct load_rsp_stc load_rsp; struct mdump_retain_data_stc mdump_retain; + struct attribute_cmd_write_stc attribute_cmd_write; /* ... */ }; @@ -1169,8 +1252,8 @@ struct public_drv_mb { /* - DONT_CARE - Don't flap the link if up */ #define DRV_MSG_CODE_LINK_RESET 0x23000000 - /* Vitaly: LLDP commands */ #define DRV_MSG_CODE_SET_LLDP 0x24000000 +#define DRV_MSG_CODE_REGISTER_LLDP_TLVS_RX 0x24100000 #define DRV_MSG_CODE_SET_DCBX 0x25000000 /* OneView feature driver HSI*/ #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 @@ -1186,7 +1269,24 @@ struct public_drv_mb { */ #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 - +#define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 +#define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 +#define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 +#define DRV_MSG_CODE_OEM_UPDATE_FCOE_CVID 0x3c000000 +#define DRV_MSG_CODE_OEM_UPDATE_FCOE_FABRIC_NAME 0x3d000000 +#define DRV_MSG_CODE_OEM_UPDATE_BOOT_CFG 0x3e000000 +#define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000 +#define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000 +#define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000 +/* params [31:8] - reserved, [7:0] - bitmap */ +#define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 + +/* Param: [0:15] Option ID, [16] - All, [17] - Init, [18] - Commit, + * [19] - Free + */ +#define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000 +/* Param: [0:15] Option ID, [17] - Init, [18] , [19] - Free */ +#define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000 /*deprecated don't use*/ #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 @@ -1199,12 +1299,12 @@ struct public_drv_mb { #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 /* MFW will place the file offset and len in file_att struct */ #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 -/* Read 32bytes of nvram data. Param is [0:23] – Offset [24:31] – - * Len in Bytes +/* Read 32bytes of nvram data. Param is [0:23] ??? Offset [24:31] - + * ??? Len in Bytes */ #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 -/* Writes up to 32Bytes to nvram. Param is [0:23] – Offset [24:31] – - * Len in Bytes. In case this address is in the range of secured file in +/* Writes up to 32Bytes to nvram. Param is [0:23] ??? Offset [24:31] + * ??? Len in Bytes. In case this address is in the range of secured file in * secured mode, the operation will fail */ #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 @@ -1234,6 +1334,7 @@ struct public_drv_mb { #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */ #define DRV_MSG_CODE_SET_VERSION 0x000f0000 +#define DRV_MSG_CODE_MCP_RESET_FORCE 0x000f04ce /* Halts the MCP. To resume MCP, user will need to use * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */ @@ -1382,10 +1483,20 @@ struct public_drv_mb { #define DRV_MB_PARAM_PORT_MASK 0x00600000 #define DRV_MSG_CODE_EXT_PHY_FW_UPGRADE 0x002a0000 +#define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 /* Param: None */ /* Param: Set DRV_MB_PARAM_FEATURE_SUPPORT_* */ #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 /* return FW_MB_PARAM_FEATURE_SUPPORT_* */ #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 +#define DRV_MSG_CODE_READ_WOL_REG 0X00320000 +#define DRV_MSG_CODE_WRITE_WOL_REG 0X00330000 +#define DRV_MSG_CODE_GET_WOL_BUFFER 0X00340000 +/* Param: [0:23] Attribute key, [24:31] Attribute sub command */ +#define DRV_MSG_CODE_ATTRIBUTE 0x00350000 + +/* Param: Password len. Union: Plain Password */ +#define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000 +#define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */ #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff @@ -1404,10 +1515,18 @@ struct public_drv_mb { #define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002 /* LLDP / DCBX params*/ + /* To be used with SET_LLDP command */ #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 #define DRV_MB_PARAM_LLDP_SEND_OFFSET 0 + /* To be used with SET_LLDP and REGISTER_LLDP_TLVS_RX commands */ #define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006 #define DRV_MB_PARAM_LLDP_AGENT_OFFSET 1 + /* To be used with REGISTER_LLDP_TLVS_RX command */ +#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_MASK 0x00000001 +#define DRV_MB_PARAM_LLDP_TLV_RX_VALID_OFFSET 0 +#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_MASK 0x000007f0 +#define DRV_MB_PARAM_LLDP_TLV_RX_TYPE_OFFSET 4 + /* To be used with SET_DCBX command */ #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008 #define DRV_MB_PARAM_DCBX_NOTIFY_OFFSET 3 @@ -1493,9 +1612,22 @@ struct public_drv_mb { #define DRV_MB_PARAM_OV_MTU_SIZE_OFFSET 0 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF +#define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ + DRV_MB_PARAM_ESWITCH_MODE_VEB | \ + DRV_MB_PARAM_ESWITCH_MODE_VEPA) +#define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 +#define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 +#define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 + +#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 +#define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 + #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 +#define DRV_MB_PARAM_SET_LED1_MODE_ON 0x3 +#define DRV_MB_PARAM_SET_LED2_MODE_ON 0x4 +#define DRV_MB_PARAM_SET_ACT_LED_MODE_ON 0x6 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 @@ -1545,9 +1677,40 @@ struct public_drv_mb { #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_MASK 0xFFFF0000 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_OFFSET 16 - +/* driver supports virtual link parameter */ +#define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 + /* Driver attributes params */ +#define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 +#define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF +#define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 +#define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 + +#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0 +/* Option# */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF +#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_OFFSET 16 +/* (Only for Set) Applies option<92>s value to all entities (port/func) + * depending on the option type + */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_OFFSET 17 +/* When set, and state is IDLE, MFW will allocate resources and load + * configuration from NVM + */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_OFFSET 18 +/* (Only for Set) - When set submit changed nvm_cfg1 to flash */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_OFFSET 19 +/* Free - When set, free allocated resources, and return to IDLE state. */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000 +#define SINGLE_NVM_WR_OP(optionId) \ + ((((optionId) & DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK) << \ + DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET) | \ + (DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK | \ + DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK | \ + DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK)) u32 fw_mb_header; -#define FW_MSG_CODE_MASK 0xffff0000 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 @@ -1568,6 +1731,7 @@ struct public_drv_mb { #define FW_MSG_CODE_LINK_RESET_DONE 0x23000000 #define FW_MSG_CODE_SET_LLDP_DONE 0x24000000 #define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000 +#define FW_MSG_CODE_REGISTER_LLDP_TLVS_RX_DONE 0x24100000 #define FW_MSG_CODE_SET_DCBX_DONE 0x25000000 #define FW_MSG_CODE_UPDATE_CURR_CFG_DONE 0x26000000 #define FW_MSG_CODE_UPDATE_BUS_NUM_DONE 0x27000000 @@ -1580,9 +1744,17 @@ struct public_drv_mb { #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 #define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000 +#define FW_MSG_CODE_GET_OEM_UPDATES_DONE 0x41000000 + #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 +#define FW_MSG_CODE_ERR_RESOURCE_TEMPORARY_UNAVAILABLE 0x008b0000 +#define FW_MSG_CODE_ERR_RESOURCE_ALREADY_ALLOCATED 0x008c0000 +#define FW_MSG_CODE_ERR_RESOURCE_NOT_ALLOCATED 0x008d0000 +#define FW_MSG_CODE_ERR_NON_USER_OPTION 0x008e0000 +#define FW_MSG_CODE_ERR_UNKNOWN_OPTION 0x008f0000 +#define FW_MSG_CODE_WAIT 0x00900000 #define FW_MSG_CODE_FLR_ACK 0x02000000 #define FW_MSG_CODE_FLR_NACK 0x02100000 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 @@ -1656,9 +1828,19 @@ struct public_drv_mb { #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_BAD_ASIC 0x00880000 -#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff +#define FW_MSG_CODE_WOL_READ_WRITE_OK 0x00820000 +#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_VAL 0x00830000 +#define FW_MSG_CODE_WOL_READ_WRITE_INVALID_ADDR 0x00840000 +#define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 +#define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 +#define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 +#define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 +#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff +#define FW_MSG_SEQ_NUMBER_OFFSET 0 +#define FW_MSG_CODE_MASK 0xffff0000 +#define FW_MSG_CODE_OFFSET 16 u32 fw_mb_param; /* Resource Allocation params - MFW version support */ #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 @@ -1671,6 +1853,32 @@ struct public_drv_mb { #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports EEE */ #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 +/* MFW supports DRV_LOAD Timeout */ +#define FW_MB_PARAM_FEATURE_SUPPORT_DRV_LOAD_TO 0x00000004 +/* MFW support complete IGU cleanup upon FLR */ +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP 0x00000080 +/* MFW supports virtual link */ +#define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 + +#define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) + +#define FW_MB_PARAM_OEM_UPDATE_MASK 0xFF +#define FW_MB_PARAM_OEM_UPDATE_OFFSET 0 +#define FW_MB_PARAM_OEM_UPDATE_BW 0x01 +#define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02 +#define FW_MB_PARAM_OEM_UPDATE_CFG 0x04 + +#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 +#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0 +#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 +#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1 +#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 +#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2 +#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 +#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3 + +#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF +#define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0 u32 drv_pulse_mb; #define DRV_PULSE_SEQ_MASK 0x00007fff @@ -1735,6 +1943,9 @@ enum MFW_DRV_MSG_TYPE { MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, MFW_DRV_MSG_EEE_NEGOTIATION_COMPLETE, + MFW_DRV_MSG_GET_TLV_REQ, + MFW_DRV_MSG_OEM_CFG_UPDATE, + MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED, MFW_DRV_MSG_MAX };