X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fsfc%2Fbase%2Fefx_regs_mcdi_aoe.h;h=f15c7b2064af602de1ba29366d823cfb7273236d;hb=6cf2f95d4dfbae8c8b4ea31ec899e750dcbc62bb;hp=033d2819f2e29b7f10c471a36a80a4d7cacf3149;hpb=d4b89002b0b7792e5fc0f2f9d8d2e4c5489b33b3;p=dpdk.git diff --git a/drivers/net/sfc/base/efx_regs_mcdi_aoe.h b/drivers/net/sfc/base/efx_regs_mcdi_aoe.h index 033d2819f2..f15c7b2064 100644 --- a/drivers/net/sfc/base/efx_regs_mcdi_aoe.h +++ b/drivers/net/sfc/base/efx_regs_mcdi_aoe.h @@ -1,10 +1,14 @@ /* SPDX-License-Identifier: BSD-3-Clause * - * Copyright 2008-2018 Solarflare Communications Inc. - * All rights reserved. + * Copyright(c) 2019-2020 Xilinx, Inc. + * Copyright(c) 2008-2019 Solarflare Communications Inc. */ -/*! \cidoxg_firmware_mc_cmd */ +/* + * This file is automatically generated. DO NOT EDIT IT. + * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and + * rebuild this file with "make -C doc mcdiheaders". + */ #ifndef _SIENA_MC_DRIVER_PCOL_AOE_H #define _SIENA_MC_DRIVER_PCOL_AOE_H @@ -271,7 +275,9 @@ /* MC_CMD_FC_IN_WRITE32 msgrequest */ #define MC_CMD_FC_IN_WRITE32_LENMIN 16 #define MC_CMD_FC_IN_WRITE32_LENMAX 252 +#define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020 #define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num)) +#define MC_CMD_FC_IN_WRITE32_BUFFER_NUM(len) (((len)-12)/4) /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4 @@ -282,6 +288,7 @@ #define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4 #define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60 +#define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM_MCDI2 252 /* MC_CMD_FC_IN_TRC_READ msgrequest */ #define MC_CMD_FC_IN_TRC_READ_LEN 12 @@ -517,7 +524,9 @@ /* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */ #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20 #define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252 +#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020 #define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num)) +#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_NUM(len) (((len)-16)/4) /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CMD_LEN 4 */ /* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */ @@ -530,6 +539,7 @@ #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59 +#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM_MCDI2 251 /* MC_CMD_FC_IN_UHLINK msgrequest */ #define MC_CMD_FC_IN_UHLINK_LEN 8 @@ -696,8 +706,8 @@ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_DMA_OP_OFST 4 #define MC_CMD_FC_IN_DMA_OP_LEN 4 -#define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ -#define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ +#define MC_CMD_FC_IN_DMA_STOP 0x0 /* enum */ +#define MC_CMD_FC_IN_DMA_READ 0x1 /* enum */ /* MC_CMD_FC_IN_DMA_STOP msgrequest */ #define MC_CMD_FC_IN_DMA_STOP_LEN 12 @@ -726,9 +736,9 @@ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_TIMED_READ_OP_OFST 4 #define MC_CMD_FC_IN_TIMED_READ_OP_LEN 4 -#define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ -#define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ -#define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_SET 0x0 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_GET 0x1 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_CLEAR 0x2 /* enum */ /* MC_CMD_FC_IN_TIMED_READ_SET msgrequest */ #define MC_CMD_FC_IN_TIMED_READ_SET_LEN 52 @@ -771,10 +781,10 @@ #define MC_CMD_FC_IN_TIMED_READ_SET_EVENT_WIDTH 1 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_LBN 3 #define MC_CMD_FC_IN_TIMED_READ_SET_PREREAD_WIDTH 2 -#define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ -#define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ -#define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ -#define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_SET_NONE 0x0 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_SET_READ 0x1 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_SET_WRITE 0x2 /* enum */ +#define MC_CMD_FC_IN_TIMED_READ_SET_READWRITE 0x3 /* enum */ /* Period at which reads are performed (100ms units) */ #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_OFST 48 #define MC_CMD_FC_IN_TIMED_READ_SET_PERIOD_LEN 4 @@ -805,8 +815,8 @@ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_LOG_OP_OFST 4 #define MC_CMD_FC_IN_LOG_OP_LEN 4 -#define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ -#define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ +#define MC_CMD_FC_IN_LOG_ADDR_RANGE 0x0 /* enum */ +#define MC_CMD_FC_IN_LOG_JTAG_UART 0x1 /* enum */ /* MC_CMD_FC_IN_LOG_ADDR_RANGE msgrequest */ #define MC_CMD_FC_IN_LOG_ADDR_RANGE_LEN 20 @@ -834,31 +844,33 @@ #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_OFST 8 #define MC_CMD_FC_IN_LOG_JTAG_UART_ENABLE_LEN 4 -/* MC_CMD_FC_IN_CLOCK msgrequest */ +/* MC_CMD_FC_IN_CLOCK msgrequest: Perform a clock operation */ #define MC_CMD_FC_IN_CLOCK_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_CLOCK_OP_OFST 4 #define MC_CMD_FC_IN_CLOCK_OP_LEN 4 -#define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ -#define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ -/* Perform a clock operation */ +#define MC_CMD_FC_IN_CLOCK_GET_TIME 0x0 /* enum */ +#define MC_CMD_FC_IN_CLOCK_SET_TIME 0x1 /* enum */ #define MC_CMD_FC_IN_CLOCK_ID_OFST 8 #define MC_CMD_FC_IN_CLOCK_ID_LEN 4 -#define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ -#define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ +#define MC_CMD_FC_IN_CLOCK_STATS 0x0 /* enum */ +#define MC_CMD_FC_IN_CLOCK_MAC 0x1 /* enum */ -/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest */ +/* MC_CMD_FC_IN_CLOCK_GET_TIME msgrequest: Retrieve the clock value of the + * specified clock + */ #define MC_CMD_FC_IN_CLOCK_GET_TIME_LEN 12 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CMD_LEN 4 */ /* MC_CMD_FC_IN_CLOCK_OP_OFST 4 */ /* MC_CMD_FC_IN_CLOCK_OP_LEN 4 */ -/* Retrieve the clock value of the specified clock */ /* MC_CMD_FC_IN_CLOCK_ID_OFST 8 */ /* MC_CMD_FC_IN_CLOCK_ID_LEN 4 */ -/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest */ +/* MC_CMD_FC_IN_CLOCK_SET_TIME msgrequest: Set the clock value of the specified + * clock + */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_LEN 24 /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CMD_LEN 4 */ @@ -870,7 +882,6 @@ #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LEN 8 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_LO_OFST 12 #define MC_CMD_FC_IN_CLOCK_SET_TIME_SECONDS_HI_OFST 16 -/* Set the clock value of the specified clock */ #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_OFST 20 #define MC_CMD_FC_IN_CLOCK_SET_TIME_NANOSECONDS_LEN 4 @@ -880,16 +891,16 @@ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_DDR_OP_OFST 4 #define MC_CMD_FC_IN_DDR_OP_LEN 4 -#define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ -#define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ -#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ +#define MC_CMD_FC_IN_DDR_SET_SPD 0x0 /* enum */ +#define MC_CMD_FC_IN_DDR_GET_STATUS 0x1 /* enum */ +#define MC_CMD_FC_IN_DDR_SET_INFO 0x2 /* enum */ #define MC_CMD_FC_IN_DDR_BANK_OFST 8 #define MC_CMD_FC_IN_DDR_BANK_LEN 4 -#define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ -#define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ -#define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ -#define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ -#define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ +#define MC_CMD_FC_IN_DDR_BANK_B0 0x0 /* enum */ +#define MC_CMD_FC_IN_DDR_BANK_B1 0x1 /* enum */ +#define MC_CMD_FC_IN_DDR_BANK_T0 0x2 /* enum */ +#define MC_CMD_FC_IN_DDR_BANK_T1 0x3 /* enum */ +#define MC_CMD_FC_IN_DDR_NUM_BANKS 0x4 /* enum */ /* MC_CMD_FC_IN_DDR_SET_SPD msgrequest */ #define MC_CMD_FC_IN_DDR_SET_SPD_LEN 148 @@ -903,7 +914,7 @@ /* Flags */ #define MC_CMD_FC_IN_DDR_FLAGS_OFST 12 #define MC_CMD_FC_IN_DDR_FLAGS_LEN 4 -#define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ +#define MC_CMD_FC_IN_DDR_SET_SPD_ACTIVE 0x1 /* enum */ /* 128-byte page of serial presence detect data read from module's EEPROM */ #define MC_CMD_FC_IN_DDR_SPD_OFST 16 #define MC_CMD_FC_IN_DDR_SPD_LEN 1 @@ -1020,7 +1031,9 @@ /* MC_CMD_FC_IN_SPI_WRITE msgrequest */ #define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16 #define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252 +#define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020 #define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num)) +#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_NUM(len) (((len)-12)/4) /* MC_CMD_FC_IN_CMD_OFST 0 */ /* MC_CMD_FC_IN_CMD_LEN 4 */ #define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4 @@ -1031,6 +1044,7 @@ #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1 #define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60 +#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM_MCDI2 252 /* MC_CMD_FC_IN_SPI_ERASE msgrequest */ #define MC_CMD_FC_IN_SPI_ERASE_LEN 16 @@ -1243,11 +1257,14 @@ /* MC_CMD_FC_OUT_READ32 msgresponse */ #define MC_CMD_FC_OUT_READ32_LENMIN 4 #define MC_CMD_FC_OUT_READ32_LENMAX 252 +#define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020 #define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num)) +#define MC_CMD_FC_OUT_READ32_BUFFER_NUM(len) (((len)-0)/4) #define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0 #define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4 #define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63 +#define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM_MCDI2 255 /* MC_CMD_FC_OUT_WRITE32 msgresponse */ #define MC_CMD_FC_OUT_WRITE32_LEN 0 @@ -1297,33 +1314,33 @@ #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_RX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_RX_NSTATS -#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ -#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ -#define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ -#define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ -#define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ -#define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ -#define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ -#define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ -#define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ -#define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ -#define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ -#define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ -#define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_OCTETS 0x0 /* enum */ +#define MC_CMD_FC_MAC_RX_OCTETS_OK 0x1 /* enum */ +#define MC_CMD_FC_MAC_RX_ALIGNMENT_ERRORS 0x2 /* enum */ +#define MC_CMD_FC_MAC_RX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ +#define MC_CMD_FC_MAC_RX_FRAMES_OK 0x4 /* enum */ +#define MC_CMD_FC_MAC_RX_CRC_ERRORS 0x5 /* enum */ +#define MC_CMD_FC_MAC_RX_VLAN_OK 0x6 /* enum */ +#define MC_CMD_FC_MAC_RX_ERRORS 0x7 /* enum */ +#define MC_CMD_FC_MAC_RX_UCAST_PKTS 0x8 /* enum */ +#define MC_CMD_FC_MAC_RX_MULTICAST_PKTS 0x9 /* enum */ +#define MC_CMD_FC_MAC_RX_BROADCAST_PKTS 0xa /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_DROP_EVENTS 0xb /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS 0xc /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_UNDERSIZE_PKTS 0xd /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_64 0xe /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_65_127 0xf /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_128_255 0x10 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_256_511 0x11 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_512_1023 0x12 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_1024_1518 0x13 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_PKTS_1519_MAX 0x14 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_OVERSIZE_PKTS 0x15 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_JABBERS 0x16 /* enum */ +#define MC_CMD_FC_MAC_RX_STATS_FRAGMENTS 0x17 /* enum */ +#define MC_CMD_FC_MAC_RX_MAC_CONTROL_FRAMES 0x18 /* enum */ /* enum: (Last entry) */ -#define MC_CMD_FC_MAC_RX_NSTATS 0x19 +#define MC_CMD_FC_MAC_RX_NSTATS 0x19 /* MC_CMD_FC_OUT_MAC_GET_TX_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_TX_NSTATS))+1))>>3) @@ -1332,30 +1349,30 @@ #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_LO_OFST 0 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_HI_OFST 4 #define MC_CMD_FC_OUT_MAC_GET_TX_STATS_STATISTICS_NUM MC_CMD_FC_MAC_TX_NSTATS -#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ -#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ -#define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ -#define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ -#define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ -#define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ -#define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ -#define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ -#define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ -#define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ -#define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ -#define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ -#define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_OCTETS 0x0 /* enum */ +#define MC_CMD_FC_MAC_TX_OCTETS_OK 0x1 /* enum */ +#define MC_CMD_FC_MAC_TX_ALIGNMENT_ERRORS 0x2 /* enum */ +#define MC_CMD_FC_MAC_TX_PAUSE_MAC_CTRL_FRAMES 0x3 /* enum */ +#define MC_CMD_FC_MAC_TX_FRAMES_OK 0x4 /* enum */ +#define MC_CMD_FC_MAC_TX_CRC_ERRORS 0x5 /* enum */ +#define MC_CMD_FC_MAC_TX_VLAN_OK 0x6 /* enum */ +#define MC_CMD_FC_MAC_TX_ERRORS 0x7 /* enum */ +#define MC_CMD_FC_MAC_TX_UCAST_PKTS 0x8 /* enum */ +#define MC_CMD_FC_MAC_TX_MULTICAST_PKTS 0x9 /* enum */ +#define MC_CMD_FC_MAC_TX_BROADCAST_PKTS 0xa /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_DROP_EVENTS 0xb /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS 0xc /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_UNDERSIZE_PKTS 0xd /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_64 0xe /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_65_127 0xf /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_128_255 0x10 /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_256_511 0x11 /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_512_1023 0x12 /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_1024_1518 0x13 /* enum */ +#define MC_CMD_FC_MAC_TX_STATS_PKTS_1519_TX_MTU 0x14 /* enum */ +#define MC_CMD_FC_MAC_TX_MAC_CONTROL_FRAMES 0x15 /* enum */ /* enum: (Last entry) */ -#define MC_CMD_FC_MAC_TX_NSTATS 0x16 +#define MC_CMD_FC_MAC_TX_NSTATS 0x16 /* MC_CMD_FC_OUT_MAC_GET_STATS msgresponse */ #define MC_CMD_FC_OUT_MAC_GET_STATS_LEN ((((0-1+(64*MC_CMD_FC_MAC_NSTATS_PER_BLOCK))+1))>>3) @@ -1791,17 +1808,17 @@ /* Options for the map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_OFST 4 #define MC_CMD_FC_OUT_READ_MAP_INDEX_OPTIONS_LEN 4 -#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ -#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_8 0x0 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_16 0x1 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_32 0x2 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_64 0x3 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_ALIGN_MASK 0x3 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_FC 0x4 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_PATH_MEM 0x8 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_READ 0x10 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_PERM_WRITE 0x20 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_FREE 0x0 /* enum */ +#define MC_CMD_FC_OUT_READ_MAP_INDEX_LICENSE_LICENSED 0x40 /* enum */ /* Address of start of map */ #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_OFST 8 #define MC_CMD_FC_OUT_READ_MAP_INDEX_ADDRESS_LEN 8 @@ -1855,11 +1872,14 @@ /* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */ #define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4 #define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252 +#define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020 #define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num)) +#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_NUM(len) (((len)-0)/4) #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63 +#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM_MCDI2 255 /* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */ #define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0 @@ -2010,12 +2030,15 @@ /* MC_CMD_FC_OUT_DMA_READ msgresponse */ #define MC_CMD_FC_OUT_DMA_READ_LENMIN 1 #define MC_CMD_FC_OUT_DMA_READ_LENMAX 252 +#define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020 #define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num)) +#define MC_CMD_FC_OUT_DMA_READ_DATA_NUM(len) (((len)-0)/1) /* The data read */ #define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0 #define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1 #define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1 #define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252 +#define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM_MCDI2 1020 /* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */ #define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4 @@ -2109,7 +2132,9 @@ /* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */ #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248 +#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num)) +#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_NUM(len) (((len)-0)/8) #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4 @@ -2120,15 +2145,19 @@ #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0 #define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31 +#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127 /* MC_CMD_FC_OUT_SPI_READ msgresponse */ #define MC_CMD_FC_OUT_SPI_READ_LENMIN 4 #define MC_CMD_FC_OUT_SPI_READ_LENMAX 252 +#define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020 #define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num)) +#define MC_CMD_FC_OUT_SPI_READ_BUFFER_NUM(len) (((len)-0)/4) #define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1 #define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63 +#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM_MCDI2 255 /* MC_CMD_FC_OUT_SPI_WRITE msgresponse */ #define MC_CMD_FC_OUT_SPI_WRITE_LEN 0 @@ -2253,6 +2282,8 @@ #define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19 /* enum: Get FC assert information and register dump */ #define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a +/* enum: Set MUM startup FUSE byte with extended delay */ +#define MC_CMD_AOE_OP_MUM_STARTUP_FUSE 0x1b /* MC_CMD_AOE_OUT msgresponse */ #define MC_CMD_AOE_OUT_LEN 0 @@ -2325,21 +2356,21 @@ #define MC_CMD_AOE_IN_POWER_OP_OFST 4 #define MC_CMD_AOE_IN_POWER_OP_LEN 4 /* enum: Turn off FPGA power */ -#define MC_CMD_AOE_IN_POWER_OFF 0x0 +#define MC_CMD_AOE_IN_POWER_OFF 0x0 /* enum: Turn on FPGA power */ -#define MC_CMD_AOE_IN_POWER_ON 0x1 +#define MC_CMD_AOE_IN_POWER_ON 0x1 /* enum: Clear peak power measurement */ -#define MC_CMD_AOE_IN_POWER_CLEAR 0x2 +#define MC_CMD_AOE_IN_POWER_CLEAR 0x2 /* enum: Show current power in sensors output */ -#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 +#define MC_CMD_AOE_IN_POWER_SHOW_CURRENT 0x3 /* enum: Show peak power in sensors output */ -#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 +#define MC_CMD_AOE_IN_POWER_SHOW_PEAK 0x4 /* enum: Show current DDR current */ -#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 +#define MC_CMD_AOE_IN_POWER_DDR_LAST 0x5 /* enum: Show peak DDR current */ -#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 +#define MC_CMD_AOE_IN_POWER_DDR_PEAK 0x6 /* enum: Clear peak DDR current */ -#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 +#define MC_CMD_AOE_IN_POWER_DDR_CLEAR 0x7 /* MC_CMD_AOE_IN_LOAD msgrequest */ #define MC_CMD_AOE_IN_LOAD_LEN 8 @@ -2408,7 +2439,9 @@ /* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */ #define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12 #define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252 +#define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020 #define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num)) +#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) /* MC_CMD_AOE_IN_CMD_OFST 0 */ /* MC_CMD_AOE_IN_CMD_LEN 4 */ #define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4 @@ -2417,6 +2450,7 @@ #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1 #define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61 +#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 /* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */ #define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8 @@ -2454,21 +2488,21 @@ #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_LBN 0 #define MC_CMD_AOE_IN_LINK_STATE_CONFIG_MODE_WIDTH 8 /* enum: AOE and associated external port */ -#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 +#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_SEPARATE 0x0 /* enum: AOE and OR of all external ports */ -#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 +#define MC_CMD_AOE_IN_LINK_STATE_SIMPLE_COMBINED 0x1 /* enum: Individual ports */ -#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 +#define MC_CMD_AOE_IN_LINK_STATE_DIAGNOSTIC 0x2 /* enum: Configure link state mode on given AOE port */ -#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 +#define MC_CMD_AOE_IN_LINK_STATE_CUSTOM 0x3 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_LBN 8 #define MC_CMD_AOE_IN_LINK_STATE_OPERATION_WIDTH 8 /* enum: No-op */ -#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 +#define MC_CMD_AOE_IN_LINK_STATE_OP_NONE 0x0 /* enum: logical OR of all SFP ports link status */ -#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 +#define MC_CMD_AOE_IN_LINK_STATE_OP_OR 0x1 /* enum: logical AND of all SFP ports link status */ -#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 +#define MC_CMD_AOE_IN_LINK_STATE_OP_AND 0x2 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_LBN 16 #define MC_CMD_AOE_IN_LINK_STATE_SFP_MASK_WIDTH 16 @@ -2490,9 +2524,9 @@ #define MC_CMD_AOE_IN_SIENA_STATS_MODE_OFST 4 #define MC_CMD_AOE_IN_SIENA_STATS_MODE_LEN 4 /* enum: Statistics from Siena (default) */ -#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 +#define MC_CMD_AOE_IN_SIENA_STATS_STATS_SIENA 0x0 /* enum: Statistics from AOE external ports */ -#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 +#define MC_CMD_AOE_IN_SIENA_STATS_STATS_AOE 0x1 /* MC_CMD_AOE_IN_ASIC_STATS msgrequest */ #define MC_CMD_AOE_IN_ASIC_STATS_LEN 8 @@ -2502,9 +2536,9 @@ #define MC_CMD_AOE_IN_ASIC_STATS_MODE_OFST 4 #define MC_CMD_AOE_IN_ASIC_STATS_MODE_LEN 4 /* enum: Statistics from the ASIC (default) */ -#define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 +#define MC_CMD_AOE_IN_ASIC_STATS_STATS_ASIC 0x0 /* enum: Statistics from AOE external ports */ -#define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 +#define MC_CMD_AOE_IN_ASIC_STATS_STATS_AOE 0x1 /* MC_CMD_AOE_IN_DDR msgrequest */ #define MC_CMD_AOE_IN_DDR_LEN 12 @@ -2574,6 +2608,17 @@ #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0 #define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1 +/* MC_CMD_AOE_IN_MUM_STARTUP_FUSE msgrequest: On AOE2, set MUM startup FUSE + * byte with extended delay of 64ms. On some servers with noisy power rails, + * this ensures that the MUM IO pins do not show spurious transitions while the + * power rails are stabilising. Note that this operation requires a hard- + * powercycle to take effect. See bug76446. + */ +#define MC_CMD_AOE_IN_MUM_STARTUP_FUSE_LEN 4 +/* Must be MC_CMD_AOE_OP_MUM_STARTUP_FUSE */ +/* MC_CMD_AOE_IN_CMD_OFST 0 */ +/* MC_CMD_AOE_IN_CMD_LEN 4 */ + /* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */ #define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144 /* Assertion status flag. */ @@ -2629,8 +2674,8 @@ /* FPGA type - read from CPLD straps */ #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_OFST 16 #define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_LEN 4 -#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ -#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A5_C2 0x1 /* enum */ +#define MC_CMD_AOE_OUT_INFO_FPGA_TYPE_A7_C2 0x2 /* enum */ /* FPGA state (debug) */ #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_OFST 20 #define MC_CMD_AOE_OUT_INFO_FPGA_STATE_LEN 4 @@ -2648,29 +2693,29 @@ #define MC_CMD_AOE_OUT_INFO_FLAGS_OFST 32 #define MC_CMD_AOE_OUT_INFO_FLAGS_LEN 4 /* enum: Power to FPGA supplied by PEG connector, not PCIe bus */ -#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 +#define MC_CMD_AOE_OUT_INFO_PEG_POWER 0x1 /* enum: CPLD apparently good */ -#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 +#define MC_CMD_AOE_OUT_INFO_CPLD_GOOD 0x2 /* enum: FPGA working normally */ -#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 +#define MC_CMD_AOE_OUT_INFO_FPGA_GOOD 0x4 /* enum: FPGA is powered */ -#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 +#define MC_CMD_AOE_OUT_INFO_FPGA_POWER 0x8 /* enum: Board has incompatible SODIMMs fitted */ -#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 +#define MC_CMD_AOE_OUT_INFO_BAD_SODIMM 0x10 /* enum: Board has ByteBlaster connected */ -#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 +#define MC_CMD_AOE_OUT_INFO_HAS_BYTEBLASTER 0x20 /* enum: FPGA Boot flash has an invalid header. */ -#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 +#define MC_CMD_AOE_OUT_INFO_FPGA_BAD_BOOT_HDR 0x40 /* enum: FPGA Application flash is accessible. */ -#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 +#define MC_CMD_AOE_OUT_INFO_FPGA_APP_FLASH_GOOD 0x80 /* Revision of Modena and Sorrento boards. Sorrento can be R1_2 or R1_3. */ #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_OFST 36 #define MC_CMD_AOE_OUT_INFO_BOARD_REVISION_LEN 4 -#define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ -#define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ -#define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ -#define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ -#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ +#define MC_CMD_AOE_OUT_INFO_UNKNOWN 0x0 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_0 0x10 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_1 0x11 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_2 0x12 /* enum */ +#define MC_CMD_AOE_OUT_INFO_R1_3 0x13 /* enum */ /* Result of FC booting - not valid while a ByteBlaster is connected. */ #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_OFST 40 #define MC_CMD_AOE_OUT_INFO_FC_BOOT_RESULT_LEN 4 @@ -2756,12 +2801,15 @@ /* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */ #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4 #define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252 +#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020 #define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num)) +#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_NUM(len) (((len)-0)/4) /* Failure counts for each fan */ #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1 #define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63 +#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM_MCDI2 255 /* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */ #define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4 @@ -2794,7 +2842,9 @@ /* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */ #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252 +#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num)) +#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1) /* in bytes */ #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4 @@ -2802,11 +2852,14 @@ #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1 #define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248 +#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016 /* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */ #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12 #define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252 +#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020 #define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num)) +#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4) /* Used to align the in and out data blocks so the MC can re-use the cmd */ #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4 @@ -2817,6 +2870,7 @@ #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1 #define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61 +#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM_MCDI2 253 /* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */ #define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0 @@ -2824,7 +2878,9 @@ /* MC_CMD_AOE_OUT_DDR msgresponse */ #define MC_CMD_AOE_OUT_DDR_LENMIN 17 #define MC_CMD_AOE_OUT_DDR_LENMAX 252 +#define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020 #define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num)) +#define MC_CMD_AOE_OUT_DDR_SPD_NUM(len) (((len)-16)/1) /* Information on the module. */ #define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0 #define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4 @@ -2850,6 +2906,7 @@ #define MC_CMD_AOE_OUT_DDR_SPD_LEN 1 #define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1 #define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236 +#define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM_MCDI2 1004 /* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */ #define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0 @@ -2909,5 +2966,12 @@ /* MC_CMD_AOE_OUT_FC_BOOT msgresponse */ #define MC_CMD_AOE_OUT_FC_BOOT_LEN 0 +/* MC_CMD_AOE_OUT_MUM_STARTUP_FUSE msgresponse */ +#define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_LEN 4 +/* Current value of startup FUSE byte (fusebyte#4) read back after the update + * operation. + */ +#define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_OFST 0 +#define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_LEN 4 + #endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */ -/*! \cidoxg_end */