X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fthunderx%2Fbase%2Fnicvf_hw.h;h=2b8738b162b00a7994ef19922396ca80abd85147;hb=a518584d1fcfe377c86f518c917a205b692c838c;hp=a7ae5313c0a8971cee9db5116ceb7791bebabb8b;hpb=7694fab264ac666d62a4cae04f2979991ce64259;p=dpdk.git

diff --git a/drivers/net/thunderx/base/nicvf_hw.h b/drivers/net/thunderx/base/nicvf_hw.h
index a7ae5313c0..2b8738b162 100644
--- a/drivers/net/thunderx/base/nicvf_hw.h
+++ b/drivers/net/thunderx/base/nicvf_hw.h
@@ -37,18 +37,23 @@
 
 #include "nicvf_hw_defs.h"
 
-#define	PCI_VENDOR_ID_CAVIUM			0x177D
-#define	PCI_DEVICE_ID_THUNDERX_PASS1_NICVF	0x0011
-#define	PCI_DEVICE_ID_THUNDERX_PASS2_NICVF	0xA034
-#define	PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF	0xA11E
-#define	PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF	0xA134
+#define	PCI_VENDOR_ID_CAVIUM				0x177D
+#define	PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF	0x0011
+#define	PCI_DEVICE_ID_THUNDERX_NICVF			0xA034
+#define	PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF		0xA11E
+#define	PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF		0xA134
+#define	PCI_SUB_DEVICE_ID_CN81XX_NICVF			0xA234
 
 #define NICVF_ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
 
-#define NICVF_PASS1	(PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF)
-#define NICVF_PASS2	(PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF)
+#define NICVF_GET_RX_STATS(reg) \
+	nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
+#define NICVF_GET_TX_STATS(reg) \
+	nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
 
-#define NICVF_CAP_TUNNEL_PARSING          (1ULL << 0)
+#define NICVF_CAP_TUNNEL_PARSING	(1ULL << 0)
+/* Additional word in Rx descriptor to hold optional tunneling extension info */
+#define NICVF_CAP_CQE_RX2		(1ULL << 1)
 
 enum nicvf_tns_mode {
 	NIC_TNS_BYPASS_MODE,
@@ -80,7 +85,40 @@ enum nicvf_err_e {
 	NICVF_ERR_RSS_GET_SZ,    /* -8171 */
 };
 
-typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *opaque);
+typedef nicvf_phys_addr_t (*rbdr_pool_get_handler)(void *dev, void *opaque);
+
+struct nicvf_hw_rx_qstats {
+	uint64_t q_rx_bytes;
+	uint64_t q_rx_packets;
+};
+
+struct nicvf_hw_tx_qstats {
+	uint64_t q_tx_bytes;
+	uint64_t q_tx_packets;
+};
+
+struct nicvf_hw_stats {
+	uint64_t rx_bytes;
+	uint64_t rx_ucast_frames;
+	uint64_t rx_bcast_frames;
+	uint64_t rx_mcast_frames;
+	uint64_t rx_fcs_errors;
+	uint64_t rx_l2_errors;
+	uint64_t rx_drop_red;
+	uint64_t rx_drop_red_bytes;
+	uint64_t rx_drop_overrun;
+	uint64_t rx_drop_overrun_bytes;
+	uint64_t rx_drop_bcast;
+	uint64_t rx_drop_mcast;
+	uint64_t rx_drop_l3_bcast;
+	uint64_t rx_drop_l3_mcast;
+
+	uint64_t tx_bytes_ok;
+	uint64_t tx_ucast_frames_ok;
+	uint64_t tx_bcast_frames_ok;
+	uint64_t tx_mcast_frames_ok;
+	uint64_t tx_drops;
+};
 
 struct nicvf_rss_reta_info {
 	uint8_t hash_bits;
@@ -156,8 +194,8 @@ int nicvf_qset_reclaim(struct nicvf *nic);
 
 int nicvf_qset_rbdr_config(struct nicvf *nic, uint16_t qidx);
 int nicvf_qset_rbdr_reclaim(struct nicvf *nic, uint16_t qidx);
-int nicvf_qset_rbdr_precharge(struct nicvf *nic, uint16_t ridx,
-			      rbdr_pool_get_handler handler, void *opaque,
+int nicvf_qset_rbdr_precharge(void *dev, struct nicvf *nic,
+			      uint16_t ridx, rbdr_pool_get_handler handler,
 			      uint32_t max_buffs);
 int nicvf_qset_rbdr_active(struct nicvf *nic, uint16_t qidx);
 
@@ -193,4 +231,10 @@ uint64_t nicvf_rss_get_cfg(struct nicvf *nic);
 
 int nicvf_loopback_config(struct nicvf *nic, bool enable);
 
+void nicvf_hw_get_stats(struct nicvf *nic, struct nicvf_hw_stats *stats);
+void nicvf_hw_get_rx_qstats(struct nicvf *nic,
+			    struct nicvf_hw_rx_qstats *qstats, uint16_t qidx);
+void nicvf_hw_get_tx_qstats(struct nicvf *nic,
+			    struct nicvf_hw_tx_qstats *qstats, uint16_t qidx);
+
 #endif /* _THUNDERX_NICVF_HW_H */