X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=lib%2Flibrte_eal%2Fcommon%2Finclude%2Frte_memory.h;h=1bed4153d31ccbb363c4916507c38b7d90c6f950;hb=67b6d3039e9edbc4624c878c6930be5e126e8b58;hp=4ae3bf75a70cb3773b09b45842c58f8b56467276;hpb=53a9ca3c570311a8e729cf86ea5a3da0a2520e8e;p=dpdk.git diff --git a/lib/librte_eal/common/include/rte_memory.h b/lib/librte_eal/common/include/rte_memory.h index 4ae3bf75a7..1bed4153d3 100644 --- a/lib/librte_eal/common/include/rte_memory.h +++ b/lib/librte_eal/common/include/rte_memory.h @@ -1,13 +1,13 @@ /*- * BSD LICENSE - * + * * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: - * + * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright @@ -17,7 +17,7 @@ * * Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -42,6 +42,7 @@ #include #include +#include #ifdef RTE_EXEC_ENV_LINUXAPP #include @@ -52,27 +53,35 @@ extern "C" { #endif enum rte_page_sizes { - RTE_PGSIZE_4K = 1 << 12, - RTE_PGSIZE_2M = RTE_PGSIZE_4K << 9, - RTE_PGSIZE_1G = RTE_PGSIZE_2M <<9 + RTE_PGSIZE_4K = 1ULL << 12, + RTE_PGSIZE_64K = 1ULL << 16, + RTE_PGSIZE_256K = 1ULL << 18, + RTE_PGSIZE_2M = 1ULL << 21, + RTE_PGSIZE_16M = 1ULL << 24, + RTE_PGSIZE_256M = 1ULL << 28, + RTE_PGSIZE_512M = 1ULL << 29, + RTE_PGSIZE_1G = 1ULL << 30, + RTE_PGSIZE_4G = 1ULL << 32, + RTE_PGSIZE_16G = 1ULL << 34, }; #define SOCKET_ID_ANY -1 /**< Any NUMA socket. */ -#ifndef CACHE_LINE_SIZE -#define CACHE_LINE_SIZE 64 /**< Cache line size. */ +#ifndef RTE_CACHE_LINE_SIZE +#define RTE_CACHE_LINE_SIZE 64 /**< Cache line size. */ #endif -#define CACHE_LINE_MASK (CACHE_LINE_SIZE-1) /**< Cache line mask. */ +#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) /**< Cache line mask. */ -#define CACHE_LINE_ROUNDUP(size) \ - (CACHE_LINE_SIZE * ((size + CACHE_LINE_SIZE - 1) / CACHE_LINE_SIZE)) +#define RTE_CACHE_LINE_ROUNDUP(size) \ + (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE)) /**< Return the first cache-aligned value greater or equal to size. */ /** * Force alignment to cache line. */ -#define __rte_cache_aligned __attribute__((__aligned__(CACHE_LINE_SIZE))) +#define __rte_cache_aligned __attribute__((__aligned__(RTE_CACHE_LINE_SIZE))) typedef uint64_t phys_addr_t; /**< Physical address definition. */ +#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1) /** * Physical memory segment descriptor. @@ -87,16 +96,37 @@ struct rte_memseg { phys_addr_t ioremap_addr; /**< Real physical address inside the VM */ #endif size_t len; /**< Length of the segment. */ - size_t hugepage_sz; /**< The pagesize of underlying memory */ + uint64_t hugepage_sz; /**< The pagesize of underlying memory */ int32_t socket_id; /**< NUMA socket ID. */ uint32_t nchannel; /**< Number of channels. */ uint32_t nrank; /**< Number of ranks. */ #ifdef RTE_LIBRTE_XEN_DOM0 /**< store segment MFNs */ - uint64_t mfn[DOM0_NUM_MEMBLOCK]; + uint64_t mfn[DOM0_NUM_MEMBLOCK]; #endif } __attribute__((__packed__)); +/** + * Lock page in physical memory and prevent from swapping. + * + * @param virt + * The virtual address. + * @return + * 0 on success, negative on error. + */ +int rte_mem_lock_page(const void *virt); + +/** + * Get physical address of any mapped virtual address in the current process. + * It is found by browsing the /proc/self/pagemap special file. + * The page must be locked. + * + * @param virt + * The virtual address. + * @return + * The physical address or RTE_BAD_PHYS_ADDR on error. + */ +phys_addr_t rte_mem_virt2phy(const void *virt); /** * Get the layout of the available physical memory. @@ -117,8 +147,11 @@ const struct rte_memseg *rte_eal_get_physmem_layout(void); /** * Dump the physical memory layout to the console. + * + * @param f + * A pointer to a file for output */ -void rte_dump_physmem_layout(void); +void rte_dump_physmem_layout(FILE *f); /** * Get the total amount of available physical memory. @@ -150,7 +183,7 @@ unsigned rte_memory_get_nrank(void); /** * Return the physical address of elt, which is an element of the pool mp. * - * @param memseg_id + * @param memseg_id * The mempool is from which memory segment. * @param phy_addr * physical address of elt. @@ -161,22 +194,22 @@ unsigned rte_memory_get_nrank(void); phys_addr_t rte_mem_phy2mch(uint32_t memseg_id, const phys_addr_t phy_addr); /** - * Memory init for supporting application running on Xen domain0. - * - * @param void - * - * @return + * Memory init for supporting application running on Xen domain0. + * + * @param void + * + * @return * 0: successfully - * negative: error - */ + * negative: error + */ int rte_xen_dom0_memory_init(void); /** - * Attach to memory setments of primary process on Xen domain0. - * - * @param void - * - * @return + * Attach to memory setments of primary process on Xen domain0. + * + * @param void + * + * @return * 0: successfully * negative: error */