X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=lib%2Flibrte_pmd_ixgbe%2Fixgbe%2Fixgbe_x540.c;h=d3e1730c8b204887d325ce94b5f584b27eeb531a;hb=6441b9f65327386490d4a4f2e2a09458f6e070bc;hp=45de9e1daac9de91f60dd0f3f735d513c60ec1f7;hpb=2ec5fc4820bebd6343765acc893d3ea3aaf03c59;p=dpdk.git diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c index 45de9e1daa..d3e1730c8b 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c @@ -37,42 +37,16 @@ POSSIBILITY OF SUCH DAMAGE. #include "ixgbe_common.h" #include "ixgbe_phy.h" -s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw); -s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - bool *autoneg); -enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw); -s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, - ixgbe_link_speed speed, - bool autoneg, bool link_up_wait_to_complete); -s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw); -s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw); -u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw); - -s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw); -s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data); -s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, - u16 offset, u16 words, u16 *data); -s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data); -s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, - u16 offset, u16 words, u16 *data); -s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw); -s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, u16 *checksum_val); -u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw); - -s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); -void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask); - -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); -static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); -static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); -static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); +STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw); +STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); +STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); +STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); /** * ixgbe_init_ops_X540 - Inits func ptrs and MAC type * @hw: pointer to hardware structure * - * Initialize the function pointers and assign the MAC type for 82599. + * Initialize the function pointers and assign the MAC type for X540. * Does not touch the hardware. **/ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) @@ -107,7 +81,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2; mac->ops.get_media_type = &ixgbe_get_media_type_X540; mac->ops.get_supported_physical_layer = - &ixgbe_get_supported_physical_layer_X540; + &ixgbe_get_supported_physical_layer_X540; mac->ops.read_analog_reg8 = NULL; mac->ops.write_analog_reg8 = NULL; mac->ops.start_hw = &ixgbe_start_hw_X540; @@ -118,31 +92,37 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic; mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540; mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync_X540; + mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic; + mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic; /* RAR, Multicast, VLAN */ mac->ops.set_vmdq = &ixgbe_set_vmdq_generic; + mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic; mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic; mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic; mac->rar_highwater = 1; mac->ops.set_vfta = &ixgbe_set_vfta_generic; + mac->ops.set_vlvf = &ixgbe_set_vlvf_generic; mac->ops.clear_vfta = &ixgbe_clear_vfta_generic; mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic; mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing; mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing; /* Link */ - mac->ops.get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic; + mac->ops.get_link_capabilities = + &ixgbe_get_copper_link_capabilities_generic; mac->ops.setup_link = &ixgbe_setup_mac_link_X540; mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic; mac->ops.check_link = &ixgbe_check_mac_link_generic; - mac->mcft_size = 128; - mac->vft_size = 128; - mac->num_rar_entries = 128; - mac->rx_pb_size = 384; - mac->max_tx_queues = 128; - mac->max_rx_queues = 128; - mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); + + mac->mcft_size = 128; + mac->vft_size = 128; + mac->num_rar_entries = 128; + mac->rx_pb_size = 384; + mac->max_tx_queues = 128; + mac->max_rx_queues = 128; + mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); /* * FWSM register @@ -150,7 +130,7 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) * enabled. */ mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) & - IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE; + IXGBE_FWSM_MODE_MASK) ? true : false; hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; @@ -168,15 +148,15 @@ s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) * ixgbe_get_link_capabilities_X540 - Determines link capabilities * @hw: pointer to hardware structure * @speed: pointer to link speed - * @negotiation: TRUE when autoneg or autotry is enabled + * @autoneg: true when autoneg or autotry is enabled * * Determines the link capabilities by reading the AUTOC register. **/ s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, - ixgbe_link_speed *speed, - bool *negotiation) + ixgbe_link_speed *speed, + bool *autoneg) { - ixgbe_get_copper_link_capabilities_generic(hw, speed, negotiation); + ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); return IXGBE_SUCCESS; } @@ -189,7 +169,6 @@ s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, **/ enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) { - UNREFERENCED_1PARAMETER(hw); return ixgbe_media_type_copper; } @@ -197,16 +176,16 @@ enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities * @hw: pointer to hardware structure * @speed: new link speed - * @autoneg: TRUE if autonegotiation enabled - * @autoneg_wait_to_complete: TRUE when waiting for completion is needed + * @autoneg: true if autonegotiation enabled + * @autoneg_wait_to_complete: true when waiting for completion is needed **/ s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, - ixgbe_link_speed speed, bool autoneg, - bool autoneg_wait_to_complete) + ixgbe_link_speed speed, bool autoneg, + bool autoneg_wait_to_complete) { DEBUGFUNC("ixgbe_setup_mac_link_X540"); return hw->phy.ops.setup_link_speed(hw, speed, autoneg, - autoneg_wait_to_complete); + autoneg_wait_to_complete); } /** @@ -281,7 +260,10 @@ mac_reset_top: /* Add the SAN MAC address to the RAR only if it's a valid address */ if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1, - hw->mac.san_addr, 0, IXGBE_RAH_AV); + hw->mac.san_addr, 0, IXGBE_RAH_AV); + + /* Save the SAN MAC RAR index */ + hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; /* Reserve the last RAR for the SAN MAC address */ hw->mac.num_rar_entries--; @@ -289,7 +271,7 @@ mac_reset_top: /* Store the alternative WWNN/WWPN prefix */ hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, - &hw->mac.wwpn_prefix); + &hw->mac.wwpn_prefix); reset_hw_out: return status; @@ -365,12 +347,12 @@ s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) eec = IXGBE_READ_REG(hw, IXGBE_EEC); eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> - IXGBE_EEC_SIZE_SHIFT); + IXGBE_EEC_SIZE_SHIFT); eeprom->word_size = 1 << (eeprom_size + - IXGBE_EEPROM_WORD_SIZE_SHIFT); + IXGBE_EEPROM_WORD_SIZE_SHIFT); DEBUGOUT2("Eeprom params: type = %d, size = %d\n", - eeprom->type, eeprom->word_size); + eeprom->type, eeprom->word_size); } return IXGBE_SUCCESS; @@ -409,7 +391,7 @@ s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) * Reads a 16 bit word(s) from the EEPROM using the EERD register. **/ s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, - u16 offset, u16 words, u16 *data) + u16 offset, u16 words, u16 *data) { s32 status = IXGBE_SUCCESS; @@ -417,7 +399,7 @@ s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == IXGBE_SUCCESS) status = ixgbe_read_eerd_buffer_generic(hw, offset, - words, data); + words, data); else status = IXGBE_ERR_SWFW_SYNC; @@ -458,7 +440,7 @@ s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) * Write a 16 bit word(s) to the EEPROM using the EEWR register. **/ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, - u16 offset, u16 words, u16 *data) + u16 offset, u16 words, u16 *data) { s32 status = IXGBE_SUCCESS; @@ -466,7 +448,7 @@ s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == IXGBE_SUCCESS) status = ixgbe_write_eewr_buffer_generic(hw, offset, - words, data); + words, data); else status = IXGBE_ERR_SWFW_SYNC; @@ -526,7 +508,7 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) pointer >= hw->eeprom.word_size) continue; - if (ixgbe_read_eerd_generic(hw, pointer, &length)!= + if (ixgbe_read_eerd_generic(hw, pointer, &length) != IXGBE_SUCCESS) { DEBUGOUT("EEPROM read failed\n"); break; @@ -561,7 +543,7 @@ u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) * caller does not need checksum_val, the value can be NULL. **/ s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, - u16 *checksum_val) + u16 *checksum_val) { s32 status; u16 checksum; @@ -590,7 +572,7 @@ s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, * the synchronization semaphores twice here. */ ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, - &read_checksum); + &read_checksum); /* * Verify read checksum from EEPROM is the same as @@ -645,7 +627,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) * take the synchronization semaphores twice here. */ status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, - checksum); + checksum); if (status == IXGBE_SUCCESS) status = ixgbe_update_flash_X540(hw); @@ -665,7 +647,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy * EEPROM from shadow RAM to the flash device. **/ -static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) +STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) { u32 flup; s32 status = IXGBE_ERR_EEPROM; @@ -712,7 +694,7 @@ out: * Polls the FLUDONE (bit 26) of the EEC Register to determine when the * flash update is done. **/ -static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) +STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) { u32 i; u32 reg; @@ -777,9 +759,9 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) goto out; } else { /* - * Firmware currently using resource (fwmask), hardware currently - * using resource (hwmask), or other software thread currently - * using resource (swmask) + * Firmware currently using resource (fwmask), hardware + * currently using resource (hwmask), or other software + * thread currently using resource (swmask) */ ixgbe_release_swfw_sync_semaphore(hw); msec_delay(5); @@ -798,7 +780,7 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) * bits in the SW_FW_SYNC register. */ swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC); - if (swfw_sync & (fwmask| hwmask)) { + if (swfw_sync & (fwmask | hwmask)) { if (ixgbe_get_swfw_sync_semaphore(hw)) { ret_val = IXGBE_ERR_SWFW_SYNC; goto out; @@ -819,7 +801,7 @@ out: * @hw: pointer to hardware structure * @mask: Mask to specify which semaphore to release * - * Releases the SWFW semaphore throught the SW_FW_SYNC register + * Releases the SWFW semaphore through the SW_FW_SYNC register * for the specified function (CSR, PHY0, PHY1, EVM, Flash) **/ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) @@ -845,7 +827,7 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask) * * Sets the hardware semaphores so SW/FW can gain control of shared resources **/ -static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) +STATIC s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) { s32 status = IXGBE_ERR_EEPROM; u32 timeout = 2000; @@ -883,13 +865,14 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) * was not granted because we don't have access to the EEPROM */ if (i >= timeout) { - DEBUGOUT("REGSMP Software NVM semaphore not granted.\n"); + DEBUGOUT("REGSMP Software NVM semaphore not " + "granted.\n"); ixgbe_release_swfw_sync_semaphore(hw); status = IXGBE_ERR_EEPROM; } } else { DEBUGOUT("Software semaphore SMBI between device drivers " - "not granted.\n"); + "not granted.\n"); } return status; @@ -901,7 +884,7 @@ static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) * * This function clears hardware semaphore bits. **/ -static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) +STATIC void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) { u32 swsm; @@ -932,18 +915,22 @@ s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) { u32 macc_reg; u32 ledctl_reg; + ixgbe_link_speed speed; + bool link_up; DEBUGFUNC("ixgbe_blink_led_start_X540"); /* - * In order for the blink bit in the LED control register - * to work, link and speed must be forced in the MAC. We - * will reverse this when we stop the blinking. + * Link should be up in order for the blink bit in the LED control + * register to work. Force link and speed in the MAC if link is down. + * This will be reversed when we stop the blinking. */ - macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); - macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; - IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); - + hw->mac.ops.check_link(hw, &speed, &link_up, false); + if (link_up == false) { + macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); + macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; + IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); + } /* Set the LED to LINK_UP + BLINK. */ ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);