X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=lib%2Flibrte_pmd_ixgbe%2Fixgbe_fdir.c;h=afc53cb83d582fef1ff9a5380bdd6816fcc0c4f6;hb=585abe0bb1b8c994d6c72a5e189c99f8f07a6de3;hp=e682d14d9180d4fcc4473e8ab794ed0bb4ba5ec5;hpb=f9072f8b90bbbb0d0c698d2ecbc1e0e69739b5e6;p=dpdk.git

diff --git a/lib/librte_pmd_ixgbe/ixgbe_fdir.c b/lib/librte_pmd_ixgbe/ixgbe_fdir.c
index e682d14d91..afc53cb83d 100644
--- a/lib/librte_pmd_ixgbe/ixgbe_fdir.c
+++ b/lib/librte_pmd_ixgbe/ixgbe_fdir.c
@@ -62,9 +62,55 @@
 #define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
 #define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
 #define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
+#define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
+#define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
+#define IXGBE_MAX_FLX_SOURCE_OFF        62
+#define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
 #define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
 
+#define IXGBE_FDIR_FLOW_TYPES ( \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
+	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
+
+#define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
+	uint8_t ipv6_addr[16]; \
+	uint8_t i; \
+	rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
+	(ipv6m) = 0; \
+	for (i = 0; i < sizeof(ipv6_addr); i++) { \
+		if (ipv6_addr[i] == UINT8_MAX) \
+			(ipv6m) |= 1 << i; \
+		else if (ipv6_addr[i] != 0) { \
+			PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
+			return -EINVAL; \
+		} \
+	} \
+} while (0)
+
+#define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
+	uint8_t ipv6_addr[16]; \
+	uint8_t i; \
+	for (i = 0; i < sizeof(ipv6_addr); i++) { \
+		if ((ipv6m) & (1 << i)) \
+			ipv6_addr[i] = UINT8_MAX; \
+		else \
+			ipv6_addr[i] = 0; \
+	} \
+	rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
+} while (0)
+
 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
+static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,
+		const struct rte_eth_fdir_masks *input_mask);
+static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
+		const struct rte_eth_fdir_flex_conf *conf);
+static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
 static int ixgbe_fdir_filter_to_atr_input(
 		const struct rte_eth_fdir_filter *fdir_filter,
 		union ixgbe_atr_input *input);
@@ -84,6 +130,12 @@ static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
 			      const struct rte_eth_fdir_filter *fdir_filter,
 			      bool del,
 			      bool update);
+static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
+static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
+			struct rte_eth_fdir_info *fdir_info);
+static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
+			struct rte_eth_fdir_stats *fdir_stats);
+
 /**
  * This function is based on ixgbe_fdir_enable_82599() in ixgbe/ixgbe_82599.c.
  * It adds extra configuration of fdirctrl that is common for all filter types.
@@ -92,7 +144,8 @@ static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
  *  @hw: pointer to hardware structure
  *  @fdirctrl: value to write to flow director control register
  **/
-static void fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
+static int
+fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
 {
 	int i;
 
@@ -132,16 +185,20 @@ static void fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
 		msec_delay(1);
 	}
 
-	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
-		PMD_INIT_LOG(WARNING, "Flow Director poll time exceeded!");
+	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
+		PMD_INIT_LOG(ERR, "Flow Director poll time exceeded "
+			"during enabling!");
+		return -ETIMEDOUT;
+	}
+	return 0;
 }
 
 /*
  * Set appropriate bits in fdirctrl for: variable reporting levels, moving
  * flexbytes matching field, and drop queue (only for perfect matching mode).
  */
-static int
-configure_fdir_flags(struct rte_fdir_conf *conf, uint32_t *fdirctrl)
+static inline int
+configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
 {
 	*fdirctrl = 0;
 
@@ -183,55 +240,21 @@ configure_fdir_flags(struct rte_fdir_conf *conf, uint32_t *fdirctrl)
 		return -EINVAL;
 	};
 
-	*fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
+	*fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
+		     IXGBE_FDIRCTRL_FLEX_SHIFT;
 
 	if (conf->mode == RTE_FDIR_MODE_PERFECT) {
 		*fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
 		*fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
 	}
-
-	return 0;
-}
-
-int
-ixgbe_fdir_configure(struct rte_eth_dev *dev)
-{
-	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-	int err;
-	uint32_t fdirctrl, pbsize;
-	int i;
-
-	PMD_INIT_FUNC_TRACE();
-
-	if (hw->mac.type != ixgbe_mac_82599EB &&
-		hw->mac.type != ixgbe_mac_X540 &&
-		hw->mac.type != ixgbe_mac_X550 &&
-		hw->mac.type != ixgbe_mac_X550EM_x)
-		return -ENOSYS;
-
-	err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
-	if (err)
-		return err;
-
 	/*
-	 * Before enabling Flow Director, the Rx Packet Buffer size
-	 * must be reduced.  The new value is the current size minus
-	 * flow director memory usage size.
-	 */
-	pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
-	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
-	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
-
-	/*
-	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
-	 * intialized to zero for non DCB mode otherwise actual total RX PB
-	 * would be bigger than programmed and filter space would run into
-	 * the PB 0 region.
+	 * Continue setup of fdirctrl register bits:
+	 *  Set the maximum length per hash bucket to 0xA filters
+	 *  Send interrupt when 64 filters are left
 	 */
-	for (i = 1; i < 8; i++)
-		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
+	*fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
+		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 
-	fdir_enable_82599(hw, fdirctrl);
 	return 0;
 }
 
@@ -242,14 +265,14 @@ ixgbe_fdir_configure(struct rte_eth_dev *dev)
  *  @lo_dword: Bits 15:0  mask to be bit swapped.
  *
  *  Flow director uses several registers to store 2 x 16 bit masks with the
- *  bits reversed such as FDIRTCPM, FDIRUDPM and FDIRIP6M. The LS bit of the
+ *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
  *  mask affects the MS bit/byte of the target. This function reverses the
  *  bits in these masks.
  *  **/
-static uint32_t
+static inline uint32_t
 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
 {
-	u32 mask = hi_dword << 16;
+	uint32_t mask = hi_dword << 16;
 	mask |= lo_dword;
 	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
 	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
@@ -257,24 +280,26 @@ reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
 	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
 }
 
-/*
- * This macro exists in ixgbe/ixgbe_82599.c, however in that file it reverses
- * the bytes, and then reverses them again. So here it does nothing.
- */
-#define IXGBE_WRITE_REG_BE32 IXGBE_WRITE_REG
-
 /*
  * This is based on ixgbe_fdir_set_input_mask_82599() in ixgbe/ixgbe_82599.c,
  * but makes use of the rte_fdir_masks structure to see which bits to set.
  */
 static int
-fdir_set_input_mask_82599(struct ixgbe_hw *hw,
-		struct rte_fdir_masks *input_mask)
+fdir_set_input_mask_82599(struct rte_eth_dev *dev,
+		const struct rte_eth_fdir_masks *input_mask)
 {
-	/* mask VM pool since it is currently not supported */
-	u32 fdirm = IXGBE_FDIRM_POOL;
-	u32 fdirtcpm;  /* TCP source and destination port masks. */
-	u32 fdiripv6m; /* IPv6 source and destination masks. */
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct ixgbe_hw_fdir_info *info =
+			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
+	/*
+	 * mask VM pool and DIPv6 since there are currently not supported
+	 * mask FLEX byte, it will be set in flex_conf
+	 */
+	uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
+	uint32_t fdirtcpm;  /* TCP source and destination port masks. */
+	uint32_t fdiripv6m; /* IPv6 source and destination masks. */
+	uint16_t dst_ipv6m = 0;
+	uint16_t src_ipv6m = 0;
 
 	PMD_INIT_FUNC_TRACE();
 
@@ -284,30 +309,24 @@ fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 	 * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 	 * cannot be masked out in this implementation.
 	 */
-	if (input_mask->only_ip_flow) {
+	if (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)
 		/* use the L4 protocol mask for raw IPv4/IPv6 traffic */
 		fdirm |= IXGBE_FDIRM_L4P;
-		if (input_mask->dst_port_mask || input_mask->src_port_mask) {
-			PMD_INIT_LOG(ERR, " Error on src/dst port mask");
-			return -EINVAL;
-		}
-	}
-
-	if (!input_mask->comp_ipv6_dst)
-		/* mask DIPV6 */
-		fdirm |= IXGBE_FDIRM_DIPv6;
 
-	if (!input_mask->vlan_id)
-		/* mask VLAN ID*/
-		fdirm |= IXGBE_FDIRM_VLANID;
-
-	if (!input_mask->vlan_prio)
-		/* mask VLAN priority */
+	if (input_mask->vlan_tci_mask == 0x0FFF)
+		/* mask VLAN Priority */
 		fdirm |= IXGBE_FDIRM_VLANP;
-
-	if (!input_mask->flexbytes)
-		/* Mask Flex Bytes */
-		fdirm |= IXGBE_FDIRM_FLEX;
+	else if (input_mask->vlan_tci_mask == 0xE000)
+		/* mask VLAN ID */
+		fdirm |= IXGBE_FDIRM_VLANID;
+	else if (input_mask->vlan_tci_mask == 0)
+		/* mask VLAN ID and Priority */
+		fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
+	else if (input_mask->vlan_tci_mask != 0xEFFF) {
+		PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
+		return -EINVAL;
+	}
+	info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 
@@ -318,47 +337,156 @@ fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 	/* write both the same so that UDP and TCP use the same mask */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
-
-	if (!input_mask->set_ipv6_mask) {
-		/* Store source and destination IPv4 masks (big-endian) */
-		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
-				IXGBE_NTOHL(~input_mask->src_ipv4_mask));
-		IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
-				IXGBE_NTOHL(~input_mask->dst_ipv4_mask));
-	} else {
-		/* Store source and destination IPv6 masks (bit reversed) */
-		fdiripv6m = reverse_fdir_bitmasks(input_mask->dst_ipv6_mask,
-						  input_mask->src_ipv6_mask);
+	info->mask.src_port_mask = input_mask->src_port_mask;
+	info->mask.dst_port_mask = input_mask->dst_port_mask;
+
+	/* Store source and destination IPv4 masks (big-endian) */
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, ~(input_mask->ipv4_mask.src_ip));
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, ~(input_mask->ipv4_mask.dst_ip));
+	info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
+	info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
+
+	if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
+		/*
+		 * IPv6 mask is only meaningful in signature mode
+		 * Store source and destination IPv6 masks (bit reversed)
+		 */
+		IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
+		IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
+		fdiripv6m = (dst_ipv6m << 16) | src_ipv6m;
 
 		IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
+		info->mask.src_ipv6_mask = src_ipv6m;
+		info->mask.dst_ipv6_mask = dst_ipv6m;
 	}
 
 	return IXGBE_SUCCESS;
 }
 
+/*
+ * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
+ * arguments are valid
+ */
+static int
+ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
+		const struct rte_eth_fdir_flex_conf *conf)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct ixgbe_hw_fdir_info *info =
+			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
+	const struct rte_eth_flex_payload_cfg *flex_cfg;
+	const struct rte_eth_fdir_flex_mask *flex_mask;
+	uint32_t fdirctrl, fdirm;
+	uint16_t flexbytes = 0;
+	uint16_t i;
+
+	fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
+	fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
+
+	if (conf == NULL) {
+		PMD_DRV_LOG(INFO, "NULL pointer.");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < conf->nb_payloads; i++) {
+		flex_cfg = &conf->flex_set[i];
+		if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
+			PMD_DRV_LOG(ERR, "unsupported payload type.");
+			return -EINVAL;
+		}
+		if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
+		    (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
+		    (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
+			fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
+			fdirctrl |= (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
+					IXGBE_FDIRCTRL_FLEX_SHIFT;
+		} else {
+			PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
+			return -EINVAL;
+		}
+	}
+
+	for (i = 0; i < conf->nb_flexmasks; i++) {
+		flex_mask = &conf->flex_mask[i];
+		if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
+			PMD_DRV_LOG(ERR, "flexmask should be set globally.");
+			return -EINVAL;
+		}
+		flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
+					((flex_mask->mask[1]) & 0xFF));
+		if (flexbytes == UINT16_MAX)
+			fdirm &= ~IXGBE_FDIRM_FLEX;
+		else if (flexbytes != 0) {
+			/* IXGBE_FDIRM_FLEX is set by default when set mask */
+			PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
+			return -EINVAL;
+		}
+	}
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
+	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
+	info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
+	info->flex_bytes_offset = (uint8_t)((fdirctrl &
+					    IXGBE_FDIRCTRL_FLEX_MASK) >>
+					    IXGBE_FDIRCTRL_FLEX_SHIFT);
+	return 0;
+}
+
 int
-ixgbe_fdir_set_masks(struct rte_eth_dev *dev, struct rte_fdir_masks *fdir_masks)
+ixgbe_fdir_configure(struct rte_eth_dev *dev)
 {
-	struct ixgbe_hw *hw;
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	int err;
+	uint32_t fdirctrl, pbsize;
+	int i;
 
 	PMD_INIT_FUNC_TRACE();
 
-	hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
-
 	if (hw->mac.type != ixgbe_mac_82599EB &&
 		hw->mac.type != ixgbe_mac_X540 &&
 		hw->mac.type != ixgbe_mac_X550 &&
 		hw->mac.type != ixgbe_mac_X550EM_x)
 		return -ENOSYS;
 
-	err = ixgbe_reinit_fdir_tables_82599(hw);
-	if (err) {
-		PMD_INIT_LOG(ERR, "reinit of fdir tables failed");
-		return -EIO;
+	err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
+	if (err)
+		return err;
+
+	/*
+	 * Before enabling Flow Director, the Rx Packet Buffer size
+	 * must be reduced.  The new value is the current size minus
+	 * flow director memory usage size.
+	 */
+	pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
+	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
+	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
+
+	/*
+	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
+	 * intialized to zero for non DCB mode otherwise actual total RX PB
+	 * would be bigger than programmed and filter space would run into
+	 * the PB 0 region.
+	 */
+	for (i = 1; i < 8; i++)
+		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
+
+	err = fdir_set_input_mask_82599(dev, &dev->data->dev_conf.fdir_conf.mask);
+	if (err < 0) {
+		PMD_INIT_LOG(ERR, " Error on setting FD mask");
+		return err;
+	}
+	err = ixgbe_set_fdir_flex_conf(dev,
+		&dev->data->dev_conf.fdir_conf.flex_conf);
+	if (err < 0) {
+		PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
+		return err;
 	}
 
-	return fdir_set_input_mask_82599(hw, fdir_masks);
+	err = fdir_enable_82599(hw, fdirctrl);
+	if (err < 0) {
+		PMD_INIT_LOG(ERR, " Error on enabling FD.");
+		return err;
+	}
+	return 0;
 }
 
 /*
@@ -375,28 +503,28 @@ ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
 		(fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
 
 	switch (fdir_filter->input.flow_type) {
-	case RTE_ETH_FLOW_TYPE_UDPV4:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
 		break;
-	case RTE_ETH_FLOW_TYPE_TCPV4:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
 		break;
-	case RTE_ETH_FLOW_TYPE_SCTPV4:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
 		break;
-	case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
 		break;
-	case RTE_ETH_FLOW_TYPE_UDPV6:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
 		break;
-	case RTE_ETH_FLOW_TYPE_TCPV6:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
 		break;
-	case RTE_ETH_FLOW_TYPE_SCTPV6:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
 		break;
-	case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
 		break;
 	default:
@@ -405,30 +533,30 @@ ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
 	}
 
 	switch (fdir_filter->input.flow_type) {
-	case RTE_ETH_FLOW_TYPE_UDPV4:
-	case RTE_ETH_FLOW_TYPE_TCPV4:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 		input->formatted.src_port =
 			fdir_filter->input.flow.udp4_flow.src_port;
 		input->formatted.dst_port =
 			fdir_filter->input.flow.udp4_flow.dst_port;
 	/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
-	case RTE_ETH_FLOW_TYPE_SCTPV4:
-	case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
+	case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 		input->formatted.src_ip[0] =
 			fdir_filter->input.flow.ip4_flow.src_ip;
 		input->formatted.dst_ip[0] =
 			fdir_filter->input.flow.ip4_flow.dst_ip;
 		break;
 
-	case RTE_ETH_FLOW_TYPE_UDPV6:
-	case RTE_ETH_FLOW_TYPE_TCPV6:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 		input->formatted.src_port =
 			fdir_filter->input.flow.udp6_flow.src_port;
 		input->formatted.dst_port =
 			fdir_filter->input.flow.udp6_flow.dst_port;
 	/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
-	case RTE_ETH_FLOW_TYPE_SCTPV6:
-	case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
+	case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 		rte_memcpy(input->formatted.src_ip,
 			   fdir_filter->input.flow.ipv6_flow.src_ip,
 			   sizeof(input->formatted.src_ip));
@@ -837,19 +965,83 @@ ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
 	return err;
 }
 
-void
-ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
+static int
+ixgbe_fdir_flush(struct rte_eth_dev *dev)
 {
 	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	struct ixgbe_hw_fdir_info *info =
 			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
-	uint32_t reg;
+	int ret;
 
-	if (hw->mac.type != ixgbe_mac_82599EB &&
-		hw->mac.type != ixgbe_mac_X540 &&
-		hw->mac.type != ixgbe_mac_X550 &&
-		hw->mac.type != ixgbe_mac_X550EM_x)
-		return;
+	ret = ixgbe_reinit_fdir_tables_82599(hw);
+	if (ret < 0) {
+		PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
+		return ret;
+	}
+
+	info->f_add = 0;
+	info->f_remove = 0;
+	info->add = 0;
+	info->remove = 0;
+
+	return ret;
+}
+
+#define FDIRENTRIES_NUM_SHIFT 10
+static void
+ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct ixgbe_hw_fdir_info *info =
+			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
+	uint32_t fdirctrl, max_num;
+	uint8_t offset;
+
+	fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
+	offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
+			IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
+
+	fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
+	max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
+			(fdirctrl & FDIRCTRL_PBALLOC_MASK)));
+	if (fdir_info->mode == RTE_FDIR_MODE_PERFECT)
+		fdir_info->guarant_spc = max_num;
+	else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
+		fdir_info->guarant_spc = max_num * 4;
+
+	fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
+	fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
+	fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
+	IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
+			fdir_info->mask.ipv6_mask.src_ip);
+	IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
+			fdir_info->mask.ipv6_mask.dst_ip);
+	fdir_info->mask.src_port_mask = info->mask.src_port_mask;
+	fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
+	fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
+	fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
+	fdir_info->flex_payload_unit = sizeof(uint16_t);
+	fdir_info->max_flex_payload_segment_num = 1;
+	fdir_info->flex_payload_limit = 62;
+	fdir_info->flex_conf.nb_payloads = 1;
+	fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
+	fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
+	fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
+	fdir_info->flex_conf.nb_flexmasks = 1;
+	fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
+	fdir_info->flex_conf.flex_mask[0].mask[0] =
+			(uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
+	fdir_info->flex_conf.flex_mask[0].mask[1] =
+			(uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
+}
+
+static void
+ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
+{
+	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
+	struct ixgbe_hw_fdir_info *info =
+			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
+	uint32_t reg, max_num;
 
 	/* Get the information from registers */
 	reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
@@ -877,14 +1069,23 @@ ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir *fdir)
 		IXGBE_FDIRFSTAT_FADD_SHIFT;
 
 	/*  Copy the new information in the fdir parameter */
-	fdir->collision = info->collision;
-	fdir->free = info->free;
-	fdir->maxhash = info->maxhash;
-	fdir->maxlen = info->maxlen;
-	fdir->remove = info->remove;
-	fdir->add = info->add;
-	fdir->f_remove = info->f_remove;
-	fdir->f_add = info->f_add;
+	fdir_stats->collision = info->collision;
+	fdir_stats->free = info->free;
+	fdir_stats->maxhash = info->maxhash;
+	fdir_stats->maxlen = info->maxlen;
+	fdir_stats->remove = info->remove;
+	fdir_stats->add = info->add;
+	fdir_stats->f_remove = info->f_remove;
+	fdir_stats->f_add = info->f_add;
+
+	reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
+	max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
+			(reg & FDIRCTRL_PBALLOC_MASK)));
+	if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
+			fdir_stats->guarant_cnt = max_num - fdir_stats->free;
+	else if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE)
+		fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
+
 }
 
 /*
@@ -925,6 +1126,15 @@ ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
 		ret = ixgbe_add_del_fdir_filter(dev,
 			(struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
 		break;
+	case RTE_ETH_FILTER_FLUSH:
+		ret = ixgbe_fdir_flush(dev);
+		break;
+	case RTE_ETH_FILTER_INFO:
+		ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
+		break;
+	case RTE_ETH_FILTER_STATS:
+		ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
+		break;
 	default:
 		PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
 		ret = -EINVAL;