X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;ds=sidebyside;f=lib%2Flibrte_pmd_ixgbe%2Fixgbe_rxtx.c;h=3059375c0d3e206bb5e918a75f92251f1bc55581;hb=6eb85c0e443fada3a74a7a45559cfeac6befcc6c;hp=e10d6a214a395bdb3f6a44cd98e8938bbe235b2e;hpb=a775949fbb09a142b630a97b6fbe5f9055f27847;p=dpdk.git diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c index e10d6a214a..3059375c0d 100644 --- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c +++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c @@ -80,17 +80,6 @@ #include "ixgbe/ixgbe_common.h" #include "ixgbe_rxtx.h" -#define IXGBE_RSS_OFFLOAD_ALL ( \ - ETH_RSS_IPV4 | \ - ETH_RSS_IPV4_TCP | \ - ETH_RSS_IPV6 | \ - ETH_RSS_IPV6_EX | \ - ETH_RSS_IPV6_TCP | \ - ETH_RSS_IPV6_TCP_EX | \ - ETH_RSS_IPV4_UDP | \ - ETH_RSS_IPV6_UDP | \ - ETH_RSS_IPV6_UDP_EX) - /* Bit Mask to indicate what bits required for building TX context */ #define IXGBE_TX_OFFLOAD_MASK ( \ PKT_TX_VLAN_PKT | \ @@ -2432,19 +2421,19 @@ ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf) mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */ if (rss_hf & ETH_RSS_IPV4) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4; - if (rss_hf & ETH_RSS_IPV4_TCP) + if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP; if (rss_hf & ETH_RSS_IPV6) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6; if (rss_hf & ETH_RSS_IPV6_EX) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX; - if (rss_hf & ETH_RSS_IPV6_TCP) + if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP; if (rss_hf & ETH_RSS_IPV6_TCP_EX) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP; - if (rss_hf & ETH_RSS_IPV4_UDP) + if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; - if (rss_hf & ETH_RSS_IPV6_UDP) + if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; if (rss_hf & ETH_RSS_IPV6_UDP_EX) mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP; @@ -2518,19 +2507,19 @@ ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4) rss_hf |= ETH_RSS_IPV4; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP) - rss_hf |= ETH_RSS_IPV4_TCP; + rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6) rss_hf |= ETH_RSS_IPV6; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX) rss_hf |= ETH_RSS_IPV6_EX; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP) - rss_hf |= ETH_RSS_IPV6_TCP; + rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP) rss_hf |= ETH_RSS_IPV6_TCP_EX; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP) - rss_hf |= ETH_RSS_IPV4_UDP; + rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP) - rss_hf |= ETH_RSS_IPV6_UDP; + rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP) rss_hf |= ETH_RSS_IPV6_UDP_EX; rss_conf->rss_hf = rss_hf; @@ -3339,6 +3328,67 @@ ixgbe_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq) return 0; } +static int +ixgbe_config_vf_rss(struct rte_eth_dev *dev) +{ + struct ixgbe_hw *hw; + uint32_t mrqc; + + ixgbe_rss_configure(dev); + + hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + /* MRQC: enable VF RSS */ + mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC); + mrqc &= ~IXGBE_MRQC_MRQE_MASK; + switch (RTE_ETH_DEV_SRIOV(dev).active) { + case ETH_64_POOLS: + mrqc |= IXGBE_MRQC_VMDQRSS64EN; + break; + + case ETH_32_POOLS: + mrqc |= IXGBE_MRQC_VMDQRSS32EN; + break; + + default: + PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS"); + return -EINVAL; + } + + IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); + + return 0; +} + +static int +ixgbe_config_vf_default(struct rte_eth_dev *dev) +{ + struct ixgbe_hw *hw = + IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + + switch (RTE_ETH_DEV_SRIOV(dev).active) { + case ETH_64_POOLS: + IXGBE_WRITE_REG(hw, IXGBE_MRQC, + IXGBE_MRQC_VMDQEN); + break; + + case ETH_32_POOLS: + IXGBE_WRITE_REG(hw, IXGBE_MRQC, + IXGBE_MRQC_VMDQRT4TCEN); + break; + + case ETH_16_POOLS: + IXGBE_WRITE_REG(hw, IXGBE_MRQC, + IXGBE_MRQC_VMDQRT8TCEN); + break; + default: + PMD_INIT_LOG(ERR, + "invalid pool number in IOV mode"); + break; + } + return 0; +} + static int ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev) { @@ -3371,24 +3421,25 @@ ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev) default: ixgbe_rss_disable(dev); } } else { - switch (RTE_ETH_DEV_SRIOV(dev).active) { /* * SRIOV active scheme - * FIXME if support DCB/RSS together with VMDq & SRIOV + * Support RSS together with VMDq & SRIOV */ - case ETH_64_POOLS: - IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQEN); - break; - - case ETH_32_POOLS: - IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT4TCEN); + switch (dev->data->dev_conf.rxmode.mq_mode) { + case ETH_MQ_RX_RSS: + case ETH_MQ_RX_VMDQ_RSS: + ixgbe_config_vf_rss(dev); break; - case ETH_16_POOLS: - IXGBE_WRITE_REG(hw, IXGBE_MRQC, IXGBE_MRQC_VMDQRT8TCEN); - break; + /* FIXME if support DCB/RSS together with VMDq & SRIOV */ + case ETH_MQ_RX_VMDQ_DCB: + case ETH_MQ_RX_VMDQ_DCB_RSS: + PMD_INIT_LOG(ERR, + "Could not support DCB with VMDq & SRIOV"); + return -1; default: - PMD_INIT_LOG(ERR, "invalid pool number in IOV mode"); + ixgbe_config_vf_default(dev); + break; } } @@ -3561,9 +3612,9 @@ ixgbe_dev_rx_init(struct rte_eth_dev *dev) IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype); } srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size << - IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & - IXGBE_SRRCTL_BSIZEHDR_MASK); - srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; + IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & + IXGBE_SRRCTL_BSIZEHDR_MASK); + srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; } else #endif srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; @@ -3744,7 +3795,7 @@ ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw) /* * Start Transmit and Receive Units. */ -void +int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev) { struct ixgbe_hw *hw; @@ -3754,6 +3805,7 @@ ixgbe_dev_rxtx_start(struct rte_eth_dev *dev) uint32_t dmatxctl; uint32_t rxctrl; uint16_t i; + int ret = 0; PMD_INIT_FUNC_TRACE(); hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); @@ -3776,14 +3828,20 @@ ixgbe_dev_rxtx_start(struct rte_eth_dev *dev) for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; - if (!txq->tx_deferred_start) - ixgbe_dev_tx_queue_start(dev, i); + if (!txq->tx_deferred_start) { + ret = ixgbe_dev_tx_queue_start(dev, i); + if (ret < 0) + return ret; + } } for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; - if (!rxq->rx_deferred_start) - ixgbe_dev_rx_queue_start(dev, i); + if (!rxq->rx_deferred_start) { + ret = ixgbe_dev_rx_queue_start(dev, i); + if (ret < 0) + return ret; + } } /* Enable Receive engine */ @@ -3798,6 +3856,7 @@ ixgbe_dev_rxtx_start(struct rte_eth_dev *dev) dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX) ixgbe_setup_loopback_link_82599(hw); + return 0; } /* @@ -3998,7 +4057,7 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) struct igb_rx_queue *rxq; struct rte_pktmbuf_pool_private *mbp_priv; uint64_t bus_addr; - uint32_t srrctl; + uint32_t srrctl, psrtype = 0; uint16_t buf_size; uint16_t i; int ret; @@ -4006,6 +4065,19 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) PMD_INIT_FUNC_TRACE(); hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); + if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) { + PMD_INIT_LOG(ERR, "The number of Rx queue invalid, " + "it should be power of 2"); + return -1; + } + + if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) { + PMD_INIT_LOG(ERR, "The number of Rx queue invalid, " + "it should be equal to or less than %d", + hw->mac.max_rx_queues); + return -1; + } + /* * When the VF driver issues a IXGBE_VF_RESET request, the PF driver * disables the VF receipt of packets if the PF MTU is > 1500. @@ -4052,20 +4124,10 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) * Configure Header Split */ if (dev->data->dev_conf.rxmode.header_split) { - - /* Must setup the PSRTYPE register */ - uint32_t psrtype; - psrtype = IXGBE_PSRTYPE_TCPHDR | - IXGBE_PSRTYPE_UDPHDR | - IXGBE_PSRTYPE_IPV4HDR | - IXGBE_PSRTYPE_IPV6HDR; - - IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE(i), psrtype); - srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size << - IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & - IXGBE_SRRCTL_BSIZEHDR_MASK); - srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; + IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & + IXGBE_SRRCTL_BSIZEHDR_MASK); + srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; } else #endif srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; @@ -4108,6 +4170,20 @@ ixgbevf_dev_rx_init(struct rte_eth_dev *dev) } } +#ifdef RTE_HEADER_SPLIT_ENABLE + if (dev->data->dev_conf.rxmode.header_split) + /* Must setup the PSRTYPE register */ + psrtype = IXGBE_PSRTYPE_TCPHDR | + IXGBE_PSRTYPE_UDPHDR | + IXGBE_PSRTYPE_IPV4HDR | + IXGBE_PSRTYPE_IPV6HDR; +#endif + + /* Set RQPL for VF RSS according to max Rx queue */ + psrtype |= (dev->data->nb_rx_queues >> 1) << + IXGBE_PSRTYPE_RQPL_SHIFT; + IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype); + if (dev->data->dev_conf.rxmode.enable_scatter) { if (!dev->data->scattered_rx) PMD_INIT_LOG(DEBUG, "forcing scatter mode");