X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=app%2Ftest%2Ftest_timer.c;h=a10b2fe9daf4c8e898c068c0b2176b8712e8c82c;hb=5fc2e5c27d69bcebb352d17603a1d3ca2628f17b;hp=2f6525a50622917fa5986eb86f32f49109146876;hpb=26e09db6cb5fd9bbf0feb928561af9932694574b;p=dpdk.git diff --git a/app/test/test_timer.c b/app/test/test_timer.c index 2f6525a506..a10b2fe9da 100644 --- a/app/test/test_timer.c +++ b/app/test/test_timer.c @@ -1,34 +1,5 @@ -/*- - * BSD LICENSE - * - * Copyright(c) 2010-2014 Intel Corporation. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Intel Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2010-2014 Intel Corporation */ #include "test.h" @@ -66,7 +37,7 @@ * - All cores then simultaneously are set to schedule all the timers at * the same time, so conflicts should occur. * - Then there is a delay while we wait for the timers to expire - * - Then the master lcore calls timer_manage() and we check that all + * - Then the main lcore calls timer_manage() and we check that all * timers have had their callbacks called exactly once - no more no less. * - Then we repeat the process, except after setting up the timers, we have * all cores randomly reschedule them. @@ -87,7 +58,7 @@ * * - timer0 * - * - At initialization, timer0 is loaded by the master core, on master core + * - At initialization, timer0 is loaded by the main core, on main core * in "single" mode (time = 1 second). * - In the first 19 callbacks, timer0 is reloaded on the same core, * then, it is explicitly stopped at the 20th call. @@ -95,21 +66,21 @@ * * - timer1 * - * - At initialization, timer1 is loaded by the master core, on the - * master core in "single" mode (time = 2 seconds). + * - At initialization, timer1 is loaded by the main core, on the + * main core in "single" mode (time = 2 seconds). * - In the first 9 callbacks, timer1 is reloaded on another * core. After the 10th callback, timer1 is not reloaded anymore. * * - timer2 * - * - At initialization, timer2 is loaded by the master core, on the - * master core in "periodical" mode (time = 1 second). + * - At initialization, timer2 is loaded by the main core, on the + * main core in "periodical" mode (time = 1 second). * - In the callback, when t=25s, it stops timer3 and reloads timer0 * on the current core. * * - timer3 * - * - At initialization, timer3 is loaded by the master core, on + * - At initialization, timer3 is loaded by the main core, on * another core in "periodical" mode (time = 1 second). * - It is stopped at t=25s by timer2. */ @@ -126,7 +97,6 @@ #include #include #include -#include #include #include #include @@ -136,6 +106,7 @@ #include #include #include +#include #define TEST_DURATION_S 1 /* in seconds */ #define NB_TIMER 4 @@ -166,8 +137,8 @@ mytimer_reset(struct mytimerinfo *timinfo, uint64_t ticks, /* timer callback for stress tests */ static void -timer_stress_cb(__attribute__((unused)) struct rte_timer *tim, - __attribute__((unused)) void *arg) +timer_stress_cb(__rte_unused struct rte_timer *tim, + __rte_unused void *arg) { long r; unsigned lcore_id = rte_lcore_id(); @@ -192,7 +163,7 @@ timer_stress_cb(__attribute__((unused)) struct rte_timer *tim, } static int -timer_stress_main_loop(__attribute__((unused)) void *arg) +timer_stress_main_loop(__rte_unused void *arg) { uint64_t hz = rte_get_timer_hz(); unsigned lcore_id = rte_lcore_id(); @@ -230,68 +201,69 @@ timer_stress_main_loop(__attribute__((unused)) void *arg) return 0; } -/* Need to synchronize slave lcores through multiple steps. */ -enum { SLAVE_WAITING = 1, SLAVE_RUN_SIGNAL, SLAVE_RUNNING, SLAVE_FINISHED }; -static rte_atomic16_t slave_state[RTE_MAX_LCORE]; +/* Need to synchronize worker lcores through multiple steps. */ +enum { WORKER_WAITING = 1, WORKER_RUN_SIGNAL, WORKER_RUNNING, WORKER_FINISHED }; +static rte_atomic16_t lcore_state[RTE_MAX_LCORE]; static void -master_init_slaves(void) +main_init_workers(void) { unsigned i; - RTE_LCORE_FOREACH_SLAVE(i) { - rte_atomic16_set(&slave_state[i], SLAVE_WAITING); + RTE_LCORE_FOREACH_WORKER(i) { + rte_atomic16_set(&lcore_state[i], WORKER_WAITING); } } static void -master_start_slaves(void) +main_start_workers(void) { unsigned i; - RTE_LCORE_FOREACH_SLAVE(i) { - rte_atomic16_set(&slave_state[i], SLAVE_RUN_SIGNAL); + RTE_LCORE_FOREACH_WORKER(i) { + rte_atomic16_set(&lcore_state[i], WORKER_RUN_SIGNAL); } - RTE_LCORE_FOREACH_SLAVE(i) { - while (rte_atomic16_read(&slave_state[i]) != SLAVE_RUNNING) + RTE_LCORE_FOREACH_WORKER(i) { + while (rte_atomic16_read(&lcore_state[i]) != WORKER_RUNNING) rte_pause(); } } static void -master_wait_for_slaves(void) +main_wait_for_workers(void) { unsigned i; - RTE_LCORE_FOREACH_SLAVE(i) { - while (rte_atomic16_read(&slave_state[i]) != SLAVE_FINISHED) + RTE_LCORE_FOREACH_WORKER(i) { + while (rte_atomic16_read(&lcore_state[i]) != WORKER_FINISHED) rte_pause(); } } static void -slave_wait_to_start(void) +worker_wait_to_start(void) { unsigned lcore_id = rte_lcore_id(); - while (rte_atomic16_read(&slave_state[lcore_id]) != SLAVE_RUN_SIGNAL) + while (rte_atomic16_read(&lcore_state[lcore_id]) != WORKER_RUN_SIGNAL) rte_pause(); - rte_atomic16_set(&slave_state[lcore_id], SLAVE_RUNNING); + rte_atomic16_set(&lcore_state[lcore_id], WORKER_RUNNING); } static void -slave_finish(void) +worker_finish(void) { unsigned lcore_id = rte_lcore_id(); - rte_atomic16_set(&slave_state[lcore_id], SLAVE_FINISHED); + rte_atomic16_set(&lcore_state[lcore_id], WORKER_FINISHED); } static volatile int cb_count = 0; /* callback for second stress test. will only be called - * on master lcore */ + * on main lcore + */ static void timer_stress2_cb(struct rte_timer *tim __rte_unused, void *arg __rte_unused) { @@ -301,41 +273,41 @@ timer_stress2_cb(struct rte_timer *tim __rte_unused, void *arg __rte_unused) #define NB_STRESS2_TIMERS 8192 static int -timer_stress2_main_loop(__attribute__((unused)) void *arg) +timer_stress2_main_loop(__rte_unused void *arg) { static struct rte_timer *timers; int i, ret; uint64_t delay = rte_get_timer_hz() / 20; - unsigned lcore_id = rte_lcore_id(); - unsigned master = rte_get_master_lcore(); + unsigned int lcore_id = rte_lcore_id(); + unsigned int main_lcore = rte_get_main_lcore(); int32_t my_collisions = 0; static rte_atomic32_t collisions; - if (lcore_id == master) { + if (lcore_id == main_lcore) { cb_count = 0; test_failed = 0; rte_atomic32_set(&collisions, 0); - master_init_slaves(); + main_init_workers(); timers = rte_malloc(NULL, sizeof(*timers) * NB_STRESS2_TIMERS, 0); if (timers == NULL) { printf("Test Failed\n"); printf("- Cannot allocate memory for timers\n" ); test_failed = 1; - master_start_slaves(); + main_start_workers(); goto cleanup; } for (i = 0; i < NB_STRESS2_TIMERS; i++) rte_timer_init(&timers[i]); - master_start_slaves(); + main_start_workers(); } else { - slave_wait_to_start(); + worker_wait_to_start(); if (test_failed) goto cleanup; } - /* have all cores schedule all timers on master lcore */ + /* have all cores schedule all timers on main lcore */ for (i = 0; i < NB_STRESS2_TIMERS; i++) { - ret = rte_timer_reset(&timers[i], delay, SINGLE, master, + ret = rte_timer_reset(&timers[i], delay, SINGLE, main_lcore, timer_stress2_cb, NULL); /* there will be collisions when multiple cores simultaneously * configure the same timers */ @@ -349,14 +321,14 @@ timer_stress2_main_loop(__attribute__((unused)) void *arg) rte_delay_ms(100); /* all cores rendezvous */ - if (lcore_id == master) { - master_wait_for_slaves(); + if (lcore_id == main_lcore) { + main_wait_for_workers(); } else { - slave_finish(); + worker_finish(); } /* now check that we get the right number of callbacks */ - if (lcore_id == master) { + if (lcore_id == main_lcore) { my_collisions = rte_atomic32_read(&collisions); if (my_collisions != 0) printf("- %d timer reset collisions (OK)\n", my_collisions); @@ -367,23 +339,23 @@ timer_stress2_main_loop(__attribute__((unused)) void *arg) printf("- Expected %d callbacks, got %d\n", NB_STRESS2_TIMERS, cb_count); test_failed = 1; - master_start_slaves(); + main_start_workers(); goto cleanup; } cb_count = 0; /* proceed */ - master_start_slaves(); + main_start_workers(); } else { /* proceed */ - slave_wait_to_start(); + worker_wait_to_start(); if (test_failed) goto cleanup; } /* now test again, just stop and restart timers at random after init*/ for (i = 0; i < NB_STRESS2_TIMERS; i++) - rte_timer_reset(&timers[i], delay, SINGLE, master, + rte_timer_reset(&timers[i], delay, SINGLE, main_lcore, timer_stress2_cb, NULL); /* pick random timer to reset, stopping them first half the time */ @@ -391,7 +363,7 @@ timer_stress2_main_loop(__attribute__((unused)) void *arg) int r = rand() % NB_STRESS2_TIMERS; if (i % 2) rte_timer_stop(&timers[r]); - rte_timer_reset(&timers[r], delay, SINGLE, master, + rte_timer_reset(&timers[r], delay, SINGLE, main_lcore, timer_stress2_cb, NULL); } @@ -399,8 +371,8 @@ timer_stress2_main_loop(__attribute__((unused)) void *arg) rte_delay_ms(100); /* now check that we get the right number of callbacks */ - if (lcore_id == master) { - master_wait_for_slaves(); + if (lcore_id == main_lcore) { + main_wait_for_workers(); rte_timer_manage(); if (cb_count != NB_STRESS2_TIMERS) { @@ -415,14 +387,14 @@ timer_stress2_main_loop(__attribute__((unused)) void *arg) } cleanup: - if (lcore_id == master) { - master_wait_for_slaves(); + if (lcore_id == main_lcore) { + main_wait_for_workers(); if (timers != NULL) { rte_free(timers); timers = NULL; } } else { - slave_finish(); + worker_finish(); } return 0; @@ -486,7 +458,7 @@ timer_basic_cb(struct rte_timer *tim, void *arg) } static int -timer_basic_main_loop(__attribute__((unused)) void *arg) +timer_basic_main_loop(__rte_unused void *arg) { uint64_t hz = rte_get_timer_hz(); unsigned lcore_id = rte_lcore_id(); @@ -494,7 +466,7 @@ timer_basic_main_loop(__attribute__((unused)) void *arg) int64_t diff = 0; /* launch all timers on core 0 */ - if (lcore_id == rte_get_master_lcore()) { + if (lcore_id == rte_get_main_lcore()) { mytimer_reset(&mytiminfo[0], hz/4, SINGLE, lcore_id, timer_basic_cb); mytimer_reset(&mytiminfo[1], hz/2, SINGLE, lcore_id, @@ -567,17 +539,17 @@ test_timer(void) uint64_t cur_time; uint64_t hz; + if (rte_lcore_count() < 2) { + printf("Not enough cores for timer_autotest, expecting at least 2\n"); + return TEST_SKIPPED; + } + /* sanity check our timer sources and timer config values */ if (timer_sanity_check() < 0) { printf("Timer sanity checks failed\n"); return TEST_FAILED; } - if (rte_lcore_count() < 2) { - printf("not enough lcores for this test\n"); - return TEST_FAILED; - } - /* init timer */ for (i=0; i