X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=app%2Ftest-bbdev%2Ftest_bbdev_perf.c;h=59b37ede4a88cdf64cb0909dcfd08b3bf6f6a17d;hb=439009e4ef3469ff1cd68d4ec71ca922f3a6d68f;hp=4d7dc4e6eddb8de994311f7b51044624832df1ab;hpb=335c11fd276345f9d5654918c29048269ed58e11;p=dpdk.git diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 4d7dc4e6ed..59b37ede4a 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -24,9 +24,10 @@ #define GET_SOCKET(socket_id) (((socket_id) == SOCKET_ID_ANY) ? 0 : (socket_id)) #define MAX_QUEUES RTE_MAX_LCORE -#define TEST_REPETITIONS 1000 +#define TEST_REPETITIONS 100 +#define WAIT_OFFLOAD_US 1000 -#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC +#ifdef RTE_BASEBAND_FPGA_LTE_FEC #include #define FPGA_LTE_PF_DRIVER_NAME ("intel_fpga_lte_fec_pf") #define FPGA_LTE_VF_DRIVER_NAME ("intel_fpga_lte_fec_vf") @@ -39,6 +40,31 @@ #define FLR_4G_TIMEOUT 610 #endif +#ifdef RTE_BASEBAND_FPGA_5GNR_FEC +#include +#define FPGA_5GNR_PF_DRIVER_NAME ("intel_fpga_5gnr_fec_pf") +#define FPGA_5GNR_VF_DRIVER_NAME ("intel_fpga_5gnr_fec_vf") +#define VF_UL_5G_QUEUE_VALUE 4 +#define VF_DL_5G_QUEUE_VALUE 4 +#define UL_5G_BANDWIDTH 3 +#define DL_5G_BANDWIDTH 3 +#define UL_5G_LOAD_BALANCE 128 +#define DL_5G_LOAD_BALANCE 128 +#define FLR_5G_TIMEOUT 610 +#endif + +#ifdef RTE_BASEBAND_ACC100 +#include +#define ACC100PF_DRIVER_NAME ("intel_acc100_pf") +#define ACC100VF_DRIVER_NAME ("intel_acc100_vf") +#define ACC100_QMGR_NUM_AQS 16 +#define ACC100_QMGR_NUM_QGS 2 +#define ACC100_QMGR_AQ_DEPTH 5 +#define ACC100_QMGR_INVALID_IDX -1 +#define ACC100_QMGR_RR 1 +#define ACC100_QOS_GBR 0 +#endif + #define OPS_CACHE_SIZE 256U #define OPS_POOL_SIZE_MIN 511U /* 0.5K per queue */ @@ -120,6 +146,8 @@ struct thread_params { double ops_per_sec; double mbps; uint8_t iter_count; + double iter_average; + double bler; rte_atomic16_t nb_dequeued; rte_atomic16_t processing_status; rte_atomic16_t burst_sz; @@ -550,17 +578,17 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, /* Configure fpga lte fec with PF & VF values * if '-i' flag is set and using fpga device */ -#ifdef RTE_LIBRTE_PMD_BBDEV_FPGA_LTE_FEC +#ifdef RTE_BASEBAND_FPGA_LTE_FEC if ((get_init_device() == true) && (!strcmp(info->drv.driver_name, FPGA_LTE_PF_DRIVER_NAME))) { - struct fpga_lte_fec_conf conf; + struct rte_fpga_lte_fec_conf conf; unsigned int i; printf("Configure FPGA LTE FEC Driver %s with default values\n", info->drv.driver_name); /* clear default configuration before initialization */ - memset(&conf, 0, sizeof(struct fpga_lte_fec_conf)); + memset(&conf, 0, sizeof(struct rte_fpga_lte_fec_conf)); /* Set PF mode : * true if PF is used for data plane @@ -588,12 +616,115 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info, conf.flr_time_out = FLR_4G_TIMEOUT; /* setup FPGA PF with configuration information */ - ret = fpga_lte_fec_configure(info->dev_name, &conf); + ret = rte_fpga_lte_fec_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, "Failed to configure 4G FPGA PF for bbdev %s", info->dev_name); } #endif +#ifdef RTE_BASEBAND_FPGA_5GNR_FEC + if ((get_init_device() == true) && + (!strcmp(info->drv.driver_name, FPGA_5GNR_PF_DRIVER_NAME))) { + struct rte_fpga_5gnr_fec_conf conf; + unsigned int i; + + printf("Configure FPGA 5GNR FEC Driver %s with default values\n", + info->drv.driver_name); + + /* clear default configuration before initialization */ + memset(&conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf)); + + /* Set PF mode : + * true if PF is used for data plane + * false for VFs + */ + conf.pf_mode_en = true; + + for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) { + /* Number of UL queues per VF (fpga supports 8 VFs) */ + conf.vf_ul_queues_number[i] = VF_UL_5G_QUEUE_VALUE; + /* Number of DL queues per VF (fpga supports 8 VFs) */ + conf.vf_dl_queues_number[i] = VF_DL_5G_QUEUE_VALUE; + } + + /* UL bandwidth. Needed for schedule algorithm */ + conf.ul_bandwidth = UL_5G_BANDWIDTH; + /* DL bandwidth */ + conf.dl_bandwidth = DL_5G_BANDWIDTH; + + /* UL & DL load Balance Factor to 64 */ + conf.ul_load_balance = UL_5G_LOAD_BALANCE; + conf.dl_load_balance = DL_5G_LOAD_BALANCE; + + /**< FLR timeout value */ + conf.flr_time_out = FLR_5G_TIMEOUT; + + /* setup FPGA PF with configuration information */ + ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf); + TEST_ASSERT_SUCCESS(ret, + "Failed to configure 5G FPGA PF for bbdev %s", + info->dev_name); + } +#endif +#ifdef RTE_BASEBAND_ACC100 + if ((get_init_device() == true) && + (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) { + struct rte_acc100_conf conf; + unsigned int i; + + printf("Configure ACC100 FEC Driver %s with default values\n", + info->drv.driver_name); + + /* clear default configuration before initialization */ + memset(&conf, 0, sizeof(struct rte_acc100_conf)); + + /* Always set in PF mode for built-in configuration */ + conf.pf_mode_en = true; + for (i = 0; i < RTE_ACC100_NUM_VFS; ++i) { + conf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_dl_4g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_dl_4g[i].round_robin_weight = ACC100_QMGR_RR; + conf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_ul_4g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_ul_4g[i].round_robin_weight = ACC100_QMGR_RR; + conf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_dl_5g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_dl_5g[i].round_robin_weight = ACC100_QMGR_RR; + conf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_ul_5g[i].gbr_threshold1 = ACC100_QOS_GBR; + conf.arb_ul_5g[i].round_robin_weight = ACC100_QMGR_RR; + } + + conf.input_pos_llr_1_bit = true; + conf.output_pos_llr_1_bit = true; + conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */ + + conf.q_ul_4g.num_qgroups = ACC100_QMGR_NUM_QGS; + conf.q_ul_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX; + conf.q_ul_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS; + conf.q_ul_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; + conf.q_dl_4g.num_qgroups = ACC100_QMGR_NUM_QGS; + conf.q_dl_4g.first_qgroup_index = ACC100_QMGR_INVALID_IDX; + conf.q_dl_4g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS; + conf.q_dl_4g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; + conf.q_ul_5g.num_qgroups = ACC100_QMGR_NUM_QGS; + conf.q_ul_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX; + conf.q_ul_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS; + conf.q_ul_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; + conf.q_dl_5g.num_qgroups = ACC100_QMGR_NUM_QGS; + conf.q_dl_5g.first_qgroup_index = ACC100_QMGR_INVALID_IDX; + conf.q_dl_5g.num_aqs_per_groups = ACC100_QMGR_NUM_AQS; + conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; + + /* setup PF with configuration information */ + ret = rte_acc100_configure(info->dev_name, &conf); + TEST_ASSERT_SUCCESS(ret, + "Failed to configure ACC100 PF for bbdev %s", + info->dev_name); + } +#endif + /* Let's refresh this now this is configured */ + rte_bbdev_info_get(dev_id, info); nb_queues = RTE_MIN(rte_lcore_count(), info->drv.max_num_queues); nb_queues = RTE_MIN(nb_queues, (unsigned int) MAX_QUEUES); @@ -752,6 +883,9 @@ testsuite_teardown(void) /* Clear active devices structs. */ memset(active_devs, 0, sizeof(active_devs)); nb_active_devs = 0; + + /* Disable interrupts */ + intr_enabled = false; } static int @@ -1207,6 +1341,312 @@ copy_reference_enc_op(struct rte_bbdev_enc_op **ops, unsigned int n, } } + +/* Returns a random number drawn from a normal distribution + * with mean of 0 and variance of 1 + * Marsaglia algorithm + */ +static double +randn(int n) +{ + double S, Z, U1, U2, u, v, fac; + + do { + U1 = (double)rand() / RAND_MAX; + U2 = (double)rand() / RAND_MAX; + u = 2. * U1 - 1.; + v = 2. * U2 - 1.; + S = u * u + v * v; + } while (S >= 1 || S == 0); + fac = sqrt(-2. * log(S) / S); + Z = (n % 2) ? u * fac : v * fac; + return Z; +} + +static inline double +maxstar(double A, double B) +{ + if (fabs(A - B) > 5) + return RTE_MAX(A, B); + else + return RTE_MAX(A, B) + log1p(exp(-fabs(A - B))); +} + +/* + * Generate Qm LLRS for Qm==8 + * Modulation, AWGN and LLR estimation from max log development + */ +static void +gen_qm8_llr(int8_t *llrs, uint32_t i, double N0, double llr_max) +{ + int qm = 8; + int qam = 256; + int m, k; + double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam]; + /* 5.1.4 of TS38.211 */ + const double symbols_I[256] = { + 5, 5, 7, 7, 5, 5, 7, 7, 3, 3, 1, 1, 3, 3, 1, 1, 5, + 5, 7, 7, 5, 5, 7, 7, 3, 3, 1, 1, 3, 3, 1, 1, 11, + 11, 9, 9, 11, 11, 9, 9, 13, 13, 15, 15, 13, 13, + 15, 15, 11, 11, 9, 9, 11, 11, 9, 9, 13, 13, 15, + 15, 13, 13, 15, 15, 5, 5, 7, 7, 5, 5, 7, 7, 3, 3, + 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7, 3, 3, 1, + 1, 3, 3, 1, 1, 11, 11, 9, 9, 11, 11, 9, 9, 13, 13, + 15, 15, 13, 13, 15, 15, 11, 11, 9, 9, 11, 11, 9, 9, + 13, 13, 15, 15, 13, 13, 15, 15, -5, -5, -7, -7, -5, + -5, -7, -7, -3, -3, -1, -1, -3, -3, -1, -1, -5, -5, + -7, -7, -5, -5, -7, -7, -3, -3, -1, -1, -3, -3, + -1, -1, -11, -11, -9, -9, -11, -11, -9, -9, -13, + -13, -15, -15, -13, -13, -15, -15, -11, -11, -9, + -9, -11, -11, -9, -9, -13, -13, -15, -15, -13, + -13, -15, -15, -5, -5, -7, -7, -5, -5, -7, -7, -3, + -3, -1, -1, -3, -3, -1, -1, -5, -5, -7, -7, -5, -5, + -7, -7, -3, -3, -1, -1, -3, -3, -1, -1, -11, -11, + -9, -9, -11, -11, -9, -9, -13, -13, -15, -15, -13, + -13, -15, -15, -11, -11, -9, -9, -11, -11, -9, -9, + -13, -13, -15, -15, -13, -13, -15, -15}; + const double symbols_Q[256] = { + 5, 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, 11, + 9, 11, 9, 13, 15, 13, 15, 11, 9, 11, 9, 13, 15, 13, + 15, 5, 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, + 11, 9, 11, 9, 13, 15, 13, 15, 11, 9, 11, 9, 13, + 15, 13, 15, -5, -7, -5, -7, -3, -1, -3, -1, -5, + -7, -5, -7, -3, -1, -3, -1, -11, -9, -11, -9, -13, + -15, -13, -15, -11, -9, -11, -9, -13, -15, -13, + -15, -5, -7, -5, -7, -3, -1, -3, -1, -5, -7, -5, + -7, -3, -1, -3, -1, -11, -9, -11, -9, -13, -15, + -13, -15, -11, -9, -11, -9, -13, -15, -13, -15, 5, + 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, 11, + 9, 11, 9, 13, 15, 13, 15, 11, 9, 11, 9, 13, 15, + 13, 15, 5, 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, + 3, 1, 11, 9, 11, 9, 13, 15, 13, 15, 11, 9, 11, 9, + 13, 15, 13, 15, -5, -7, -5, -7, -3, -1, -3, -1, + -5, -7, -5, -7, -3, -1, -3, -1, -11, -9, -11, -9, + -13, -15, -13, -15, -11, -9, -11, -9, -13, -15, + -13, -15, -5, -7, -5, -7, -3, -1, -3, -1, -5, -7, + -5, -7, -3, -1, -3, -1, -11, -9, -11, -9, -13, -15, + -13, -15, -11, -9, -11, -9, -13, -15, -13, -15}; + /* Average constellation point energy */ + N0 *= 170.0; + for (k = 0; k < qm; k++) + b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0; + /* 5.1.4 of TS38.211 */ + I = (1 - 2 * b[0]) * (8 - (1 - 2 * b[2]) * + (4 - (1 - 2 * b[4]) * (2 - (1 - 2 * b[6])))); + Q = (1 - 2 * b[1]) * (8 - (1 - 2 * b[3]) * + (4 - (1 - 2 * b[5]) * (2 - (1 - 2 * b[7])))); + /* AWGN channel */ + I += sqrt(N0 / 2) * randn(0); + Q += sqrt(N0 / 2) * randn(1); + /* + * Calculate the log of the probability that each of + * the constellation points was transmitted + */ + for (m = 0; m < qam; m++) + log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0) + + pow(Q - symbols_Q[m], 2.0)) / N0; + /* Calculate an LLR for each of the k_64QAM bits in the set */ + for (k = 0; k < qm; k++) { + p0 = -999999; + p1 = -999999; + /* For each constellation point */ + for (m = 0; m < qam; m++) { + if ((m >> (qm - k - 1)) & 1) + p1 = maxstar(p1, log_syml_prob[m]); + else + p0 = maxstar(p0, log_syml_prob[m]); + } + /* Calculate the LLR */ + llr_ = p0 - p1; + llr_ *= (1 << ldpc_llr_decimals); + llr_ = round(llr_); + if (llr_ > llr_max) + llr_ = llr_max; + if (llr_ < -llr_max) + llr_ = -llr_max; + llrs[qm * i + k] = (int8_t) llr_; + } +} + + +/* + * Generate Qm LLRS for Qm==6 + * Modulation, AWGN and LLR estimation from max log development + */ +static void +gen_qm6_llr(int8_t *llrs, uint32_t i, double N0, double llr_max) +{ + int qm = 6; + int qam = 64; + int m, k; + double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam]; + /* 5.1.4 of TS38.211 */ + const double symbols_I[64] = { + 3, 3, 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7, + 3, 3, 1, 1, 3, 3, 1, 1, 5, 5, 7, 7, 5, 5, 7, 7, + -3, -3, -1, -1, -3, -3, -1, -1, -5, -5, -7, -7, + -5, -5, -7, -7, -3, -3, -1, -1, -3, -3, -1, -1, + -5, -5, -7, -7, -5, -5, -7, -7}; + const double symbols_Q[64] = { + 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, 5, 7, 5, 7, + -3, -1, -3, -1, -5, -7, -5, -7, -3, -1, -3, -1, + -5, -7, -5, -7, 3, 1, 3, 1, 5, 7, 5, 7, 3, 1, 3, 1, + 5, 7, 5, 7, -3, -1, -3, -1, -5, -7, -5, -7, + -3, -1, -3, -1, -5, -7, -5, -7}; + /* Average constellation point energy */ + N0 *= 42.0; + for (k = 0; k < qm; k++) + b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0; + /* 5.1.4 of TS38.211 */ + I = (1 - 2 * b[0])*(4 - (1 - 2 * b[2]) * (2 - (1 - 2 * b[4]))); + Q = (1 - 2 * b[1])*(4 - (1 - 2 * b[3]) * (2 - (1 - 2 * b[5]))); + /* AWGN channel */ + I += sqrt(N0 / 2) * randn(0); + Q += sqrt(N0 / 2) * randn(1); + /* + * Calculate the log of the probability that each of + * the constellation points was transmitted + */ + for (m = 0; m < qam; m++) + log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0) + + pow(Q - symbols_Q[m], 2.0)) / N0; + /* Calculate an LLR for each of the k_64QAM bits in the set */ + for (k = 0; k < qm; k++) { + p0 = -999999; + p1 = -999999; + /* For each constellation point */ + for (m = 0; m < qam; m++) { + if ((m >> (qm - k - 1)) & 1) + p1 = maxstar(p1, log_syml_prob[m]); + else + p0 = maxstar(p0, log_syml_prob[m]); + } + /* Calculate the LLR */ + llr_ = p0 - p1; + llr_ *= (1 << ldpc_llr_decimals); + llr_ = round(llr_); + if (llr_ > llr_max) + llr_ = llr_max; + if (llr_ < -llr_max) + llr_ = -llr_max; + llrs[qm * i + k] = (int8_t) llr_; + } +} + +/* + * Generate Qm LLRS for Qm==4 + * Modulation, AWGN and LLR estimation from max log development + */ +static void +gen_qm4_llr(int8_t *llrs, uint32_t i, double N0, double llr_max) +{ + int qm = 4; + int qam = 16; + int m, k; + double I, Q, p0, p1, llr_, b[qm], log_syml_prob[qam]; + /* 5.1.4 of TS38.211 */ + const double symbols_I[16] = {1, 1, 3, 3, 1, 1, 3, 3, + -1, -1, -3, -3, -1, -1, -3, -3}; + const double symbols_Q[16] = {1, 3, 1, 3, -1, -3, -1, -3, + 1, 3, 1, 3, -1, -3, -1, -3}; + /* Average constellation point energy */ + N0 *= 10.0; + for (k = 0; k < qm; k++) + b[k] = llrs[qm * i + k] < 0 ? 1.0 : 0.0; + /* 5.1.4 of TS38.211 */ + I = (1 - 2 * b[0]) * (2 - (1 - 2 * b[2])); + Q = (1 - 2 * b[1]) * (2 - (1 - 2 * b[3])); + /* AWGN channel */ + I += sqrt(N0 / 2) * randn(0); + Q += sqrt(N0 / 2) * randn(1); + /* + * Calculate the log of the probability that each of + * the constellation points was transmitted + */ + for (m = 0; m < qam; m++) + log_syml_prob[m] = -(pow(I - symbols_I[m], 2.0) + + pow(Q - symbols_Q[m], 2.0)) / N0; + /* Calculate an LLR for each of the k_64QAM bits in the set */ + for (k = 0; k < qm; k++) { + p0 = -999999; + p1 = -999999; + /* For each constellation point */ + for (m = 0; m < qam; m++) { + if ((m >> (qm - k - 1)) & 1) + p1 = maxstar(p1, log_syml_prob[m]); + else + p0 = maxstar(p0, log_syml_prob[m]); + } + /* Calculate the LLR */ + llr_ = p0 - p1; + llr_ *= (1 << ldpc_llr_decimals); + llr_ = round(llr_); + if (llr_ > llr_max) + llr_ = llr_max; + if (llr_ < -llr_max) + llr_ = -llr_max; + llrs[qm * i + k] = (int8_t) llr_; + } +} + +static void +gen_qm2_llr(int8_t *llrs, uint32_t j, double N0, double llr_max) +{ + double b, b1, n; + double coeff = 2.0 * sqrt(N0); + + /* Ignore in vectors rare quasi null LLRs not to be saturated */ + if (llrs[j] < 8 && llrs[j] > -8) + return; + + /* Note don't change sign here */ + n = randn(j % 2); + b1 = ((llrs[j] > 0 ? 2.0 : -2.0) + + coeff * n) / N0; + b = b1 * (1 << ldpc_llr_decimals); + b = round(b); + if (b > llr_max) + b = llr_max; + if (b < -llr_max) + b = -llr_max; + llrs[j] = (int8_t) b; +} + +/* Generate LLR for a given SNR */ +static void +generate_llr_input(uint16_t n, struct rte_bbdev_op_data *inputs, + struct rte_bbdev_dec_op *ref_op) +{ + struct rte_mbuf *m; + uint16_t qm; + uint32_t i, j, e, range; + double N0, llr_max; + + e = ref_op->ldpc_dec.cb_params.e; + qm = ref_op->ldpc_dec.q_m; + llr_max = (1 << (ldpc_llr_size - 1)) - 1; + range = e / qm; + N0 = 1.0 / pow(10.0, get_snr() / 10.0); + + for (i = 0; i < n; ++i) { + m = inputs[i].data; + int8_t *llrs = rte_pktmbuf_mtod_offset(m, int8_t *, 0); + if (qm == 8) { + for (j = 0; j < range; ++j) + gen_qm8_llr(llrs, j, N0, llr_max); + } else if (qm == 6) { + for (j = 0; j < range; ++j) + gen_qm6_llr(llrs, j, N0, llr_max); + } else if (qm == 4) { + for (j = 0; j < range; ++j) + gen_qm4_llr(llrs, j, N0, llr_max); + } else { + for (j = 0; j < e; ++j) + gen_qm2_llr(llrs, j, N0, llr_max); + } + } +} + static void copy_reference_ldpc_dec_op(struct rte_bbdev_dec_op **ops, unsigned int n, unsigned int start_idx, @@ -1593,6 +2033,30 @@ validate_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n, return TEST_SUCCESS; } +/* Check Number of code blocks errors */ +static int +validate_ldpc_bler(struct rte_bbdev_dec_op **ops, const uint16_t n) +{ + unsigned int i; + struct op_data_entries *hard_data_orig = + &test_vector.entries[DATA_HARD_OUTPUT]; + struct rte_bbdev_op_ldpc_dec *ops_td; + struct rte_bbdev_op_data *hard_output; + int errors = 0; + struct rte_mbuf *m; + + for (i = 0; i < n; ++i) { + ops_td = &ops[i]->ldpc_dec; + hard_output = &ops_td->hard_output; + m = hard_output->data; + if (memcmp(rte_pktmbuf_mtod_offset(m, uint32_t *, 0), + hard_data_orig->segments[0].addr, + hard_data_orig->segments[0].length)) + errors++; + } + return errors; +} + static int validate_ldpc_dec_op(struct rte_bbdev_dec_op **ops, const uint16_t n, struct rte_bbdev_dec_op *ref_op, const int vector_mask) @@ -2004,7 +2468,7 @@ retrieve_harq_ddr(uint16_t dev_id, uint16_t queue_id, { uint16_t j; int save_status, ret; - uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024; + uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * MAX_OPS; struct rte_bbdev_dec_op *ops_deq[MAX_BURST]; uint32_t flags = ops[0]->ldpc_dec.op_flags; bool loopback = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK; @@ -2050,20 +2514,20 @@ preload_harq_ddr(uint16_t dev_id, uint16_t queue_id, bool preload) { uint16_t j; - int ret; - uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024; - struct rte_bbdev_op_data save_hc_in, save_hc_out; - struct rte_bbdev_dec_op *ops_deq[MAX_BURST]; + int deq; + uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * MAX_OPS; + struct rte_bbdev_op_data save_hc_in[MAX_OPS], save_hc_out[MAX_OPS]; + struct rte_bbdev_dec_op *ops_deq[MAX_OPS]; uint32_t flags = ops[0]->ldpc_dec.op_flags; bool mem_in = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE; bool hc_in = flags & RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; bool mem_out = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE; bool hc_out = flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; bool h_comp = flags & RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; - for (j = 0; j < n; ++j) { - if ((mem_in || hc_in) && preload) { - save_hc_in = ops[j]->ldpc_dec.harq_combined_input; - save_hc_out = ops[j]->ldpc_dec.harq_combined_output; + if ((mem_in || hc_in) && preload) { + for (j = 0; j < n; ++j) { + save_hc_in[j] = ops[j]->ldpc_dec.harq_combined_input; + save_hc_out[j] = ops[j]->ldpc_dec.harq_combined_output; ops[j]->ldpc_dec.op_flags = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE; @@ -2073,16 +2537,23 @@ preload_harq_ddr(uint16_t dev_id, uint16_t queue_id, ops[j]->ldpc_dec.harq_combined_output.offset = harq_offset; ops[j]->ldpc_dec.harq_combined_input.offset = 0; - rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id, - &ops[j], 1); - ret = 0; - while (ret == 0) - ret = rte_bbdev_dequeue_ldpc_dec_ops( - dev_id, queue_id, &ops_deq[j], 1); + harq_offset += HARQ_INCR; + } + rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id, &ops[0], n); + deq = 0; + while (deq != n) + deq += rte_bbdev_dequeue_ldpc_dec_ops( + dev_id, queue_id, &ops_deq[deq], + n - deq); + /* Restore the operations */ + for (j = 0; j < n; ++j) { ops[j]->ldpc_dec.op_flags = flags; - ops[j]->ldpc_dec.harq_combined_input = save_hc_in; - ops[j]->ldpc_dec.harq_combined_output = save_hc_out; + ops[j]->ldpc_dec.harq_combined_input = save_hc_in[j]; + ops[j]->ldpc_dec.harq_combined_output = save_hc_out[j]; } + } + harq_offset = (uint32_t) queue_id * HARQ_INCR * MAX_OPS; + for (j = 0; j < n; ++j) { /* Adjust HARQ offset when we reach external DDR */ if (mem_in || hc_in) ops[j]->ldpc_dec.harq_combined_input.offset @@ -2229,6 +2700,109 @@ dequeue_event_callback(uint16_t dev_id, rte_atomic16_add(&tp->nb_dequeued, deq); } +static int +throughput_intr_lcore_ldpc_dec(void *arg) +{ + struct thread_params *tp = arg; + unsigned int enqueued; + const uint16_t queue_id = tp->queue_id; + const uint16_t burst_sz = tp->op_params->burst_sz; + const uint16_t num_to_process = tp->op_params->num_to_process; + struct rte_bbdev_dec_op *ops[num_to_process]; + struct test_buffers *bufs = NULL; + struct rte_bbdev_info info; + int ret, i, j; + struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op; + uint16_t num_to_enq, enq; + + bool loopback = check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK); + bool hc_out = check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE); + + TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST), + "BURST_SIZE should be <= %u", MAX_BURST); + + TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id), + "Failed to enable interrupts for dev: %u, queue_id: %u", + tp->dev_id, queue_id); + + rte_bbdev_info_get(tp->dev_id, &info); + + TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim), + "NUM_OPS cannot exceed %u for this device", + info.drv.queue_size_lim); + + bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id]; + + rte_atomic16_clear(&tp->processing_status); + rte_atomic16_clear(&tp->nb_dequeued); + + while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT) + rte_pause(); + + ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops, + num_to_process); + TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", + num_to_process); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_dec_op(ops, num_to_process, 0, bufs->inputs, + bufs->hard_outputs, bufs->soft_outputs, + bufs->harq_inputs, bufs->harq_outputs, ref_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < num_to_process; ++j) + ops[j]->opaque_data = (void *)(uintptr_t)j; + + for (j = 0; j < TEST_REPETITIONS; ++j) { + for (i = 0; i < num_to_process; ++i) { + if (!loopback) + rte_pktmbuf_reset( + ops[i]->ldpc_dec.hard_output.data); + if (hc_out || loopback) + mbuf_reset( + ops[i]->ldpc_dec.harq_combined_output.data); + } + + tp->start_time = rte_rdtsc_precise(); + for (enqueued = 0; enqueued < num_to_process;) { + num_to_enq = burst_sz; + + if (unlikely(num_to_process - enqueued < num_to_enq)) + num_to_enq = num_to_process - enqueued; + + enq = 0; + do { + enq += rte_bbdev_enqueue_ldpc_dec_ops( + tp->dev_id, + queue_id, &ops[enqueued], + num_to_enq); + } while (unlikely(num_to_enq != enq)); + enqueued += enq; + + /* Write to thread burst_sz current number of enqueued + * descriptors. It ensures that proper number of + * descriptors will be dequeued in callback + * function - needed for last batch in case where + * the number of operations is not a multiple of + * burst size. + */ + rte_atomic16_set(&tp->burst_sz, num_to_enq); + + /* Wait until processing of previous batch is + * completed + */ + while (rte_atomic16_read(&tp->nb_dequeued) != + (int16_t) enqueued) + rte_pause(); + } + if (j != TEST_REPETITIONS - 1) + rte_atomic16_clear(&tp->nb_dequeued); + } + + return TEST_SUCCESS; +} + static int throughput_intr_lcore_dec(void *arg) { @@ -2408,43 +2982,135 @@ throughput_intr_lcore_enc(void *arg) return TEST_SUCCESS; } + static int -throughput_pmd_lcore_dec(void *arg) +throughput_intr_lcore_ldpc_enc(void *arg) { struct thread_params *tp = arg; - uint16_t enq, deq; - uint64_t total_time = 0, start_time; + unsigned int enqueued; const uint16_t queue_id = tp->queue_id; const uint16_t burst_sz = tp->op_params->burst_sz; - const uint16_t num_ops = tp->op_params->num_to_process; - struct rte_bbdev_dec_op *ops_enq[num_ops]; - struct rte_bbdev_dec_op *ops_deq[num_ops]; - struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op; + const uint16_t num_to_process = tp->op_params->num_to_process; + struct rte_bbdev_enc_op *ops[num_to_process]; struct test_buffers *bufs = NULL; - int i, j, ret; struct rte_bbdev_info info; - uint16_t num_to_enq; + int ret, i, j; + uint16_t num_to_enq, enq; TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST), "BURST_SIZE should be <= %u", MAX_BURST); + TEST_ASSERT_SUCCESS(rte_bbdev_queue_intr_enable(tp->dev_id, queue_id), + "Failed to enable interrupts for dev: %u, queue_id: %u", + tp->dev_id, queue_id); + rte_bbdev_info_get(tp->dev_id, &info); - TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim), + TEST_ASSERT_SUCCESS((num_to_process > info.drv.queue_size_lim), "NUM_OPS cannot exceed %u for this device", info.drv.queue_size_lim); bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id]; + rte_atomic16_clear(&tp->processing_status); + rte_atomic16_clear(&tp->nb_dequeued); + while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT) rte_pause(); - ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops); - TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops); - - if (test_vector.op_type != RTE_BBDEV_OP_NONE) - copy_reference_dec_op(ops_enq, num_ops, 0, bufs->inputs, - bufs->hard_outputs, bufs->soft_outputs, ref_op); + ret = rte_bbdev_enc_op_alloc_bulk(tp->op_params->mp, ops, + num_to_process); + TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", + num_to_process); + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_enc_op(ops, num_to_process, 0, + bufs->inputs, bufs->hard_outputs, + tp->op_params->ref_enc_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < num_to_process; ++j) + ops[j]->opaque_data = (void *)(uintptr_t)j; + + for (j = 0; j < TEST_REPETITIONS; ++j) { + for (i = 0; i < num_to_process; ++i) + rte_pktmbuf_reset(ops[i]->turbo_enc.output.data); + + tp->start_time = rte_rdtsc_precise(); + for (enqueued = 0; enqueued < num_to_process;) { + num_to_enq = burst_sz; + + if (unlikely(num_to_process - enqueued < num_to_enq)) + num_to_enq = num_to_process - enqueued; + + enq = 0; + do { + enq += rte_bbdev_enqueue_ldpc_enc_ops( + tp->dev_id, + queue_id, &ops[enqueued], + num_to_enq); + } while (unlikely(enq != num_to_enq)); + enqueued += enq; + + /* Write to thread burst_sz current number of enqueued + * descriptors. It ensures that proper number of + * descriptors will be dequeued in callback + * function - needed for last batch in case where + * the number of operations is not a multiple of + * burst size. + */ + rte_atomic16_set(&tp->burst_sz, num_to_enq); + + /* Wait until processing of previous batch is + * completed + */ + while (rte_atomic16_read(&tp->nb_dequeued) != + (int16_t) enqueued) + rte_pause(); + } + if (j != TEST_REPETITIONS - 1) + rte_atomic16_clear(&tp->nb_dequeued); + } + + return TEST_SUCCESS; +} + +static int +throughput_pmd_lcore_dec(void *arg) +{ + struct thread_params *tp = arg; + uint16_t enq, deq; + uint64_t total_time = 0, start_time; + const uint16_t queue_id = tp->queue_id; + const uint16_t burst_sz = tp->op_params->burst_sz; + const uint16_t num_ops = tp->op_params->num_to_process; + struct rte_bbdev_dec_op *ops_enq[num_ops]; + struct rte_bbdev_dec_op *ops_deq[num_ops]; + struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op; + struct test_buffers *bufs = NULL; + int i, j, ret; + struct rte_bbdev_info info; + uint16_t num_to_enq; + + TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST), + "BURST_SIZE should be <= %u", MAX_BURST); + + rte_bbdev_info_get(tp->dev_id, &info); + + TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim), + "NUM_OPS cannot exceed %u for this device", + info.drv.queue_size_lim); + + bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id]; + + while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT) + rte_pause(); + + ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops); + TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops); + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_dec_op(ops_enq, num_ops, 0, bufs->inputs, + bufs->hard_outputs, bufs->soft_outputs, ref_op); /* Set counter to validate the ordering */ for (j = 0; j < num_ops; ++j) @@ -2505,6 +3171,137 @@ throughput_pmd_lcore_dec(void *arg) return TEST_SUCCESS; } +static int +bler_pmd_lcore_ldpc_dec(void *arg) +{ + struct thread_params *tp = arg; + uint16_t enq, deq; + uint64_t total_time = 0, start_time; + const uint16_t queue_id = tp->queue_id; + const uint16_t burst_sz = tp->op_params->burst_sz; + const uint16_t num_ops = tp->op_params->num_to_process; + struct rte_bbdev_dec_op *ops_enq[num_ops]; + struct rte_bbdev_dec_op *ops_deq[num_ops]; + struct rte_bbdev_dec_op *ref_op = tp->op_params->ref_dec_op; + struct test_buffers *bufs = NULL; + int i, j, ret; + float parity_bler = 0; + struct rte_bbdev_info info; + uint16_t num_to_enq; + bool extDdr = check_bit(ldpc_cap_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE); + bool loopback = check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK); + bool hc_out = check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE); + + TEST_ASSERT_SUCCESS((burst_sz > MAX_BURST), + "BURST_SIZE should be <= %u", MAX_BURST); + + rte_bbdev_info_get(tp->dev_id, &info); + + TEST_ASSERT_SUCCESS((num_ops > info.drv.queue_size_lim), + "NUM_OPS cannot exceed %u for this device", + info.drv.queue_size_lim); + + bufs = &tp->op_params->q_bufs[GET_SOCKET(info.socket_id)][queue_id]; + + while (rte_atomic16_read(&tp->op_params->sync) == SYNC_WAIT) + rte_pause(); + + ret = rte_bbdev_dec_op_alloc_bulk(tp->op_params->mp, ops_enq, num_ops); + TEST_ASSERT_SUCCESS(ret, "Allocation failed for %d ops", num_ops); + + /* For BLER tests we need to enable early termination */ + if (!check_bit(ref_op->ldpc_dec.op_flags, + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE)) + ref_op->ldpc_dec.op_flags += + RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE; + ref_op->ldpc_dec.iter_max = get_iter_max(); + ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max; + + if (test_vector.op_type != RTE_BBDEV_OP_NONE) + copy_reference_ldpc_dec_op(ops_enq, num_ops, 0, bufs->inputs, + bufs->hard_outputs, bufs->soft_outputs, + bufs->harq_inputs, bufs->harq_outputs, ref_op); + generate_llr_input(num_ops, bufs->inputs, ref_op); + + /* Set counter to validate the ordering */ + for (j = 0; j < num_ops; ++j) + ops_enq[j]->opaque_data = (void *)(uintptr_t)j; + + for (i = 0; i < 1; ++i) { /* Could add more iterations */ + for (j = 0; j < num_ops; ++j) { + if (!loopback) + mbuf_reset( + ops_enq[j]->ldpc_dec.hard_output.data); + if (hc_out || loopback) + mbuf_reset( + ops_enq[j]->ldpc_dec.harq_combined_output.data); + } + if (extDdr) + preload_harq_ddr(tp->dev_id, queue_id, ops_enq, + num_ops, true); + start_time = rte_rdtsc_precise(); + + for (enq = 0, deq = 0; enq < num_ops;) { + num_to_enq = burst_sz; + + if (unlikely(num_ops - enq < num_to_enq)) + num_to_enq = num_ops - enq; + + enq += rte_bbdev_enqueue_ldpc_dec_ops(tp->dev_id, + queue_id, &ops_enq[enq], num_to_enq); + + deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id, + queue_id, &ops_deq[deq], enq - deq); + } + + /* dequeue the remaining */ + while (deq < enq) { + deq += rte_bbdev_dequeue_ldpc_dec_ops(tp->dev_id, + queue_id, &ops_deq[deq], enq - deq); + } + + total_time += rte_rdtsc_precise() - start_time; + } + + tp->iter_count = 0; + tp->iter_average = 0; + /* get the max of iter_count for all dequeued ops */ + for (i = 0; i < num_ops; ++i) { + tp->iter_count = RTE_MAX(ops_enq[i]->ldpc_dec.iter_count, + tp->iter_count); + tp->iter_average += (double) ops_enq[i]->ldpc_dec.iter_count; + if (ops_enq[i]->status & (1 << RTE_BBDEV_SYNDROME_ERROR)) + parity_bler += 1.0; + } + + parity_bler /= num_ops; /* This one is based on SYND */ + tp->iter_average /= num_ops; + tp->bler = (double) validate_ldpc_bler(ops_deq, num_ops) / num_ops; + + if (test_vector.op_type != RTE_BBDEV_OP_NONE + && tp->bler == 0 + && parity_bler == 0 + && !hc_out) { + ret = validate_ldpc_dec_op(ops_deq, num_ops, ref_op, + tp->op_params->vector_mask); + TEST_ASSERT_SUCCESS(ret, "Validation failed!"); + } + + rte_bbdev_dec_op_free_bulk(ops_enq, num_ops); + + double tb_len_bits = calc_ldpc_dec_TB_size(ref_op); + tp->ops_per_sec = ((double)num_ops * 1) / + ((double)total_time / (double)rte_get_tsc_hz()); + tp->mbps = (((double)(num_ops * 1 * tb_len_bits)) / + 1000000.0) / ((double)total_time / + (double)rte_get_tsc_hz()); + + return TEST_SUCCESS; +} + static int throughput_pmd_lcore_ldpc_dec(void *arg) { @@ -2550,7 +3347,7 @@ throughput_pmd_lcore_ldpc_dec(void *arg) RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE)) ref_op->ldpc_dec.op_flags -= RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE; - ref_op->ldpc_dec.iter_max = 6; + ref_op->ldpc_dec.iter_max = get_iter_max(); ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max; if (test_vector.op_type != RTE_BBDEV_OP_NONE) @@ -2571,11 +3368,9 @@ throughput_pmd_lcore_ldpc_dec(void *arg) mbuf_reset( ops_enq[j]->ldpc_dec.harq_combined_output.data); } - if (extDdr) { - bool preload = i == (TEST_REPETITIONS - 1); + if (extDdr) preload_harq_ddr(tp->dev_id, queue_id, ops_enq, - num_ops, preload); - } + num_ops, true); start_time = rte_rdtsc_precise(); for (enq = 0, deq = 0; enq < num_ops;) { @@ -2831,27 +3626,151 @@ print_enc_throughput(struct thread_params *t_params, unsigned int used_cores) used_cores, total_mops, total_mbps); } +/* Aggregate the performance results over the number of cores used */ static void print_dec_throughput(struct thread_params *t_params, unsigned int used_cores) { - unsigned int iter = 0; + unsigned int core_idx = 0; double total_mops = 0, total_mbps = 0; uint8_t iter_count = 0; - for (iter = 0; iter < used_cores; iter++) { + for (core_idx = 0; core_idx < used_cores; core_idx++) { printf( "Throughput for core (%u): %.8lg Ops/s, %.8lg Mbps @ max %u iterations\n", - t_params[iter].lcore_id, t_params[iter].ops_per_sec, - t_params[iter].mbps, t_params[iter].iter_count); - total_mops += t_params[iter].ops_per_sec; - total_mbps += t_params[iter].mbps; - iter_count = RTE_MAX(iter_count, t_params[iter].iter_count); + t_params[core_idx].lcore_id, + t_params[core_idx].ops_per_sec, + t_params[core_idx].mbps, + t_params[core_idx].iter_count); + total_mops += t_params[core_idx].ops_per_sec; + total_mbps += t_params[core_idx].mbps; + iter_count = RTE_MAX(iter_count, + t_params[core_idx].iter_count); } printf( "\nTotal throughput for %u cores: %.8lg MOPS, %.8lg Mbps @ max %u iterations\n", used_cores, total_mops, total_mbps, iter_count); } +/* Aggregate the performance results over the number of cores used */ +static void +print_dec_bler(struct thread_params *t_params, unsigned int used_cores) +{ + unsigned int core_idx = 0; + double total_mbps = 0, total_bler = 0, total_iter = 0; + double snr = get_snr(); + + for (core_idx = 0; core_idx < used_cores; core_idx++) { + printf("Core%u BLER %.1f %% - Iters %.1f - Tp %.1f Mbps %s\n", + t_params[core_idx].lcore_id, + t_params[core_idx].bler * 100, + t_params[core_idx].iter_average, + t_params[core_idx].mbps, + get_vector_filename()); + total_mbps += t_params[core_idx].mbps; + total_bler += t_params[core_idx].bler; + total_iter += t_params[core_idx].iter_average; + } + total_bler /= used_cores; + total_iter /= used_cores; + + printf("SNR %.2f BLER %.1f %% - Iterations %.1f %d - Tp %.1f Mbps %s\n", + snr, total_bler * 100, total_iter, get_iter_max(), + total_mbps, get_vector_filename()); +} + +/* + * Test function that determines BLER wireless performance + */ +static int +bler_test(struct active_device *ad, + struct test_op_params *op_params) +{ + int ret; + unsigned int lcore_id, used_cores = 0; + struct thread_params *t_params; + struct rte_bbdev_info info; + lcore_function_t *bler_function; + uint16_t num_lcores; + const char *op_type_str; + + rte_bbdev_info_get(ad->dev_id, &info); + + op_type_str = rte_bbdev_op_type_str(test_vector.op_type); + TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", + test_vector.op_type); + + printf("+ ------------------------------------------------------- +\n"); + printf("== test: bler\ndev: %s, nb_queues: %u, burst size: %u, num ops: %u, num_lcores: %u, op type: %s, itr mode: %s, GHz: %lg\n", + info.dev_name, ad->nb_queues, op_params->burst_sz, + op_params->num_to_process, op_params->num_lcores, + op_type_str, + intr_enabled ? "Interrupt mode" : "PMD mode", + (double)rte_get_tsc_hz() / 1000000000.0); + + /* Set number of lcores */ + num_lcores = (ad->nb_queues < (op_params->num_lcores)) + ? ad->nb_queues + : op_params->num_lcores; + + /* Allocate memory for thread parameters structure */ + t_params = rte_zmalloc(NULL, num_lcores * sizeof(struct thread_params), + RTE_CACHE_LINE_SIZE); + TEST_ASSERT_NOT_NULL(t_params, "Failed to alloc %zuB for t_params", + RTE_ALIGN(sizeof(struct thread_params) * num_lcores, + RTE_CACHE_LINE_SIZE)); + + if ((test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) && + !check_bit(test_vector.ldpc_dec.op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK) + && !check_bit(test_vector.ldpc_dec.op_flags, + RTE_BBDEV_LDPC_LLR_COMPRESSION)) + bler_function = bler_pmd_lcore_ldpc_dec; + else + return TEST_SKIPPED; + + rte_atomic16_set(&op_params->sync, SYNC_WAIT); + + /* Main core is set at first entry */ + t_params[0].dev_id = ad->dev_id; + t_params[0].lcore_id = rte_lcore_id(); + t_params[0].op_params = op_params; + t_params[0].queue_id = ad->queue_ids[used_cores++]; + t_params[0].iter_count = 0; + + RTE_LCORE_FOREACH_WORKER(lcore_id) { + if (used_cores >= num_lcores) + break; + + t_params[used_cores].dev_id = ad->dev_id; + t_params[used_cores].lcore_id = lcore_id; + t_params[used_cores].op_params = op_params; + t_params[used_cores].queue_id = ad->queue_ids[used_cores]; + t_params[used_cores].iter_count = 0; + + rte_eal_remote_launch(bler_function, + &t_params[used_cores++], lcore_id); + } + + rte_atomic16_set(&op_params->sync, SYNC_START); + ret = bler_function(&t_params[0]); + + /* Main core is always used */ + for (used_cores = 1; used_cores < num_lcores; used_cores++) + ret |= rte_eal_wait_lcore(t_params[used_cores].lcore_id); + + print_dec_bler(t_params, num_lcores); + + /* Return if test failed */ + if (ret) { + rte_free(t_params); + return ret; + } + + /* Function to print something here*/ + rte_free(t_params); + return ret; +} + /* * Test function that determines how long an enqueue + dequeue of a burst * takes on available lcores. @@ -2898,11 +3817,11 @@ throughput_test(struct active_device *ad, if (test_vector.op_type == RTE_BBDEV_OP_TURBO_DEC) throughput_function = throughput_intr_lcore_dec; else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_DEC) - throughput_function = throughput_intr_lcore_dec; + throughput_function = throughput_intr_lcore_ldpc_dec; else if (test_vector.op_type == RTE_BBDEV_OP_TURBO_ENC) throughput_function = throughput_intr_lcore_enc; else if (test_vector.op_type == RTE_BBDEV_OP_LDPC_ENC) - throughput_function = throughput_intr_lcore_enc; + throughput_function = throughput_intr_lcore_ldpc_enc; else throughput_function = throughput_intr_lcore_enc; @@ -2929,14 +3848,14 @@ throughput_test(struct active_device *ad, rte_atomic16_set(&op_params->sync, SYNC_WAIT); - /* Master core is set at first entry */ + /* Main core is set at first entry */ t_params[0].dev_id = ad->dev_id; t_params[0].lcore_id = rte_lcore_id(); t_params[0].op_params = op_params; t_params[0].queue_id = ad->queue_ids[used_cores++]; t_params[0].iter_count = 0; - RTE_LCORE_FOREACH_SLAVE(lcore_id) { + RTE_LCORE_FOREACH_WORKER(lcore_id) { if (used_cores >= num_lcores) break; @@ -2953,7 +3872,7 @@ throughput_test(struct active_device *ad, rte_atomic16_set(&op_params->sync, SYNC_START); ret = throughput_function(&t_params[0]); - /* Master core is always used */ + /* Main core is always used */ for (used_cores = 1; used_cores < num_lcores; used_cores++) ret |= rte_eal_wait_lcore(t_params[used_cores].lcore_id); @@ -2977,7 +3896,7 @@ throughput_test(struct active_device *ad, /* In interrupt TC we need to wait for the interrupt callback to deqeue * all pending operations. Skip waiting for queues which reported an * error using processing_status variable. - * Wait for master lcore operations. + * Wait for main lcore operations. */ tp = &t_params[0]; while ((rte_atomic16_read(&tp->nb_dequeued) < @@ -2990,7 +3909,7 @@ throughput_test(struct active_device *ad, tp->mbps /= TEST_REPETITIONS; ret |= (int)rte_atomic16_read(&tp->processing_status); - /* Wait for slave lcores operations */ + /* Wait for worker lcores operations */ for (used_cores = 1; used_cores < num_lcores; used_cores++) { tp = &t_params[used_cores]; @@ -3088,12 +4007,14 @@ latency_test_dec(struct rte_mempool *mempool, return i; } +/* Test case for latency/validation for LDPC Decoder */ static int latency_test_ldpc_dec(struct rte_mempool *mempool, struct test_buffers *bufs, struct rte_bbdev_dec_op *ref_op, int vector_mask, uint16_t dev_id, uint16_t queue_id, const uint16_t num_to_process, uint16_t burst_sz, - uint64_t *total_time, uint64_t *min_time, uint64_t *max_time) + uint64_t *total_time, uint64_t *min_time, uint64_t *max_time, + bool disable_et) { int ret = TEST_SUCCESS; uint16_t i, j, dequeued; @@ -3115,11 +4036,11 @@ latency_test_ldpc_dec(struct rte_mempool *mempool, "rte_bbdev_dec_op_alloc_bulk() failed"); /* For latency tests we need to disable early termination */ - if (check_bit(ref_op->ldpc_dec.op_flags, + if (disable_et && check_bit(ref_op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE)) ref_op->ldpc_dec.op_flags -= RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE; - ref_op->ldpc_dec.iter_max = 6; + ref_op->ldpc_dec.iter_max = get_iter_max(); ref_op->ldpc_dec.iter_count = ref_op->ldpc_dec.iter_max; if (test_vector.op_type != RTE_BBDEV_OP_NONE) @@ -3310,9 +4231,10 @@ latency_test_ldpc_enc(struct rte_mempool *mempool, return i; } +/* Common function for running validation and latency test cases */ static int -latency_test(struct active_device *ad, - struct test_op_params *op_params) +validation_latency_test(struct active_device *ad, + struct test_op_params *op_params, bool latency_flag) { int iter; uint16_t burst_sz = op_params->burst_sz; @@ -3337,7 +4259,11 @@ latency_test(struct active_device *ad, TEST_ASSERT_NOT_NULL(op_type_str, "Invalid op type: %u", op_type); printf("+ ------------------------------------------------------- +\n"); - printf("== test: validation/latency\ndev: %s, burst size: %u, num ops: %u, op type: %s\n", + if (latency_flag) + printf("== test: latency\ndev:"); + else + printf("== test: validation\ndev:"); + printf("%s, burst size: %u, num ops: %u, op type: %s\n", info.dev_name, burst_sz, num_to_process, op_type_str); if (op_type == RTE_BBDEV_OP_TURBO_DEC) @@ -3345,11 +4271,6 @@ latency_test(struct active_device *ad, op_params->ref_dec_op, op_params->vector_mask, ad->dev_id, queue_id, num_to_process, burst_sz, &total_time, &min_time, &max_time); - else if (op_type == RTE_BBDEV_OP_TURBO_ENC) - iter = latency_test_enc(op_params->mp, bufs, - op_params->ref_enc_op, ad->dev_id, queue_id, - num_to_process, burst_sz, &total_time, - &min_time, &max_time); else if (op_type == RTE_BBDEV_OP_LDPC_ENC) iter = latency_test_ldpc_enc(op_params->mp, bufs, op_params->ref_enc_op, ad->dev_id, queue_id, @@ -3359,13 +4280,14 @@ latency_test(struct active_device *ad, iter = latency_test_ldpc_dec(op_params->mp, bufs, op_params->ref_dec_op, op_params->vector_mask, ad->dev_id, queue_id, num_to_process, - burst_sz, &total_time, &min_time, &max_time); - else + burst_sz, &total_time, &min_time, &max_time, + latency_flag); + else /* RTE_BBDEV_OP_TURBO_ENC */ iter = latency_test_enc(op_params->mp, bufs, - op_params->ref_enc_op, - ad->dev_id, queue_id, - num_to_process, burst_sz, &total_time, - &min_time, &max_time); + op_params->ref_enc_op, + ad->dev_id, queue_id, + num_to_process, burst_sz, &total_time, + &min_time, &max_time); if (iter <= 0) return TEST_FAILED; @@ -3384,6 +4306,18 @@ latency_test(struct active_device *ad, return TEST_SUCCESS; } +static int +latency_test(struct active_device *ad, struct test_op_params *op_params) +{ + return validation_latency_test(ad, op_params, true); +} + +static int +validation_test(struct active_device *ad, struct test_op_params *op_params) +{ + return validation_latency_test(ad, op_params, false); +} + #ifdef RTE_BBDEV_OFFLOAD_COST static int get_bbdev_queue_stats(uint16_t dev_id, uint16_t queue_id, @@ -3459,15 +4393,15 @@ offload_latency_test_dec(struct rte_mempool *mempool, struct test_buffers *bufs, time_st->enq_acc_total_time += stats.acc_offload_cycles; /* give time for device to process ops */ - rte_delay_us(200); + rte_delay_us(WAIT_OFFLOAD_US); /* Start time meas for dequeue function offload latency */ deq_start_time = rte_rdtsc_precise(); /* Dequeue one operation */ do { deq += rte_bbdev_dequeue_dec_ops(dev_id, queue_id, - &ops_deq[deq], 1); - } while (unlikely(deq != 1)); + &ops_deq[deq], enq); + } while (unlikely(deq == 0)); deq_last_time = rte_rdtsc_precise() - deq_start_time; time_st->deq_max_time = RTE_MAX(time_st->deq_max_time, @@ -3550,15 +4484,15 @@ offload_latency_test_ldpc_dec(struct rte_mempool *mempool, time_st->enq_acc_total_time += stats.acc_offload_cycles; /* give time for device to process ops */ - rte_delay_us(200); + rte_delay_us(WAIT_OFFLOAD_US); /* Start time meas for dequeue function offload latency */ deq_start_time = rte_rdtsc_precise(); /* Dequeue one operation */ do { deq += rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id, - &ops_deq[deq], 1); - } while (unlikely(deq != 1)); + &ops_deq[deq], enq); + } while (unlikely(deq == 0)); deq_last_time = rte_rdtsc_precise() - deq_start_time; time_st->deq_max_time = RTE_MAX(time_st->deq_max_time, @@ -3638,15 +4572,15 @@ offload_latency_test_enc(struct rte_mempool *mempool, struct test_buffers *bufs, time_st->enq_acc_total_time += stats.acc_offload_cycles; /* give time for device to process ops */ - rte_delay_us(200); + rte_delay_us(WAIT_OFFLOAD_US); /* Start time meas for dequeue function offload latency */ deq_start_time = rte_rdtsc_precise(); /* Dequeue one operation */ do { deq += rte_bbdev_dequeue_enc_ops(dev_id, queue_id, - &ops_deq[deq], 1); - } while (unlikely(deq != 1)); + &ops_deq[deq], enq); + } while (unlikely(deq == 0)); deq_last_time = rte_rdtsc_precise() - deq_start_time; time_st->deq_max_time = RTE_MAX(time_st->deq_max_time, @@ -3721,15 +4655,15 @@ offload_latency_test_ldpc_enc(struct rte_mempool *mempool, time_st->enq_acc_total_time += stats.acc_offload_cycles; /* give time for device to process ops */ - rte_delay_us(200); + rte_delay_us(WAIT_OFFLOAD_US); /* Start time meas for dequeue function offload latency */ deq_start_time = rte_rdtsc_precise(); /* Dequeue one operation */ do { deq += rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, - &ops_deq[deq], 1); - } while (unlikely(deq != 1)); + &ops_deq[deq], enq); + } while (unlikely(deq == 0)); deq_last_time = rte_rdtsc_precise() - deq_start_time; time_st->deq_max_time = RTE_MAX(time_st->deq_max_time, @@ -3851,6 +4785,23 @@ offload_cost_test(struct active_device *ad, (double)(time_st.deq_max_time * 1000000) / rte_get_tsc_hz()); + struct rte_bbdev_stats stats = {0}; + get_bbdev_queue_stats(ad->dev_id, queue_id, &stats); + if (op_type != RTE_BBDEV_OP_LDPC_DEC) { + TEST_ASSERT_SUCCESS(stats.enqueued_count != num_to_process, + "Mismatch in enqueue count %10"PRIu64" %d", + stats.enqueued_count, num_to_process); + TEST_ASSERT_SUCCESS(stats.dequeued_count != num_to_process, + "Mismatch in dequeue count %10"PRIu64" %d", + stats.dequeued_count, num_to_process); + } + TEST_ASSERT_SUCCESS(stats.enqueue_err_count != 0, + "Enqueue count Error %10"PRIu64"", + stats.enqueue_err_count); + TEST_ASSERT_SUCCESS(stats.dequeue_err_count != 0, + "Dequeue count Error (%10"PRIu64"", + stats.dequeue_err_count); + return TEST_SUCCESS; #endif } @@ -3860,7 +4811,7 @@ static int offload_latency_empty_q_test_dec(uint16_t dev_id, uint16_t queue_id, const uint16_t num_to_process, uint16_t burst_sz, uint64_t *deq_total_time, uint64_t *deq_min_time, - uint64_t *deq_max_time) + uint64_t *deq_max_time, const enum rte_bbdev_op_type op_type) { int i, deq_total; struct rte_bbdev_dec_op *ops[MAX_BURST]; @@ -3874,7 +4825,12 @@ offload_latency_empty_q_test_dec(uint16_t dev_id, uint16_t queue_id, if (unlikely(num_to_process - deq_total < burst_sz)) burst_sz = num_to_process - deq_total; - rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops, burst_sz); + if (op_type == RTE_BBDEV_OP_LDPC_DEC) + rte_bbdev_dequeue_ldpc_dec_ops(dev_id, queue_id, ops, + burst_sz); + else + rte_bbdev_dequeue_dec_ops(dev_id, queue_id, ops, + burst_sz); deq_last_time = rte_rdtsc_precise() - deq_start_time; *deq_max_time = RTE_MAX(*deq_max_time, deq_last_time); @@ -3889,7 +4845,7 @@ static int offload_latency_empty_q_test_enc(uint16_t dev_id, uint16_t queue_id, const uint16_t num_to_process, uint16_t burst_sz, uint64_t *deq_total_time, uint64_t *deq_min_time, - uint64_t *deq_max_time) + uint64_t *deq_max_time, const enum rte_bbdev_op_type op_type) { int i, deq_total; struct rte_bbdev_enc_op *ops[MAX_BURST]; @@ -3902,7 +4858,12 @@ offload_latency_empty_q_test_enc(uint16_t dev_id, uint16_t queue_id, if (unlikely(num_to_process - deq_total < burst_sz)) burst_sz = num_to_process - deq_total; - rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops, burst_sz); + if (op_type == RTE_BBDEV_OP_LDPC_ENC) + rte_bbdev_dequeue_ldpc_enc_ops(dev_id, queue_id, ops, + burst_sz); + else + rte_bbdev_dequeue_enc_ops(dev_id, queue_id, ops, + burst_sz); deq_last_time = rte_rdtsc_precise() - deq_start_time; *deq_max_time = RTE_MAX(*deq_max_time, deq_last_time); @@ -3912,6 +4873,7 @@ offload_latency_empty_q_test_enc(uint16_t dev_id, uint16_t queue_id, return i; } + #endif static int @@ -3949,14 +4911,15 @@ offload_latency_empty_q_test(struct active_device *ad, printf("== test: offload latency empty dequeue\ndev: %s, burst size: %u, num ops: %u, op type: %s\n", info.dev_name, burst_sz, num_to_process, op_type_str); - if (op_type == RTE_BBDEV_OP_TURBO_DEC) + if (op_type == RTE_BBDEV_OP_TURBO_DEC || + op_type == RTE_BBDEV_OP_LDPC_DEC) iter = offload_latency_empty_q_test_dec(ad->dev_id, queue_id, num_to_process, burst_sz, &deq_total_time, - &deq_min_time, &deq_max_time); + &deq_min_time, &deq_max_time, op_type); else iter = offload_latency_empty_q_test_enc(ad->dev_id, queue_id, num_to_process, burst_sz, &deq_total_time, - &deq_min_time, &deq_max_time); + &deq_min_time, &deq_max_time, op_type); if (iter <= 0) return TEST_FAILED; @@ -3976,6 +4939,12 @@ offload_latency_empty_q_test(struct active_device *ad, #endif } +static int +bler_tc(void) +{ + return run_test_case(bler_test); +} + static int throughput_tc(void) { @@ -4000,12 +4969,28 @@ latency_tc(void) return run_test_case(latency_test); } +static int +validation_tc(void) +{ + return run_test_case(validation_test); +} + static int interrupt_tc(void) { return run_test_case(throughput_test); } +static struct unit_test_suite bbdev_bler_testsuite = { + .suite_name = "BBdev BLER Tests", + .setup = testsuite_setup, + .teardown = testsuite_teardown, + .unit_test_cases = { + TEST_CASE_ST(ut_setup, ut_teardown, bler_tc), + TEST_CASES_END() /**< NULL terminate unit test array */ + } +}; + static struct unit_test_suite bbdev_throughput_testsuite = { .suite_name = "BBdev Throughput Tests", .setup = testsuite_setup, @@ -4021,7 +5006,7 @@ static struct unit_test_suite bbdev_validation_testsuite = { .setup = testsuite_setup, .teardown = testsuite_teardown, .unit_test_cases = { - TEST_CASE_ST(ut_setup, ut_teardown, latency_tc), + TEST_CASE_ST(ut_setup, ut_teardown, validation_tc), TEST_CASES_END() /**< NULL terminate unit test array */ } }; @@ -4057,6 +5042,7 @@ static struct unit_test_suite bbdev_interrupt_testsuite = { } }; +REGISTER_TEST_COMMAND(bler, bbdev_bler_testsuite); REGISTER_TEST_COMMAND(throughput, bbdev_throughput_testsuite); REGISTER_TEST_COMMAND(validation, bbdev_validation_testsuite); REGISTER_TEST_COMMAND(latency, bbdev_latency_testsuite);