X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=aversive%2Fparts%2FAT90S4433.h;fp=aversive%2Fparts%2FAT90S4433.h;h=0000000000000000000000000000000000000000;hb=57895b3bb2fe0582c589685b7df34f3968b346ec;hp=dd2a1afeeaf302494dddbc3a5830f7fb3a8643a4;hpb=9a9b64112aee5ab26398b46cb13b7e49c292a355;p=protos%2Fxbee-avr.git diff --git a/aversive/parts/AT90S4433.h b/aversive/parts/AT90S4433.h deleted file mode 100644 index dd2a1af..0000000 --- a/aversive/parts/AT90S4433.h +++ /dev/null @@ -1,478 +0,0 @@ -/* - * Copyright Droids Corporation, Microb Technology, Eirbot (2009) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Revision : $Id $ - * - */ - -/* WARNING : this file is automatically generated by scripts. - * You should not edit it. If you find something wrong in it, - * write to zer0@droids-corp.org */ - - -/* prescalers timer 0 */ -#define TIMER0_PRESCALER_DIV_0 0 -#define TIMER0_PRESCALER_DIV_1 1 -#define TIMER0_PRESCALER_DIV_8 2 -#define TIMER0_PRESCALER_DIV_64 3 -#define TIMER0_PRESCALER_DIV_256 4 -#define TIMER0_PRESCALER_DIV_1024 5 -#define TIMER0_PRESCALER_DIV_FALL 6 -#define TIMER0_PRESCALER_DIV_RISE 7 - -#define TIMER0_PRESCALER_REG_0 0 -#define TIMER0_PRESCALER_REG_1 1 -#define TIMER0_PRESCALER_REG_2 8 -#define TIMER0_PRESCALER_REG_3 64 -#define TIMER0_PRESCALER_REG_4 256 -#define TIMER0_PRESCALER_REG_5 1024 -#define TIMER0_PRESCALER_REG_6 -1 -#define TIMER0_PRESCALER_REG_7 -2 - -/* prescalers timer 1 */ -#define TIMER1_PRESCALER_DIV_0 0 -#define TIMER1_PRESCALER_DIV_1 1 -#define TIMER1_PRESCALER_DIV_8 2 -#define TIMER1_PRESCALER_DIV_64 3 -#define TIMER1_PRESCALER_DIV_256 4 -#define TIMER1_PRESCALER_DIV_1024 5 -#define TIMER1_PRESCALER_DIV_FALL 6 -#define TIMER1_PRESCALER_DIV_RISE 7 - -#define TIMER1_PRESCALER_REG_0 0 -#define TIMER1_PRESCALER_REG_1 1 -#define TIMER1_PRESCALER_REG_2 8 -#define TIMER1_PRESCALER_REG_3 64 -#define TIMER1_PRESCALER_REG_4 256 -#define TIMER1_PRESCALER_REG_5 1024 -#define TIMER1_PRESCALER_REG_6 -1 -#define TIMER1_PRESCALER_REG_7 -2 - - -/* available timers */ -#define TIMER0_AVAILABLE -#define TIMER1_AVAILABLE - -/* overflow interrupt number */ -#define SIG_OVERFLOW0_NUM 0 -#define SIG_OVERFLOW1_NUM 1 -#define SIG_OVERFLOW_TOTAL_NUM 2 - -/* output compare interrupt number */ -#define SIG_OUTPUT_COMPARE1_NUM 0 -#define SIG_OUTPUT_COMPARE_TOTAL_NUM 1 - -/* Pwm nums */ -#define PWM1_NUM 0 -#define PWM_TOTAL_NUM 1 - -/* input capture interrupt number */ -#define SIG_INPUT_CAPTURE1_NUM 0 -#define SIG_INPUT_CAPTURE_TOTAL_NUM 1 - - -/* WDTCR */ -#define WDP0_REG WDTCR -#define WDP1_REG WDTCR -#define WDP2_REG WDTCR -#define WDE_REG WDTCR -#define WDTOE_REG WDTCR - -/* GIMSK */ -#define INT0_REG GIMSK -#define INT1_REG GIMSK - -/* ADMUX */ -#define MUX0_REG ADMUX -#define MUX1_REG ADMUX -#define MUX2_REG ADMUX -#define ADCBG_REG ADMUX - -/* TCCR0 */ -#define CS00_REG TCCR0 -#define CS01_REG TCCR0 -#define CS02_REG TCCR0 - -/* SREG */ -#define C_REG SREG -#define Z_REG SREG -#define N_REG SREG -#define V_REG SREG -#define S_REG SREG -#define H_REG SREG -#define T_REG SREG -#define I_REG SREG - -/* DDRB */ -#define DDB0_REG DDRB -#define DDB1_REG DDRB -#define DDB2_REG DDRB -#define DDB3_REG DDRB -#define DDB4_REG DDRB -#define DDB5_REG DDRB - -/* EEDR */ -#define EEDR0_REG EEDR -#define EEDR1_REG EEDR -#define EEDR2_REG EEDR -#define EEDR3_REG EEDR -#define EEDR4_REG EEDR -#define EEDR5_REG EEDR -#define EEDR6_REG EEDR -#define EEDR7_REG EEDR - -/* DDRC */ -#define DDC0_REG DDRC -#define DDC1_REG DDRC -#define DDC2_REG DDRC -#define DDC3_REG DDRC -#define DDC4_REG DDRC -#define DDC5_REG DDRC - -/* PIND */ -#define PIND0_REG PIND -#define PIND1_REG PIND -#define PIND2_REG PIND -#define PIND3_REG PIND -#define PIND4_REG PIND -#define PIND5_REG PIND -#define PIND6_REG PIND -#define PIND7_REG PIND - -/* TCCR1A */ -#define PWM10_REG TCCR1A -#define PWM11_REG TCCR1A -#define COM10_REG TCCR1A -#define COM11_REG TCCR1A - -/* DDRD */ -#define DDD0_REG DDRD -#define DDD1_REG DDRD -#define DDD2_REG DDRD -#define DDD3_REG DDRD -#define DDD4_REG DDRD -#define DDD5_REG DDRD -#define DDD6_REG DDRD -#define DDD7_REG DDRD - -/* TCCR1B */ -#define CS10_REG TCCR1B -#define CS11_REG TCCR1B -#define CS12_REG TCCR1B -#define CTC1_REG TCCR1B -#define ICES1_REG TCCR1B -#define ICNC1_REG TCCR1B - -/* GIFR */ -#define INTF0_REG GIFR -#define INTF1_REG GIFR - -/* TIMSK */ -#define TOIE0_REG TIMSK -#define TICIE1_REG TIMSK -#define OCIE1_REG TIMSK -#define TOIE1_REG TIMSK - -/* SPDR */ -#define SPDR0_REG SPDR -#define SPDR1_REG SPDR -#define SPDR2_REG SPDR -#define SPDR3_REG SPDR -#define SPDR4_REG SPDR -#define SPDR5_REG SPDR -#define SPDR6_REG SPDR -#define SPDR7_REG SPDR - -/* UBRRHI */ -#define UBRRHI0_REG UBRRHI -#define UBRRHI1_REG UBRRHI -#define UBRRHI2_REG UBRRHI -#define UBRRHI3_REG UBRRHI - -/* SPSR */ -#define WCOL_REG SPSR -#define SPIF_REG SPSR - -/* ACSR */ -#define ACIS0_REG ACSR -#define ACIS1_REG ACSR -#define ACIC_REG ACSR -#define ACIE_REG ACSR -#define ACI_REG ACSR -#define ACO_REG ACSR -#define AINBG_REG ACSR -#define ACD_REG ACSR - -/* ICR1H */ -#define ICR1H0_REG ICR1H -#define ICR1H1_REG ICR1H -#define ICR1H2_REG ICR1H -#define ICR1H3_REG ICR1H -#define ICR1H4_REG ICR1H -#define ICR1H5_REG ICR1H -#define ICR1H6_REG ICR1H -#define ICR1H7_REG ICR1H - -/* UCSRA */ -#define MPCM_REG UCSRA -#define OR_REG UCSRA -#define FE_REG UCSRA -#define UDRE_REG UCSRA -#define TXC_REG UCSRA -#define RXC_REG UCSRA - -/* UCSRB */ -#define TXB8_REG UCSRB -#define RXB8_REG UCSRB -#define CHR9_REG UCSRB -#define TXEN_REG UCSRB -#define RXEN_REG UCSRB -#define UDRIE_REG UCSRB -#define TXCIE_REG UCSRB -#define RXCIE_REG UCSRB - -/* ICR1L */ -#define ICR1L0_REG ICR1L -#define ICR1L1_REG ICR1L -#define ICR1L2_REG ICR1L -#define ICR1L3_REG ICR1L -#define ICR1L4_REG ICR1L -#define ICR1L5_REG ICR1L -#define ICR1L6_REG ICR1L -#define ICR1L7_REG ICR1L - -/* UBRR */ -#define UBRR0_REG UBRR -#define UBRR1_REG UBRR -#define UBRR2_REG UBRR -#define UBRR3_REG UBRR -#define UBRR4_REG UBRR -#define UBRR5_REG UBRR -#define UBRR6_REG UBRR -#define UBRR7_REG UBRR - -/* ADCL */ -#define ADC0_REG ADCL -#define ADC1_REG ADCL -#define ADC2_REG ADCL -#define ADC3_REG ADCL -#define ADC4_REG ADCL -#define ADC5_REG ADCL -#define ADC6_REG ADCL -#define ADC7_REG ADCL - -/* MCUSR */ -#define PORF_REG MCUSR -#define EXTRF_REG MCUSR -#define BORF_REG MCUSR -#define WDRF_REG MCUSR - -/* EECR */ -#define EERE_REG EECR -#define EEWE_REG EECR -#define EEMWE_REG EECR -#define EERIE_REG EECR - -/* TCNT1L */ -#define TCNT1L0_REG TCNT1L -#define TCNT1L1_REG TCNT1L -#define TCNT1L2_REG TCNT1L -#define TCNT1L3_REG TCNT1L -#define TCNT1L4_REG TCNT1L -#define TCNT1L5_REG TCNT1L -#define TCNT1L6_REG TCNT1L -#define TCNT1L7_REG TCNT1L - -/* PORTB */ -#define PORTB0_REG PORTB -#define PORTB1_REG PORTB -#define PORTB2_REG PORTB -#define PORTB3_REG PORTB -#define PORTB4_REG PORTB -#define PORTB5_REG PORTB - -/* PORTD */ -#define PORTD0_REG PORTD -#define PORTD1_REG PORTD -#define PORTD2_REG PORTD -#define PORTD3_REG PORTD -#define PORTD4_REG PORTD -#define PORTD5_REG PORTD -#define PORTD6_REG PORTD -#define PORTD7_REG PORTD - -/* EEAR */ -#define EEAR0_REG EEAR -#define EEAR1_REG EEAR -#define EEAR2_REG EEAR -#define EEAR3_REG EEAR -#define EEAR4_REG EEAR -#define EEAR5_REG EEAR -#define EEAR6_REG EEAR -#define EEAR7_REG EEAR - -/* TCNT1H */ -#define TCNT1H0_REG TCNT1H -#define TCNT1H1_REG TCNT1H -#define TCNT1H2_REG TCNT1H -#define TCNT1H3_REG TCNT1H -#define TCNT1H4_REG TCNT1H -#define TCNT1H5_REG TCNT1H -#define TCNT1H6_REG TCNT1H -#define TCNT1H7_REG TCNT1H - -/* PORTC */ -#define PORTC0_REG PORTC -#define PORTC1_REG PORTC -#define PORTC2_REG PORTC -#define PORTC3_REG PORTC -#define PORTC4_REG PORTC -#define PORTC5_REG PORTC - -/* ADCH */ -#define ADC8_REG ADCH -#define ADC9_REG ADCH - -/* TCNT0 */ -#define TCNT00_REG TCNT0 -#define TCNT01_REG TCNT0 -#define TCNT02_REG TCNT0 -#define TCNT03_REG TCNT0 -#define TCNT04_REG TCNT0 -#define TCNT05_REG TCNT0 -#define TCNT06_REG TCNT0 -#define TCNT07_REG TCNT0 - -/* TIFR */ -#define TOV0_REG TIFR -#define ICF1_REG TIFR -#define OCF1_REG TIFR -#define TOV1_REG TIFR - -/* UDR */ -#define UDR0_REG UDR -#define UDR1_REG UDR -#define UDR2_REG UDR -#define UDR3_REG UDR -#define UDR4_REG UDR -#define UDR5_REG UDR -#define UDR6_REG UDR -#define UDR7_REG UDR - -/* OCR1L */ -#define OCR1AL0_REG OCR1L -#define OCR1AL1_REG OCR1L -#define OCR1AL2_REG OCR1L -#define OCR1AL3_REG OCR1L -#define OCR1AL4_REG OCR1L -#define OCR1AL5_REG OCR1L -#define OCR1AL6_REG OCR1L -#define OCR1AL7_REG OCR1L - -/* ADCSR */ -#define ADPS0_REG ADCSR -#define ADPS1_REG ADCSR -#define ADPS2_REG ADCSR -#define ADIE_REG ADCSR -#define ADIF_REG ADCSR -#define ADFR_REG ADCSR -#define ADSC_REG ADCSR -#define ADEN_REG ADCSR - -/* OCR1H */ -#define OCR1AH0_REG OCR1H -#define OCR1AH1_REG OCR1H -#define OCR1AH2_REG OCR1H -#define OCR1AH3_REG OCR1H -#define OCR1AH4_REG OCR1H -#define OCR1AH5_REG OCR1H -#define OCR1AH6_REG OCR1H -#define OCR1AH7_REG OCR1H - -/* PINC */ -#define PINC0_REG PINC -#define PINC1_REG PINC -#define PINC2_REG PINC -#define PINC3_REG PINC -#define PINC4_REG PINC -#define PINC5_REG PINC - -/* PINB */ -#define PINB0_REG PINB -#define PINB1_REG PINB -#define PINB2_REG PINB -#define PINB3_REG PINB -#define PINB4_REG PINB -#define PINB5_REG PINB - -/* SP */ -#define SP0_REG SP -#define SP1_REG SP -#define SP2_REG SP -#define SP3_REG SP -#define SP4_REG SP -#define SP5_REG SP -#define SP6_REG SP -#define SP7_REG SP - -/* MCUCR */ -#define ISC00_REG MCUCR -#define ISC01_REG MCUCR -#define ISC10_REG MCUCR -#define ISC11_REG MCUCR -#define SM_REG MCUCR -#define SE_REG MCUCR - -/* SPCR */ -#define SPR0_REG SPCR -#define SPR1_REG SPCR -#define CPHA_REG SPCR -#define CPOL_REG SPCR -#define MSTR_REG SPCR -#define DORD_REG SPCR -#define SPE_REG SPCR -#define SPIE_REG SPCR - -/* pins mapping */ -#define ADC0_PORT PORTC -#define ADC0_BIT 0 - -#define ADC1_PORT PORTC -#define ADC1_BIT 1 - -#define ADC2_PORT PORTC -#define ADC2_BIT 2 - -#define ADC3_PORT PORTC -#define ADC3_BIT 3 - -#define ADC4_PORT PORTC -#define ADC4_BIT 4 - -#define ADC5_PORT PORTC -#define ADC5_BIT 5 - -#define RXD_PORT PORTD -#define RXD_BIT 0 - -#define TXD_PORT PORTD -#define TXD_BIT 1 - -#define INT0_PORT PORTD -#define INT0_BIT 2 - -