X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=aversive%2Fparts%2FATmega103comp.h;fp=aversive%2Fparts%2FATmega103comp.h;h=0000000000000000000000000000000000000000;hb=57895b3bb2fe0582c589685b7df34f3968b346ec;hp=57b5ed6914434f867310dca673642a555a532e1b;hpb=9a9b64112aee5ab26398b46cb13b7e49c292a355;p=protos%2Fxbee-avr.git diff --git a/aversive/parts/ATmega103comp.h b/aversive/parts/ATmega103comp.h deleted file mode 100644 index 57b5ed6..0000000 --- a/aversive/parts/ATmega103comp.h +++ /dev/null @@ -1,902 +0,0 @@ -/* - * Copyright Droids Corporation, Microb Technology, Eirbot (2009) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Revision : $Id $ - * - */ - -/* WARNING : this file is automatically generated by scripts. - * You should not edit it. If you find something wrong in it, - * write to zer0@droids-corp.org */ - - -/* prescalers timer 0 */ -#define TIMER0_PRESCALER_DIV_0 0 -#define TIMER0_PRESCALER_DIV_1 1 -#define TIMER0_PRESCALER_DIV_8 2 -#define TIMER0_PRESCALER_DIV_32 3 -#define TIMER0_PRESCALER_DIV_64 4 -#define TIMER0_PRESCALER_DIV_128 5 -#define TIMER0_PRESCALER_DIV_256 6 -#define TIMER0_PRESCALER_DIV_1024 7 - -#define TIMER0_PRESCALER_REG_0 0 -#define TIMER0_PRESCALER_REG_1 1 -#define TIMER0_PRESCALER_REG_2 8 -#define TIMER0_PRESCALER_REG_3 32 -#define TIMER0_PRESCALER_REG_4 64 -#define TIMER0_PRESCALER_REG_5 128 -#define TIMER0_PRESCALER_REG_6 256 -#define TIMER0_PRESCALER_REG_7 1024 - -/* prescalers timer 1 */ -#define TIMER1_PRESCALER_DIV_0 0 -#define TIMER1_PRESCALER_DIV_1 1 -#define TIMER1_PRESCALER_DIV_8 2 -#define TIMER1_PRESCALER_DIV_64 3 -#define TIMER1_PRESCALER_DIV_256 4 -#define TIMER1_PRESCALER_DIV_1024 5 -#define TIMER1_PRESCALER_DIV_FALL 6 -#define TIMER1_PRESCALER_DIV_RISE 7 - -#define TIMER1_PRESCALER_REG_0 0 -#define TIMER1_PRESCALER_REG_1 1 -#define TIMER1_PRESCALER_REG_2 8 -#define TIMER1_PRESCALER_REG_3 64 -#define TIMER1_PRESCALER_REG_4 256 -#define TIMER1_PRESCALER_REG_5 1024 -#define TIMER1_PRESCALER_REG_6 -1 -#define TIMER1_PRESCALER_REG_7 -2 - -/* prescalers timer 2 */ -#define TIMER2_PRESCALER_DIV_0 0 -#define TIMER2_PRESCALER_DIV_1 1 -#define TIMER2_PRESCALER_DIV_8 2 -#define TIMER2_PRESCALER_DIV_64 3 -#define TIMER2_PRESCALER_DIV_256 4 -#define TIMER2_PRESCALER_DIV_1024 5 -#define TIMER2_PRESCALER_DIV_FALL 6 -#define TIMER2_PRESCALER_DIV_RISE 7 - -#define TIMER2_PRESCALER_REG_0 0 -#define TIMER2_PRESCALER_REG_1 1 -#define TIMER2_PRESCALER_REG_2 8 -#define TIMER2_PRESCALER_REG_3 64 -#define TIMER2_PRESCALER_REG_4 256 -#define TIMER2_PRESCALER_REG_5 1024 -#define TIMER2_PRESCALER_REG_6 -1 -#define TIMER2_PRESCALER_REG_7 -2 - - -/* available timers */ -#define TIMER0_AVAILABLE -#define TIMER1_AVAILABLE -#define TIMER1A_AVAILABLE -#define TIMER1B_AVAILABLE -#define TIMER1C_AVAILABLE -#define TIMER2_AVAILABLE -#define TIMER3_AVAILABLE -#define TIMER3A_AVAILABLE -#define TIMER3B_AVAILABLE -#define TIMER3C_AVAILABLE - -/* overflow interrupt number */ -#define SIG_OVERFLOW0_NUM 0 -#define SIG_OVERFLOW1_NUM 1 -#define SIG_OVERFLOW2_NUM 2 -#define SIG_OVERFLOW3_NUM 3 -#define SIG_OVERFLOW_TOTAL_NUM 4 - -/* output compare interrupt number */ -#define SIG_OUTPUT_COMPARE0_NUM 0 -#define SIG_OUTPUT_COMPARE1A_NUM 1 -#define SIG_OUTPUT_COMPARE1B_NUM 2 -#define SIG_OUTPUT_COMPARE1C_NUM 3 -#define SIG_OUTPUT_COMPARE2_NUM 4 -#define SIG_OUTPUT_COMPARE3A_NUM 5 -#define SIG_OUTPUT_COMPARE3B_NUM 6 -#define SIG_OUTPUT_COMPARE3C_NUM 7 -#define SIG_OUTPUT_COMPARE_TOTAL_NUM 8 - -/* Pwm nums */ -#define PWM0_NUM 0 -#define PWM1A_NUM 1 -#define PWM1B_NUM 2 -#define PWM1C_NUM 3 -#define PWM2_NUM 4 -#define PWM3A_NUM 5 -#define PWM3B_NUM 6 -#define PWM3C_NUM 7 -#define PWM_TOTAL_NUM 8 - -/* input capture interrupt number */ -#define SIG_INPUT_CAPTURE1_NUM 0 -#define SIG_INPUT_CAPTURE3_NUM 1 -#define SIG_INPUT_CAPTURE_TOTAL_NUM 2 - - -/* WDTCR */ -#define WDP0_REG WDTCR -#define WDP1_REG WDTCR -#define WDP2_REG WDTCR -#define WDE_REG WDTCR -#define WDCE_REG WDTCR - -/* ICR1H */ -#define ICR1H0_REG ICR1H -#define ICR1H1_REG ICR1H -#define ICR1H2_REG ICR1H -#define ICR1H3_REG ICR1H -#define ICR1H4_REG ICR1H -#define ICR1H5_REG ICR1H -#define ICR1H6_REG ICR1H -#define ICR1H7_REG ICR1H - -/* ADMUX */ -#define MUX0_REG ADMUX -#define MUX1_REG ADMUX -#define MUX2_REG ADMUX -#define MUX3_REG ADMUX -#define MUX4_REG ADMUX -#define ADLAR_REG ADMUX -#define REFS0_REG ADMUX -#define REFS1_REG ADMUX - -/* TCCR0 */ -#define CS00_REG TCCR0 -#define CS01_REG TCCR0 -#define CS02_REG TCCR0 -#define CTC0_REG TCCR0 -#define COM00_REG TCCR0 -#define COM01_REG TCCR0 -#define PWM0_REG TCCR0 - -/* SREG */ -#define C_REG SREG -#define Z_REG SREG -#define N_REG SREG -#define V_REG SREG -#define S_REG SREG -#define H_REG SREG -#define T_REG SREG -#define I_REG SREG - -/* DDRB */ -#define DDB0_REG DDRB -#define DDB1_REG DDRB -#define DDB2_REG DDRB -#define DDB3_REG DDRB -#define DDB4_REG DDRB -#define DDB5_REG DDRB -#define DDB6_REG DDRB -#define DDB7_REG DDRB - -/* XDIV */ -#define XDIV0_REG XDIV -#define XDIV1_REG XDIV -#define XDIV2_REG XDIV -#define XDIV3_REG XDIV -#define XDIV4_REG XDIV -#define XDIV5_REG XDIV -#define XDIV6_REG XDIV -#define XDIVEN_REG XDIV - -/* EEDR */ -#define EEDR0_REG EEDR -#define EEDR1_REG EEDR -#define EEDR2_REG EEDR -#define EEDR3_REG EEDR -#define EEDR4_REG EEDR -#define EEDR5_REG EEDR -#define EEDR6_REG EEDR -#define EEDR7_REG EEDR - -/* DDRE */ -#define DDE0_REG DDRE -#define DDE1_REG DDRE -#define DDE2_REG DDRE -#define DDE3_REG DDRE -#define DDE4_REG DDRE -#define DDE5_REG DDRE -#define DDE6_REG DDRE -#define DDE7_REG DDRE - -/* DDRA */ -#define DDA0_REG DDRA -#define DDA1_REG DDRA -#define DDA2_REG DDRA -#define DDA3_REG DDRA -#define DDA4_REG DDRA -#define DDA5_REG DDRA -#define DDA6_REG DDRA -#define DDA7_REG DDRA - -/* TCCR1A */ -#define PWM10_REG TCCR1A -#define PWM11_REG TCCR1A -#define COM1B0_REG TCCR1A -#define COM1B1_REG TCCR1A -#define COM1A0_REG TCCR1A -#define COM1A1_REG TCCR1A - -/* DDRD */ -#define DDD0_REG DDRD -#define DDD1_REG DDRD -#define DDD2_REG DDRD -#define DDD3_REG DDRD -#define DDD4_REG DDRD -#define DDD5_REG DDRD -#define DDD6_REG DDRD -#define DDD7_REG DDRD - -/* TCCR1B */ -#define CS10_REG TCCR1B -#define CS11_REG TCCR1B -#define CS12_REG TCCR1B -#define CTC1_REG TCCR1B -#define ICES1_REG TCCR1B -#define ICNC1_REG TCCR1B - -/* TIMSK */ -#define TOIE2_REG TIMSK -#define OCIE2_REG TIMSK -#define TOIE0_REG TIMSK -#define OCIE0_REG TIMSK -#define TOIE1_REG TIMSK -#define OCIE1B_REG TIMSK -#define OCIE1A_REG TIMSK -#define TICIE1_REG TIMSK - -/* EIMSK */ -#define INT0_REG EIMSK -#define INT1_REG EIMSK -#define INT2_REG EIMSK -#define INT3_REG EIMSK -#define INT4_REG EIMSK -#define INT5_REG EIMSK -#define INT6_REG EIMSK -#define INT7_REG EIMSK - -/* RAMPZ */ -#define RAMPZ0_REG RAMPZ - -/* SPDR */ -#define SPDR0_REG SPDR -#define SPDR1_REG SPDR -#define SPDR2_REG SPDR -#define SPDR3_REG SPDR -#define SPDR4_REG SPDR -#define SPDR5_REG SPDR -#define SPDR6_REG SPDR -#define SPDR7_REG SPDR - -/* ADCSR */ -#define ADPS0_REG ADCSR -#define ADPS1_REG ADCSR -#define ADPS2_REG ADCSR -#define ADIE_REG ADCSR -#define ADIF_REG ADCSR -#define ADFR_REG ADCSR -#define ADSC_REG ADCSR -#define ADEN_REG ADCSR - -/* SFIOR */ -#define ACME_REG SFIOR -#define PSR321_REG SFIOR -#define PSR0_REG SFIOR -#define PUD_REG SFIOR -#define TSM_REG SFIOR - -/* UDR0 */ -#define UDR00_REG UDR0 -#define UDR01_REG UDR0 -#define UDR02_REG UDR0 -#define UDR03_REG UDR0 -#define UDR04_REG UDR0 -#define UDR05_REG UDR0 -#define UDR06_REG UDR0 -#define UDR07_REG UDR0 - -/* SPH */ -#define SP8_REG SPH -#define SP9_REG SPH -#define SP10_REG SPH -#define SP11_REG SPH -#define SP12_REG SPH -#define SP13_REG SPH -#define SP14_REG SPH -#define SP15_REG SPH - -/* OCR1BL */ -#define OCR1BL0_REG OCR1BL -#define OCR1BL1_REG OCR1BL -#define OCR1BL2_REG OCR1BL -#define OCR1BL3_REG OCR1BL -#define OCR1BL4_REG OCR1BL -#define OCR1BL5_REG OCR1BL -#define OCR1BL6_REG OCR1BL -#define OCR1BL7_REG OCR1BL - -/* SPL */ -#define SP0_REG SPL -#define SP1_REG SPL -#define SP2_REG SPL -#define SP3_REG SPL -#define SP4_REG SPL -#define SP5_REG SPL -#define SP6_REG SPL -#define SP7_REG SPL - -/* OCR1BH */ -#define OCR1BH0_REG OCR1BH -#define OCR1BH1_REG OCR1BH -#define OCR1BH2_REG OCR1BH -#define OCR1BH3_REG OCR1BH -#define OCR1BH4_REG OCR1BH -#define OCR1BH5_REG OCR1BH -#define OCR1BH6_REG OCR1BH -#define OCR1BH7_REG OCR1BH - -/* PIND */ -#define PIND0_REG PIND -#define PIND1_REG PIND -#define PIND2_REG PIND -#define PIND3_REG PIND -#define PIND4_REG PIND -#define PIND5_REG PIND -#define PIND6_REG PIND -#define PIND7_REG PIND - -/* ICR1L */ -#define ICR1L0_REG ICR1L -#define ICR1L1_REG ICR1L -#define ICR1L2_REG ICR1L -#define ICR1L3_REG ICR1L -#define ICR1L4_REG ICR1L -#define ICR1L5_REG ICR1L -#define ICR1L6_REG ICR1L -#define ICR1L7_REG ICR1L - -/* SPSR */ -#define SPI2X_REG SPSR -#define WCOL_REG SPSR -#define SPIF_REG SPSR - -/* ADCL */ -#define ADCL0_REG ADCL -#define ADCL1_REG ADCL -#define ADCL2_REG ADCL -#define ADCL3_REG ADCL -#define ADCL4_REG ADCL -#define ADCL5_REG ADCL -#define ADCL6_REG ADCL -#define ADCL7_REG ADCL - -/* ACSR */ -#define ACIS0_REG ACSR -#define ACIS1_REG ACSR -#define ACIC_REG ACSR -#define ACIE_REG ACSR -#define ACI_REG ACSR -#define ACO_REG ACSR -#define ACBG_REG ACSR -#define ACD_REG ACSR - -/* EECR */ -#define EERE_REG EECR -#define EEWE_REG EECR -#define EEMWE_REG EECR -#define EERIE_REG EECR - -/* PORTE */ -#define PORTE0_REG PORTE -#define PORTE1_REG PORTE -#define PORTE2_REG PORTE -#define PORTE3_REG PORTE -#define PORTE4_REG PORTE -#define PORTE5_REG PORTE -#define PORTE6_REG PORTE -#define PORTE7_REG PORTE - -/* TCNT1L */ -#define TCNT1L0_REG TCNT1L -#define TCNT1L1_REG TCNT1L -#define TCNT1L2_REG TCNT1L -#define TCNT1L3_REG TCNT1L -#define TCNT1L4_REG TCNT1L -#define TCNT1L5_REG TCNT1L -#define TCNT1L6_REG TCNT1L -#define TCNT1L7_REG TCNT1L - -/* PORTB */ -#define PORTB0_REG PORTB -#define PORTB1_REG PORTB -#define PORTB2_REG PORTB -#define PORTB3_REG PORTB -#define PORTB4_REG PORTB -#define PORTB5_REG PORTB -#define PORTB6_REG PORTB -#define PORTB7_REG PORTB - -/* PORTD */ -#define PORTD0_REG PORTD -#define PORTD1_REG PORTD -#define PORTD2_REG PORTD -#define PORTD3_REG PORTD -#define PORTD4_REG PORTD -#define PORTD5_REG PORTD -#define PORTD6_REG PORTD -#define PORTD7_REG PORTD - -/* UCSR0B */ -#define TXB80_REG UCSR0B -#define RXB80_REG UCSR0B -#define UCSZ02_REG UCSR0B -#define TXEN0_REG UCSR0B -#define RXEN0_REG UCSR0B -#define UDRIE0_REG UCSR0B -#define TXCIE0_REG UCSR0B -#define RXCIE0_REG UCSR0B - -/* TCNT1H */ -#define TCNT1H0_REG TCNT1H -#define TCNT1H1_REG TCNT1H -#define TCNT1H2_REG TCNT1H -#define TCNT1H3_REG TCNT1H -#define TCNT1H4_REG TCNT1H -#define TCNT1H5_REG TCNT1H -#define TCNT1H6_REG TCNT1H -#define TCNT1H7_REG TCNT1H - -/* PORTC */ -#define PORTC0_REG PORTC -#define PORTC1_REG PORTC -#define PORTC2_REG PORTC -#define PORTC3_REG PORTC -#define PORTC4_REG PORTC -#define PORTC5_REG PORTC -#define PORTC6_REG PORTC -#define PORTC7_REG PORTC - -/* ADCH */ -#define ADCH0_REG ADCH -#define ADCH1_REG ADCH -#define ADCH2_REG ADCH -#define ADCH3_REG ADCH -#define ADCH4_REG ADCH -#define ADCH5_REG ADCH -#define ADCH6_REG ADCH -#define ADCH7_REG ADCH - -/* PORTA */ -#define PORTA0_REG PORTA -#define PORTA1_REG PORTA -#define PORTA2_REG PORTA -#define PORTA3_REG PORTA -#define PORTA4_REG PORTA -#define PORTA5_REG PORTA -#define PORTA6_REG PORTA -#define PORTA7_REG PORTA - -/* TCNT2 */ -#define TCNT2_0_REG TCNT2 -#define TCNT2_1_REG TCNT2 -#define TCNT2_2_REG TCNT2 -#define TCNT2_3_REG TCNT2 -#define TCNT2_4_REG TCNT2 -#define TCNT2_5_REG TCNT2 -#define TCNT2_6_REG TCNT2 -#define TCNT2_7_REG TCNT2 - -/* TCNT0 */ -#define TCNT0_0_REG TCNT0 -#define TCNT0_1_REG TCNT0 -#define TCNT0_2_REG TCNT0 -#define TCNT0_3_REG TCNT0 -#define TCNT0_4_REG TCNT0 -#define TCNT0_5_REG TCNT0 -#define TCNT0_6_REG TCNT0 -#define TCNT0_7_REG TCNT0 - -/* MCUCSR */ -#define PORF_REG MCUCSR -#define EXTRF_REG MCUCSR - -/* UCSR0A */ -#define MPCM0_REG UCSR0A -#define U2X0_REG UCSR0A -#define UPE0_REG UCSR0A -#define DOR0_REG UCSR0A -#define FE0_REG UCSR0A -#define UDRE0_REG UCSR0A -#define TXC0_REG UCSR0A -#define RXC0_REG UCSR0A - -/* EEARL */ -#define EEARL0_REG EEARL -#define EEARL1_REG EEARL -#define EEARL2_REG EEARL -#define EEARL3_REG EEARL -#define EEARL4_REG EEARL -#define EEARL5_REG EEARL -#define EEARL6_REG EEARL -#define EEARL7_REG EEARL - -/* TCCR2 */ -#define CS20_REG TCCR2 -#define CS21_REG TCCR2 -#define CS22_REG TCCR2 -#define CTC2_REG TCCR2 -#define COM20_REG TCCR2 -#define COM21_REG TCCR2 -#define PWM2_REG TCCR2 - -/* TIFR */ -#define TOV2_REG TIFR -#define OCF2_REG TIFR -#define TOV0_REG TIFR -#define OCF0_REG TIFR -#define TOV1_REG TIFR -#define OCF1B_REG TIFR -#define OCF1A_REG TIFR -#define ICF1_REG TIFR - -/* UBRR0L */ -#define UBRR0_REG UBRR0L -#define UBRR1_REG UBRR0L -#define UBRR2_REG UBRR0L -#define UBRR3_REG UBRR0L -#define UBRR4_REG UBRR0L -#define UBRR5_REG UBRR0L -#define UBRR6_REG UBRR0L -#define UBRR7_REG UBRR0L - -/* EEARH */ -#define EEAR8_REG EEARH -#define EEAR9_REG EEARH -#define EEAR10_REG EEARH -#define EEAR11_REG EEARH - -/* EICRB */ -#define ISC40_REG EICRB -#define ISC41_REG EICRB -#define ISC50_REG EICRB -#define ISC51_REG EICRB -#define ISC60_REG EICRB -#define ISC61_REG EICRB -#define ISC70_REG EICRB -#define ISC71_REG EICRB - -/* PINB */ -#define PINB0_REG PINB -#define PINB1_REG PINB -#define PINB2_REG PINB -#define PINB3_REG PINB -#define PINB4_REG PINB -#define PINB5_REG PINB -#define PINB6_REG PINB -#define PINB7_REG PINB - -/* EIFR */ -#define INTF0_REG EIFR -#define INTF1_REG EIFR -#define INTF2_REG EIFR -#define INTF3_REG EIFR -#define INTF4_REG EIFR -#define INTF5_REG EIFR -#define INTF6_REG EIFR -#define INTF7_REG EIFR - -/* PINF */ -#define PINF0_REG PINF -#define PINF1_REG PINF -#define PINF2_REG PINF -#define PINF3_REG PINF -#define PINF4_REG PINF -#define PINF5_REG PINF -#define PINF6_REG PINF -#define PINF7_REG PINF - -/* PINE */ -#define PINE0_REG PINE -#define PINE1_REG PINE -#define PINE2_REG PINE -#define PINE3_REG PINE -#define PINE4_REG PINE -#define PINE5_REG PINE -#define PINE6_REG PINE -#define PINE7_REG PINE - -/* MCUCR */ -#define IVCE_REG MCUCR -#define IVSEL_REG MCUCR -#define SM2_REG MCUCR -#define SM0_REG MCUCR -#define SM1_REG MCUCR -#define SE_REG MCUCR -#define SRW10_REG MCUCR -#define SRE_REG MCUCR - -/* OCR1AH */ -#define OCR1AH0_REG OCR1AH -#define OCR1AH1_REG OCR1AH -#define OCR1AH2_REG OCR1AH -#define OCR1AH3_REG OCR1AH -#define OCR1AH4_REG OCR1AH -#define OCR1AH5_REG OCR1AH -#define OCR1AH6_REG OCR1AH -#define OCR1AH7_REG OCR1AH - -/* OCR1AL */ -#define OCR1AL0_REG OCR1AL -#define OCR1AL1_REG OCR1AL -#define OCR1AL2_REG OCR1AL -#define OCR1AL3_REG OCR1AL -#define OCR1AL4_REG OCR1AL -#define OCR1AL5_REG OCR1AL -#define OCR1AL6_REG OCR1AL -#define OCR1AL7_REG OCR1AL - -/* SPCR */ -#define SPR0_REG SPCR -#define SPR1_REG SPCR -#define CPHA_REG SPCR -#define CPOL_REG SPCR -#define MSTR_REG SPCR -#define DORD_REG SPCR -#define SPE_REG SPCR -#define SPIE_REG SPCR - -/* OCR0 */ -#define OCR0_0_REG OCR0 -#define OCR0_1_REG OCR0 -#define OCR0_2_REG OCR0 -#define OCR0_3_REG OCR0 -#define OCR0_4_REG OCR0 -#define OCR0_5_REG OCR0 -#define OCR0_6_REG OCR0 -#define OCR0_7_REG OCR0 - -/* PINA */ -#define PINA0_REG PINA -#define PINA1_REG PINA -#define PINA2_REG PINA -#define PINA3_REG PINA -#define PINA4_REG PINA -#define PINA5_REG PINA -#define PINA6_REG PINA -#define PINA7_REG PINA - -/* OCR2 */ -#define OCR2_0_REG OCR2 -#define OCR2_1_REG OCR2 -#define OCR2_2_REG OCR2 -#define OCR2_3_REG OCR2 -#define OCR2_4_REG OCR2 -#define OCR2_5_REG OCR2 -#define OCR2_6_REG OCR2 -#define OCR2_7_REG OCR2 - -/* ASSR */ -#define TCR0UB_REG ASSR -#define OCR0UB_REG ASSR -#define TCN0UB_REG ASSR -#define AS0_REG ASSR - -/* pins mapping */ -#define AD0_PORT PORTA -#define AD0_BIT 0 - -#define AD1_PORT PORTA -#define AD1_BIT 1 - -#define AD2_PORT PORTA -#define AD2_BIT 2 - -#define AD3_PORT PORTA -#define AD3_BIT 3 - -#define AD4_PORT PORTA -#define AD4_BIT 4 - -#define AD5_PORT PORTA -#define AD5_BIT 5 - -#define AD6_PORT PORTA -#define AD6_BIT 6 - -#define AD7_PORT PORTA -#define AD7_BIT 7 - -#define SS_PORT PORTB -#define SS_BIT 0 - -#define SCK_PORT PORTB -#define SCK_BIT 1 - -#define MOSI_PORT PORTB -#define MOSI_BIT 2 - -#define MISO_PORT PORTB -#define MISO_BIT 3 - -#define OC0_PORT PORTB -#define OC0_BIT 4 -#define PWM0_PORT PORTB -#define PWM0_BIT 4 - -#define OC1A_PORT PORTB -#define OC1A_BIT 5 -#define PWM1A_PORT PORTB -#define PWM1A_BIT 5 - -#define OC1B_PORT PORTB -#define OC1B_BIT 6 -#define PWM1B_PORT PORTB -#define PWM1B_BIT 6 - -#define OC2_PORT PORTB -#define OC2_BIT 7 -#define PWM2_PORT PORTB -#define PWM2_BIT 7 -#define OC1C_PORT PORTB -#define OC1C_BIT 7 - -#define A8_PORT PORTC -#define A8_BIT 0 - -#define A9_PORT PORTC -#define A9_BIT 1 - -#define A10_PORT PORTC -#define A10_BIT 2 - -#define A11_PORT PORTC -#define A11_BIT 3 - -#define A12_PORT PORTC -#define A12_BIT 4 - -#define A13_PORT PORTC -#define A13_BIT 5 - -#define A14_PORT PORTC -#define A14_BIT 6 - -#define A15_PORT PORTC -#define A15_BIT 7 - -#define SCL_PORT PORTD -#define SCL_BIT 0 -#define INT0_PORT PORTD -#define INT0_BIT 0 - -#define SDA_PORT PORTD -#define SDA_BIT 1 -#define INT1_PORT PORTD -#define INT1_BIT 1 - -#define RXD1_PORT PORTD -#define RXD1_BIT 2 -#define INT2_PORT PORTD -#define INT2_BIT 2 - -#define TXD1_PORT PORTD -#define TXD1_BIT 3 -#define INT3_PORT PORTD -#define INT3_BIT 3 - -#define IC1_PORT PORTD -#define IC1_BIT 4 - -#define XCK1_PORT PORTD -#define XCK1_BIT 5 - -#define T1_PORT PORTD -#define T1_BIT 6 - -#define T2_PORT PORTD -#define T2_BIT 7 - -#define RXD0_PORT PORTE -#define RXD0_BIT 0 -#define PDI_PORT PORTE -#define PDI_BIT 0 - -#define TXD0_PORT PORTE -#define TXD0_BIT 1 -#define PDO_PORT PORTE -#define PDO_BIT 1 - -#define XCK0_PORT PORTE -#define XCK0_BIT 2 -#define AIN0_PORT PORTE -#define AIN0_BIT 2 - -#define OC3A_PORT PORTE -#define OC3A_BIT 3 -#define AIN1_PORT PORTE -#define AIN1_BIT 3 - -#define OC3B_PORT PORTE -#define OC3B_BIT 4 -#define INT4_PORT PORTE -#define INT4_BIT 4 - -#define OC3C_PORT PORTE -#define OC3C_BIT 5 -#define INT5_PORT PORTE -#define INT5_BIT 5 - -#define T3_PORT PORTE -#define T3_BIT 6 -#define INT6_PORT PORTE -#define INT6_BIT 6 - -#define IC3_PORT PORTE -#define IC3_BIT 7 -#define INT7_PORT PORTE -#define INT7_BIT 7 - -#define ADC0_PORT PORTF -#define ADC0_BIT 0 - -#define ADC1_PORT PORTF -#define ADC1_BIT 1 - -#define ADC2_PORT PORTF -#define ADC2_BIT 2 - -#define ADC3_PORT PORTF -#define ADC3_BIT 3 - -#define ADC4_PORT PORTF -#define ADC4_BIT 4 -#define TCK_PORT PORTF -#define TCK_BIT 4 - -#define ADC5_PORT PORTF -#define ADC5_BIT 5 -#define TMS_PORT PORTF -#define TMS_BIT 5 - -#define ADC6_PORT PORTF -#define ADC6_BIT 6 -#define TD0_PORT PORTF -#define TD0_BIT 6 - -#define ADC7_PORT PORTF -#define ADC7_BIT 7 -#define TDI_PORT PORTF -#define TDI_BIT 7 - -#define WR_PORT PORTG -#define WR_BIT 0 - -#define RD_PORT PORTG -#define RD_BIT 1 - -#define ALE_PORT PORTG -#define ALE_BIT 2 - -#define TOSC2_PORT PORTG -#define TOSC2_BIT 3 - -#define TOSC1_PORT PORTG -#define TOSC1_BIT 4 - -