X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=aversive%2Fparts%2FATtiny43U.h;fp=aversive%2Fparts%2FATtiny43U.h;h=0000000000000000000000000000000000000000;hb=57895b3bb2fe0582c589685b7df34f3968b346ec;hp=9bb6c69fbe3f1c8ddbbf186cd07652c43fa01114;hpb=9a9b64112aee5ab26398b46cb13b7e49c292a355;p=protos%2Fxbee-avr.git diff --git a/aversive/parts/ATtiny43U.h b/aversive/parts/ATtiny43U.h deleted file mode 100644 index 9bb6c69..0000000 --- a/aversive/parts/ATtiny43U.h +++ /dev/null @@ -1,524 +0,0 @@ -/* - * Copyright Droids Corporation, Microb Technology, Eirbot (2009) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * Revision : $Id $ - * - */ - -/* WARNING : this file is automatically generated by scripts. - * You should not edit it. If you find something wrong in it, - * write to zer0@droids-corp.org */ - - -/* prescalers timer 0 */ -#define TIMER0_PRESCALER_DIV_0 0 -#define TIMER0_PRESCALER_DIV_1 1 -#define TIMER0_PRESCALER_DIV_8 2 -#define TIMER0_PRESCALER_DIV_64 3 -#define TIMER0_PRESCALER_DIV_256 4 -#define TIMER0_PRESCALER_DIV_1024 5 -#define TIMER0_PRESCALER_DIV_FALL 6 -#define TIMER0_PRESCALER_DIV_RISE 7 - -#define TIMER0_PRESCALER_REG_0 0 -#define TIMER0_PRESCALER_REG_1 1 -#define TIMER0_PRESCALER_REG_2 8 -#define TIMER0_PRESCALER_REG_3 64 -#define TIMER0_PRESCALER_REG_4 256 -#define TIMER0_PRESCALER_REG_5 1024 -#define TIMER0_PRESCALER_REG_6 -1 -#define TIMER0_PRESCALER_REG_7 -2 - -/* prescalers timer 1 */ -#define TIMER1_PRESCALER_DIV_0 0 -#define TIMER1_PRESCALER_DIV_1 1 -#define TIMER1_PRESCALER_DIV_8 2 -#define TIMER1_PRESCALER_DIV_64 3 -#define TIMER1_PRESCALER_DIV_256 4 -#define TIMER1_PRESCALER_DIV_1024 5 -#define TIMER1_PRESCALER_DIV_FALL 6 -#define TIMER1_PRESCALER_DIV_RISE 7 - -#define TIMER1_PRESCALER_REG_0 0 -#define TIMER1_PRESCALER_REG_1 1 -#define TIMER1_PRESCALER_REG_2 8 -#define TIMER1_PRESCALER_REG_3 64 -#define TIMER1_PRESCALER_REG_4 256 -#define TIMER1_PRESCALER_REG_5 1024 -#define TIMER1_PRESCALER_REG_6 -1 -#define TIMER1_PRESCALER_REG_7 -2 - - -/* available timers */ - -/* overflow interrupt number */ -#define SIG_OVERFLOW_TOTAL_NUM 0 - -/* output compare interrupt number */ -#define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 - -/* Pwm nums */ -#define PWM_TOTAL_NUM 0 - -/* input capture interrupt number */ -#define SIG_INPUT_CAPTURE_TOTAL_NUM 0 - - -/* CLKPR */ -#define CLKPS0_REG CLKPR -#define CLKPS1_REG CLKPR -#define CLKPS2_REG CLKPR -#define CLKPS3_REG CLKPR -#define CLKPCE_REG CLKPR - -/* ACSR */ -#define ACIS0_REG ACSR -#define ACIS1_REG ACSR -#define ACIE_REG ACSR -#define ACI_REG ACSR -#define ACO_REG ACSR -#define ACBG_REG ACSR -#define ACD_REG ACSR - -/* GIMSK */ -#define PCIE0_REG GIMSK -#define PCIE1_REG GIMSK -#define INT0_REG GIMSK - -/* DIDR0 */ -#define ADC0D_REG DIDR0 -#define ADC1D_REG DIDR0 -#define ADC2D_REG DIDR0 -#define ADC3D_REG DIDR0 -#define AIN0D_REG DIDR0 -#define AIN1D_REG DIDR0 - -/* ADMUX */ -#define MUX0_REG ADMUX -#define MUX1_REG ADMUX -#define MUX2_REG ADMUX -#define REFS_REG ADMUX - -/* SREG */ -#define C_REG SREG -#define Z_REG SREG -#define N_REG SREG -#define V_REG SREG -#define S_REG SREG -#define H_REG SREG -#define T_REG SREG -#define I_REG SREG - -/* DDRB */ -#define DDB0_REG DDRB -#define DDB1_REG DDRB -#define DDB2_REG DDRB -#define DDB3_REG DDRB -#define DDB4_REG DDRB -#define DDB5_REG DDRB -#define DDB6_REG DDRB -#define DDB7_REG DDRB - -/* WDTCSR */ -#define WDP0_REG WDTCSR -#define WDP1_REG WDTCSR -#define WDP2_REG WDTCSR -#define WDE_REG WDTCSR -#define WDCE_REG WDTCSR -#define WDP3_REG WDTCSR -#define WDIE_REG WDTCSR -#define WDIF_REG WDTCSR - -/* EEDR */ -#define EEDR0_REG EEDR -#define EEDR1_REG EEDR -#define EEDR2_REG EEDR -#define EEDR3_REG EEDR -#define EEDR4_REG EEDR -#define EEDR5_REG EEDR -#define EEDR6_REG EEDR -#define EEDR7_REG EEDR - -/* OCR1A */ -/* #define OCR1_0_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_1_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_2_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_3_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_4_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_5_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_6_REG OCR1A */ /* dup in OCR1B */ -/* #define OCR1_7_REG OCR1A */ /* dup in OCR1B */ - -/* TCCR1A */ -#define WGM10_REG TCCR1A -#define WGM11_REG TCCR1A -#define COM1B0_REG TCCR1A -#define COM1B1_REG TCCR1A -#define COM1A0_REG TCCR1A -#define COM1A1_REG TCCR1A - -/* GTCCR */ -#define PSR10_REG GTCCR -#define TSM_REG GTCCR - -/* TCCR1B */ -#define CS10_REG TCCR1B -#define CS11_REG TCCR1B -#define CS12_REG TCCR1B -#define WGM12_REG TCCR1B -#define FOC1B_REG TCCR1B -#define FOC1A_REG TCCR1B - -/* GIFR */ -#define PCIF0_REG GIFR -#define PCIF1_REG GIFR -#define INTF0_REG GIFR - -/* OSCCAL */ -#define CAL0_REG OSCCAL -#define CAL1_REG OSCCAL -#define CAL2_REG OSCCAL -#define CAL3_REG OSCCAL -#define CAL4_REG OSCCAL -#define CAL5_REG OSCCAL -#define CAL6_REG OSCCAL -#define CAL7_REG OSCCAL - -/* DDRA */ -#define DDA0_REG DDRA -#define DDA1_REG DDRA -#define DDA2_REG DDRA -#define DDA3_REG DDRA -#define DDA4_REG DDRA -#define DDA5_REG DDRA -#define DDA6_REG DDRA -#define DDA7_REG DDRA - -/* ADCSRA */ -#define ADPS0_REG ADCSRA -#define ADPS1_REG ADCSRA -#define ADPS2_REG ADCSRA -#define ADIE_REG ADCSRA -#define ADIF_REG ADCSRA -#define ADATE_REG ADCSRA -#define ADSC_REG ADCSRA -#define ADEN_REG ADCSRA - -/* ADCSRB */ -#define ACME_REG ADCSRB -#define ADTS0_REG ADCSRB -#define ADTS1_REG ADCSRB -#define ADTS2_REG ADCSRB -#define ADLAR_REG ADCSRB -#define BVRON_REG ADCSRB - -/* OCR0A */ -/* #define OCR0_0_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_1_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_2_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_3_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_4_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_5_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_6_REG OCR0A */ /* dup in OCR0B */ -/* #define OCR0_7_REG OCR0A */ /* dup in OCR0B */ - -/* OCR0B */ -/* #define OCR0_0_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_1_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_2_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_3_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_4_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_5_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_6_REG OCR0B */ /* dup in OCR0A */ -/* #define OCR0_7_REG OCR0B */ /* dup in OCR0A */ - -/* SPH */ -#define SP8_REG SPH - -/* SPL */ -#define SP0_REG SPL -#define SP1_REG SPL -#define SP2_REG SPL -#define SP3_REG SPL -#define SP4_REG SPL -#define SP5_REG SPL -#define SP6_REG SPL -#define SP7_REG SPL - -/* PRR */ -#define PRADC_REG PRR -#define PRUSI_REG PRR -#define PRTIM0_REG PRR -#define PRTIM1_REG PRR - -/* GPIOR1 */ -#define GPIOR10_REG GPIOR1 -#define GPIOR11_REG GPIOR1 -#define GPIOR12_REG GPIOR1 -#define GPIOR13_REG GPIOR1 -#define GPIOR14_REG GPIOR1 -#define GPIOR15_REG GPIOR1 -#define GPIOR16_REG GPIOR1 -#define GPIOR17_REG GPIOR1 - -/* GPIOR0 */ -#define GPIOR00_REG GPIOR0 -#define GPIOR01_REG GPIOR0 -#define GPIOR02_REG GPIOR0 -#define GPIOR03_REG GPIOR0 -#define GPIOR04_REG GPIOR0 -#define GPIOR05_REG GPIOR0 -#define GPIOR06_REG GPIOR0 -#define GPIOR07_REG GPIOR0 - -/* GPIOR2 */ -#define GPIOR20_REG GPIOR2 -#define GPIOR21_REG GPIOR2 -#define GPIOR22_REG GPIOR2 -#define GPIOR23_REG GPIOR2 -#define GPIOR24_REG GPIOR2 -#define GPIOR25_REG GPIOR2 -#define GPIOR26_REG GPIOR2 -#define GPIOR27_REG GPIOR2 - -/* MCUSR */ -#define PORF_REG MCUSR -#define EXTRF_REG MCUSR -#define BORF_REG MCUSR -#define WDRF_REG MCUSR - -/* EECR */ -#define EERE_REG EECR -#define EEPE_REG EECR -#define EEMPE_REG EECR -#define EERIE_REG EECR -#define EEPM0_REG EECR -#define EEPM1_REG EECR - -/* USISR */ -#define USICNT0_REG USISR -#define USICNT1_REG USISR -#define USICNT2_REG USISR -#define USICNT3_REG USISR -#define USIDC_REG USISR -#define USIPF_REG USISR -#define USIOIF_REG USISR -#define USISIF_REG USISR - -/* SPMCSR */ -#define SPMEN_REG SPMCSR -#define PGERS_REG SPMCSR -#define PGWRT_REG SPMCSR -#define RFLB_REG SPMCSR -#define CTPB_REG SPMCSR - -/* ADCL */ -#define ADCL0_REG ADCL -#define ADCL1_REG ADCL -#define ADCL2_REG ADCL -#define ADCL3_REG ADCL -#define ADCL4_REG ADCL -#define ADCL5_REG ADCL -#define ADCL6_REG ADCL -#define ADCL7_REG ADCL - -/* EEAR */ -#define EEAR0_REG EEAR -#define EEAR1_REG EEAR -#define EEAR2_REG EEAR -#define EEAR3_REG EEAR -#define EEAR4_REG EEAR -#define EEAR5_REG EEAR - -/* PORTB */ -#define PORTB0_REG PORTB -#define PORTB1_REG PORTB -#define PORTB2_REG PORTB -#define PORTB3_REG PORTB -#define PORTB4_REG PORTB -#define PORTB5_REG PORTB -#define PORTB6_REG PORTB -#define PORTB7_REG PORTB - -/* ADCH */ -#define ADCH0_REG ADCH -#define ADCH1_REG ADCH -#define ADCH2_REG ADCH -#define ADCH3_REG ADCH -#define ADCH4_REG ADCH -#define ADCH5_REG ADCH -#define ADCH6_REG ADCH -#define ADCH7_REG ADCH - -/* PORTA */ -#define PORTA0_REG PORTA -#define PORTA1_REG PORTA -#define PORTA2_REG PORTA -#define PORTA3_REG PORTA -#define PORTA4_REG PORTA -#define PORTA5_REG PORTA -#define PORTA6_REG PORTA -#define PORTA7_REG PORTA - -/* TCNT0 */ -#define TCNT0_0_REG TCNT0 -#define TCNT0_1_REG TCNT0 -#define TCNT0_2_REG TCNT0 -#define TCNT0_3_REG TCNT0 -#define TCNT0_4_REG TCNT0 -#define TCNT0_5_REG TCNT0 -#define TCNT0_6_REG TCNT0 -#define TCNT0_7_REG TCNT0 - -/* TCNT1 */ -#define TCNT1_0_REG TCNT1 -#define TCNT1_1_REG TCNT1 -#define TCNT1_2_REG TCNT1 -#define TCNT1_3_REG TCNT1 -#define TCNT1_4_REG TCNT1 -#define TCNT1_5_REG TCNT1 -#define TCNT1_6_REG TCNT1 -#define TCNT1_7_REG TCNT1 - -/* TIMSK0 */ -#define TOIE0_REG TIMSK0 -#define OCIE0A_REG TIMSK0 -#define OCIE0B_REG TIMSK0 - -/* TIMSK1 */ -#define TOIE1_REG TIMSK1 -#define OCIE1A_REG TIMSK1 -#define OCIE1B_REG TIMSK1 - -/* TCCR0B */ -#define CS00_REG TCCR0B -#define CS01_REG TCCR0B -#define CS02_REG TCCR0B -#define WGM02_REG TCCR0B -#define FOC0B_REG TCCR0B -#define FOC0A_REG TCCR0B - -/* TCCR0A */ -#define WGM00_REG TCCR0A -#define WGM01_REG TCCR0A -#define COM0B0_REG TCCR0A -#define COM0B1_REG TCCR0A -#define COM0A0_REG TCCR0A -#define COM0A1_REG TCCR0A - -/* USICR */ -#define USITC_REG USICR -#define USICLK_REG USICR -#define USICS0_REG USICR -#define USICS1_REG USICR -#define USIWM0_REG USICR -#define USIWM1_REG USICR -#define USIOIE_REG USICR -#define USISIE_REG USICR - -/* PCMSK0 */ -#define PCINT0_REG PCMSK0 -#define PCINT1_REG PCMSK0 -#define PCINT2_REG PCMSK0 -#define PCINT3_REG PCMSK0 -#define PCINT4_REG PCMSK0 -#define PCINT5_REG PCMSK0 -#define PCINT6_REG PCMSK0 -#define PCINT7_REG PCMSK0 - -/* PCMSK1 */ -#define PCINT8_REG PCMSK1 -#define PCINT9_REG PCMSK1 -#define PCINT10_REG PCMSK1 -#define PCINT11_REG PCMSK1 -#define PCINT12_REG PCMSK1 -#define PCINT13_REG PCMSK1 -#define PCINT14_REG PCMSK1 -#define PCINT15_REG PCMSK1 - -/* PINB */ -#define PINB0_REG PINB -#define PINB1_REG PINB -#define PINB2_REG PINB -#define PINB3_REG PINB -#define PINB4_REG PINB -#define PINB5_REG PINB -#define PINB6_REG PINB -#define PINB7_REG PINB - -/* PINA */ -#define PINA0_REG PINA -#define PINA1_REG PINA -#define PINA2_REG PINA -#define PINA3_REG PINA -#define PINA4_REG PINA -#define PINA5_REG PINA -#define PINA6_REG PINA -#define PINA7_REG PINA - -/* OCR1B */ -/* #define OCR1_0_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_1_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_2_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_3_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_4_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_5_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_6_REG OCR1B */ /* dup in OCR1A */ -/* #define OCR1_7_REG OCR1B */ /* dup in OCR1A */ - -/* MCUCR */ -#define ISC00_REG MCUCR -#define ISC01_REG MCUCR -#define BODSE_REG MCUCR -#define SM0_REG MCUCR -#define SM1_REG MCUCR -#define SE_REG MCUCR -#define PUD_REG MCUCR -#define BODS_REG MCUCR - -/* USIDR */ -#define USIDR0_REG USIDR -#define USIDR1_REG USIDR -#define USIDR2_REG USIDR -#define USIDR3_REG USIDR -#define USIDR4_REG USIDR -#define USIDR5_REG USIDR -#define USIDR6_REG USIDR -#define USIDR7_REG USIDR - -/* USIBR */ -#define USIBR0_REG USIBR -#define USIBR1_REG USIBR -#define USIBR2_REG USIBR -#define USIBR3_REG USIBR -#define USIBR4_REG USIBR -#define USIBR5_REG USIBR -#define USIBR6_REG USIBR -#define USIBR7_REG USIBR - -/* TIFR0 */ -#define TOV0_REG TIFR0 -#define OCF0A_REG TIFR0 -#define OCF0B_REG TIFR0 - -/* TIFR1 */ -#define TOV1_REG TIFR1 -#define OCF1A_REG TIFR1 -#define OCF1B_REG TIFR1 - -/* pins mapping */ -