X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=config%2Farm%2Fmeson.build;h=9b147c0b93047b60cf2fc0aab373997aa87b2bd7;hb=6b62423face13bf321f7a9b4f6fac4d65a3efb9c;hp=a5bfb9610cb2f7f865bc9ef7e4460f4a574de518;hpb=200b88cbe0e6f3efd5edf81f8bfc4ace2bb17928;p=dpdk.git diff --git a/config/arm/meson.build b/config/arm/meson.build index a5bfb9610c..9b147c0b93 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -1,118 +1,494 @@ # SPDX-License-Identifier: BSD-3-Clause # Copyright(c) 2017 Intel Corporation. # Copyright(c) 2017 Cavium, Inc +# Copyright(c) 2021 PANTHEON.tech s.r.o. -# for checking defines we need to use the correct compiler flags -march_opt = '-march=@0@'.format(machine) - -machine_args_generic = [ - ['default', ['-march=armv8-a+crc+crypto']]] -machine_args_cavium = [ - ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], - ['0xa1', ['-mcpu=thunderxt88']], - ['0xa2', ['-mcpu=thunderxt81']], - ['0xa3', ['-mcpu=thunderxt83']]] - -flags_generic = [[]] -flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], - ['RTE_CACHE_LINE_SIZE', 128], - ['RTE_MAX_NUMA_NODES', 2], - ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_RING_USE_C11_MEM_MODEL', false]] - -impl_generic = ['Generic armv8', flags_generic, machine_args_generic] -impl_0x43 = ['Cavium', flags_cavium, machine_args_cavium] - -if cc.get_define('__clang__') != '' - dpdk_conf.set_quoted('RTE_TOOLCHAIN', 'clang') - dpdk_conf.set('RTE_TOOLCHAIN_CLANG', 1) -else - dpdk_conf.set_quoted('RTE_TOOLCHAIN', 'gcc') - dpdk_conf.set('RTE_TOOLCHAIN_GCC', 1) -endif +# common flags to all aarch64 builds, with lowest priority +flags_common = [ + # Accelerate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) + # to determine the best threshold in code. Refer to notes in source file + # (lib/eal/arm/include/rte_memcpy_64.h) for more info. + ['RTE_ARCH_ARM64_MEMCPY', false], + # ['RTE_ARM64_MEMCPY_ALIGNED_THRESHOLD', 2048], + # ['RTE_ARM64_MEMCPY_UNALIGNED_THRESHOLD', 512], + # Leave below RTE_ARM64_MEMCPY_xxx options commented out, + # unless there are strong reasons. + # ['RTE_ARM64_MEMCPY_SKIP_GCC_VER_CHECK', false], + # ['RTE_ARM64_MEMCPY_ALIGN_MASK', 0xF], + # ['RTE_ARM64_MEMCPY_STRICT_ALIGN', false], + + ['RTE_SCHED_VECTOR', false], + ['RTE_ARM_USE_WFE', false], + ['RTE_ARCH_ARM64', true], + ['RTE_CACHE_LINE_SIZE', 128] +] + +## Part numbers are specific to Arm implementers +# implementer specific aarch64 flags have middle priority +# (will overwrite common flags) +# part number specific aarch64 flags have higher priority +# (will overwrite both common and implementer specific flags) +implementer_generic = { + 'description': 'Generic armv8', + 'flags': [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_MAX_LCORE', 256], + ['RTE_MAX_NUMA_NODES', 4] + ], + 'part_number_config': { + 'generic': {'machine_args': ['-march=armv8-a+crc', '-moutline-atomics']} + } +} + +part_number_config_arm = { + '0xd03': {'machine_args': ['-mcpu=cortex-a53']}, + '0xd04': {'machine_args': ['-mcpu=cortex-a35']}, + '0xd07': {'machine_args': ['-mcpu=cortex-a57']}, + '0xd08': {'machine_args': ['-mcpu=cortex-a72']}, + '0xd09': {'machine_args': ['-mcpu=cortex-a73']}, + '0xd0a': {'machine_args': ['-mcpu=cortex-a75']}, + '0xd0b': {'machine_args': ['-mcpu=cortex-a76']}, + '0xd0c': { + 'machine_args': ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], + 'flags': [ + ['RTE_MACHINE', '"neoverse-n1"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_MAX_MEM_MB', 1048576], + ['RTE_MAX_LCORE', 160], + ['RTE_MAX_NUMA_NODES', 2] + ] + }, + '0xd49': { + 'machine_args': ['-march=armv8.5-a+crypto+sve2'], + 'flags': [ + ['RTE_MACHINE', '"neoverse-n2"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 1] + ] + } +} +implementer_arm = { + 'description': 'Arm', + 'flags': [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 4] + ], + 'part_number_config': part_number_config_arm +} + +flags_part_number_thunderx = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false] +] +implementer_cavium = { + 'description': 'Cavium', + 'flags': [ + ['RTE_MAX_VFIO_GROUPS', 128], + ['RTE_MAX_LCORE', 96], + ['RTE_MAX_NUMA_NODES', 2] + ], + 'part_number_config': { + '0xa1': { + 'machine_args': ['-mcpu=thunderxt88'], + 'flags': flags_part_number_thunderx + }, + '0xa2': { + 'machine_args': ['-mcpu=thunderxt81'], + 'flags': flags_part_number_thunderx + }, + '0xa3': { + 'machine_args': ['-mcpu=thunderxt83'], + 'flags': flags_part_number_thunderx + }, + '0xaf': { + 'machine_args': ['-march=armv8.1-a+crc+crypto', '-mcpu=thunderx2t99'], + 'flags': [ + ['RTE_MACHINE', '"thunderx2"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_LCORE', 256] + ] + }, + '0xb2': { + 'machine_args': ['-march=armv8.2-a+crc+crypto+lse', '-mcpu=octeontx2'], + 'flags': [ + ['RTE_MACHINE', '"octeontx2"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_MAX_LCORE', 36], + ['RTE_MAX_NUMA_NODES', 1] + ] + } + } +} + +implementer_ampere = { + 'description': 'Ampere Computing', + 'flags': [ + ['RTE_MACHINE', '"emag"'], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_LCORE', 32], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'part_number_config': { + '0x0': {'machine_args': ['-march=armv8-a+crc+crypto', '-mtune=emag']} + } +} + +implementer_hisilicon = { + 'description': 'HiSilicon', + 'flags': [ + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 128] + ], + 'part_number_config': { + '0xd01': { + 'machine_args': ['-march=armv8.2-a+crypto', '-mtune=tsv110'], + 'flags': [ + ['RTE_MACHINE', '"Kunpeng 920"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_MAX_LCORE', 256], + ['RTE_MAX_NUMA_NODES', 8] + ] + }, + '0xd02': { + 'machine_args': ['-march=armv8.2-a+crypto+sve'], + 'flags': [ + ['RTE_MACHINE', '"Kunpeng 930"'], + ['RTE_ARM_FEATURE_ATOMICS', true], + ['RTE_MAX_LCORE', 1280], + ['RTE_MAX_NUMA_NODES', 16] + ] + } + } +} + +implementer_qualcomm = { + 'description': 'Qualcomm', + 'flags': [ + ['RTE_MACHINE', '"armv8a"'], + ['RTE_USE_C11_MEM_MODEL', true], + ['RTE_CACHE_LINE_SIZE', 64], + ['RTE_MAX_LCORE', 64], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'part_number_config': { + '0xc00': {'machine_args': ['-march=armv8-a+crc']} + } +} + +## Arm implementers (ID from MIDR in Arm Architecture Reference Manual) +implementers = { + 'generic': implementer_generic, + '0x41': implementer_arm, + '0x43': implementer_cavium, + '0x48': implementer_hisilicon, + '0x50': implementer_ampere, + '0x51': implementer_qualcomm +} + +# SoC specific aarch64 flags have the highest priority +# (will overwrite all other flags) +soc_generic = { + 'description': 'Generic un-optimized build for all aarch64 machines', + 'implementer': 'generic', + 'part_number': 'generic' +} + +soc_armada = { + 'description': 'Marvell ARMADA', + 'implementer': '0x41', + 'part_number': '0xd08', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'numa': false +} + +soc_bluefield = { + 'description': 'NVIDIA BlueField', + 'implementer': '0x41', + 'part_number': '0xd08', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'numa': false +} + +soc_centriq2400 = { + 'description': 'Qualcomm Centriq 2400', + 'implementer': '0x51', + 'part_number': '0xc00', + 'numa': false +} + +soc_cn10k = { + 'description' : 'Marvell OCTEON 10', + 'implementer' : '0x41', + 'flags': [ + ['RTE_MAX_LCORE', 24], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'part_number': '0xd49', + 'numa': false +} + +soc_dpaa = { + 'description': 'NXP DPAA', + 'implementer': '0x41', + 'part_number': '0xd08', + 'flags': [ + ['RTE_MACHINE', '"dpaa"'], + ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false], + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'numa': false +} + +soc_emag = { + 'description': 'Ampere eMAG', + 'implementer': '0x50', + 'part_number': '0x0' +} + +soc_graviton2 = { + 'description': 'AWS Graviton2', + 'implementer': '0x41', + 'part_number': '0xd0c', + 'numa': false +} + +soc_kunpeng920 = { + 'description': 'HiSilicon Kunpeng 920', + 'implementer': '0x48', + 'part_number': '0xd01', + 'numa': true +} +soc_kunpeng930 = { + 'description': 'HiSilicon Kunpeng 930', + 'implementer': '0x48', + 'part_number': '0xd02', + 'numa': true +} + +soc_n1sdp = { + 'description': 'Arm Neoverse N1SDP', + 'implementer': '0x41', + 'part_number': '0xd0c', + 'flags': [ + ['RTE_MAX_LCORE', 4] + ], + 'numa': false +} + +soc_n2 = { + 'description': 'Arm Neoverse N2', + 'implementer': '0x41', + 'part_number': '0xd49', + 'numa': false +} + +soc_octeontx2 = { + 'description': 'Marvell OCTEON TX2', + 'implementer': '0x43', + 'part_number': '0xb2', + 'numa': false +} + +soc_stingray = { + 'description': 'Broadcom Stingray', + 'implementer': '0x41', + 'flags': [ + ['RTE_MAX_LCORE', 16], + ['RTE_MAX_NUMA_NODES', 1] + ], + 'part_number': '0xd08', + 'numa': false +} + +soc_thunderx2 = { + 'description': 'Marvell ThunderX2 T99', + 'implementer': '0x43', + 'part_number': '0xaf' +} + +soc_thunderxt88 = { + 'description': 'Marvell ThunderX T88', + 'implementer': '0x43', + 'part_number': '0xa1' +} + +''' +Start of SoCs list +generic: Generic un-optimized build for all aarch64 machines. +armada: Marvell ARMADA +bluefield: NVIDIA BlueField +centriq2400: Qualcomm Centriq 2400 +cn10k: Marvell OCTEON 10 +dpaa: NXP DPAA +emag: Ampere eMAG +graviton2: AWS Graviton2 +kunpeng920: HiSilicon Kunpeng 920 +kunpeng930: HiSilicon Kunpeng 930 +n1sdp: Arm Neoverse N1SDP +n2: Arm Neoverse N2 +octeontx2: Marvell OCTEON TX2 +stingray: Broadcom Stingray +thunderx2: Marvell ThunderX2 T99 +thunderxt88: Marvell ThunderX T88 +End of SoCs list +''' +# The string above is included in the documentation, keep it in sync with the +# SoCs list below. +socs = { + 'generic': soc_generic, + 'armada': soc_armada, + 'bluefield': soc_bluefield, + 'centriq2400': soc_centriq2400, + 'cn10k' : soc_cn10k, + 'dpaa': soc_dpaa, + 'emag': soc_emag, + 'graviton2': soc_graviton2, + 'kunpeng920': soc_kunpeng920, + 'kunpeng930': soc_kunpeng930, + 'n1sdp': soc_n1sdp, + 'n2': soc_n2, + 'octeontx2': soc_octeontx2, + 'stingray': soc_stingray, + 'thunderx2': soc_thunderx2, + 'thunderxt88': soc_thunderxt88 +} + +dpdk_conf.set('RTE_ARCH_ARM', 1) dpdk_conf.set('RTE_FORCE_INTRINSICS', 1) -if cc.sizeof('void *') != 8 - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) - dpdk_conf.set('RTE_ARCH_ARM', 1) - dpdk_conf.set('RTE_ARCH_ARMv7', 1) +if dpdk_conf.get('RTE_ARCH_32') + # armv7 build + dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) + dpdk_conf.set('RTE_ARCH_ARMv7', 1) + # the minimum architecture supported, armv7-a, needs the following, + machine_args += '-mfpu=neon' else - dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128) - dpdk_conf.set('RTE_ARCH_ARM64', 1) - dpdk_conf.set('RTE_ARCH_64', 1) - - machine = [] - cmd_generic = ['generic', '', '', 'default', ''] - cmd_output = cmd_generic # Set generic by default - machine_args = [] # Clear previous machine args - if not meson.is_cross_build() - # The script returns ['Implementer', 'Variant', 'Architecture', - # 'Primary Part number', 'Revision'] - detect_vendor = find_program(join_paths( - meson.current_source_dir(), 'armv8_machine.py')) - cmd = run_command(detect_vendor.path()) - if cmd.returncode() == 0 - cmd_output = cmd.stdout().strip().split(' ') - endif - # Set to generic if variable is not found - machine = get_variable('impl_' + cmd_output[0], 'generic') - else - impl_id = meson.get_cross_property('implementor_id', 'generic') - machine = get_variable('impl_' + impl_id) - endif - - if machine == 'generic' - machine = impl_generic - cmd_output = cmd_generic - endif - - message('Implementer : ' + machine[0]) - foreach flag: machine[1] - if flag.length() > 0 - dpdk_conf.set(flag[0], flag[1]) - endif - endforeach - # Primary part number based mcpu flags are supported - # for gcc versions > 7 - if cc.version().version_compare( - '<7.0') or cmd_output.length() == 0 - foreach marg: machine[2] - if marg[0] == 'default' - foreach f: marg[1] - machine_args += f - endforeach - endif - endforeach - else - foreach marg: machine[2] - if marg[0] == cmd_output[3] - foreach f: marg[1] - machine_args += f - endforeach - endif - endforeach - endif + # aarch64 build + soc = get_option('platform') + soc_config = {} + if not meson.is_cross_build() + if machine == 'generic' + # generic build + if soc != '' + error('Building for a particular platform is unsupported with generic build.') + endif + implementer_id = 'generic' + part_number = 'generic' + elif soc != '' + soc_config = socs.get(soc, {'not_supported': true}) + else + # native build + # The script returns ['Implementer', 'Variant', 'Architecture', + # 'Primary Part number', 'Revision'] + detect_vendor = find_program(join_paths(meson.current_source_dir(), + 'armv8_machine.py')) + cmd = run_command(detect_vendor.path()) + if cmd.returncode() == 0 + cmd_output = cmd.stdout().to_lower().strip().split(' ') + implementer_id = cmd_output[0] + part_number = cmd_output[3] + else + error('Error when getting Arm Implementer ID and part number.') + endif + endif + else + # cross build + soc = meson.get_cross_property('platform', '') + if soc == '' + error('Arm SoC must be specified in the cross file.') + endif + soc_config = socs.get(soc, {'not_supported': true}) + endif + + soc_flags = [] + if soc_config.has_key('not_supported') + error('SoC @0@ not supported.'.format(soc)) + elif soc_config != {} + implementer_id = soc_config['implementer'] + implementer_config = implementers[implementer_id] + part_number = soc_config['part_number'] + soc_flags = soc_config.get('flags', []) + if not soc_config.get('numa', true) + has_libnuma = 0 + endif + + disable_drivers += ',' + soc_config.get('disable_drivers', '') + enable_drivers += ',' + soc_config.get('enable_drivers', '') + endif + + if implementers.has_key(implementer_id) + implementer_config = implementers[implementer_id] + else + error('Unsupported Arm implementer: @0@. '.format(implementer_id) + + 'Please add support for it or use the generic ' + + '(-Dmachine=generic) build.') + endif + + message('Arm implementer: ' + implementer_config['description']) + message('Arm part number: ' + part_number) + + part_number_config = implementer_config['part_number_config'] + if part_number_config.has_key(part_number) + # use the specified part_number machine args if found + part_number_config = part_number_config[part_number] + else + # unknown part number + error('Unsupported part number @0@ of implementer @1@. ' + .format(part_number, implementer_id) + + 'Please add support for it or use the generic ' + + '(-Dmachine=generic) build.') + endif + + # add/overwrite flags in the proper order + dpdk_flags = flags_common + implementer_config['flags'] + part_number_config.get('flags', []) + soc_flags + + # apply supported machine args + machine_args = [] # Clear previous machine args + foreach flag: part_number_config['machine_args'] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + + # apply flags + foreach flag: dpdk_flags + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif + endforeach +endif +message('Using machine args: @0@'.format(machine_args)) + +if (cc.get_define('__ARM_NEON', args: machine_args) != '' or + cc.get_define('__aarch64__', args: machine_args) != '') + compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] endif -message(machine_args) -if cc.get_define('__ARM_NEON', args: machine_args) != '' - dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1) - compile_time_cpuflags += ['RTE_CPUFLAG_NEON'] +if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + compile_time_cpuflags += ['RTE_CPUFLAG_SVE'] endif if cc.get_define('__ARM_FEATURE_CRC32', args: machine_args) != '' - dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1) - compile_time_cpuflags += ['RTE_CPUFLAG_CRC32'] + compile_time_cpuflags += ['RTE_CPUFLAG_CRC32'] endif if cc.get_define('__ARM_FEATURE_CRYPTO', args: machine_args) != '' - dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1) - dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1) - dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1) - dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1) - compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL', - 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2'] + compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL', + 'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2'] endif