X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=config%2Fcommon_base;h=6fbd1d86b291a1ba203344f66911aec1c449843d;hb=e76d76b27be270b0eaba52b3a6bbc7860a9197af;hp=7abf7c6fcfea4247ef84b6623f87c62107c6bba4;hpb=fe93968722afe38d1bade07dcf5df0ebd35c5eb6;p=dpdk.git diff --git a/config/common_base b/config/common_base index 7abf7c6fcf..6fbd1d86b2 100644 --- a/config/common_base +++ b/config/common_base @@ -55,13 +55,32 @@ CONFIG_RTE_MAJOR_ABI= # CONFIG_RTE_CACHE_LINE_SIZE=64 +# +# Memory model +# +CONFIG_RTE_USE_C11_MEM_MODEL=n + # # Compile Environment Abstraction Layer # CONFIG_RTE_LIBRTE_EAL=y CONFIG_RTE_MAX_LCORE=128 CONFIG_RTE_MAX_NUMA_NODES=8 -CONFIG_RTE_MAX_MEMSEG=256 +CONFIG_RTE_MAX_HEAPS=32 +CONFIG_RTE_MAX_MEMSEG_LISTS=64 +# each memseg list will be limited to either RTE_MAX_MEMSEG_PER_LIST pages +# or RTE_MAX_MEM_MB_PER_LIST megabytes worth of memory, whichever is smaller +CONFIG_RTE_MAX_MEMSEG_PER_LIST=8192 +CONFIG_RTE_MAX_MEM_MB_PER_LIST=32768 +# a "type" is a combination of page size and NUMA node. total number of memseg +# lists per type will be limited to either RTE_MAX_MEMSEG_PER_TYPE pages (split +# over multiple lists of RTE_MAX_MEMSEG_PER_LIST pages), or +# RTE_MAX_MEM_MB_PER_TYPE megabytes of memory (split over multiple lists of +# RTE_MAX_MEM_MB_PER_LIST), whichever is smaller +CONFIG_RTE_MAX_MEMSEG_PER_TYPE=32768 +CONFIG_RTE_MAX_MEM_MB_PER_TYPE=131072 +# global maximum usable amount of VA, in megabytes +CONFIG_RTE_MAX_MEM_MB=524288 CONFIG_RTE_MAX_MEMZONE=2560 CONFIG_RTE_MAX_TAILQ=32 CONFIG_RTE_ENABLE_ASSERT=n @@ -74,8 +93,10 @@ CONFIG_RTE_EAL_ALWAYS_PANIC_ON_ERROR=n CONFIG_RTE_EAL_IGB_UIO=n CONFIG_RTE_EAL_VFIO=n CONFIG_RTE_MAX_VFIO_GROUPS=64 +CONFIG_RTE_MAX_VFIO_CONTAINERS=64 CONFIG_RTE_MALLOC_DEBUG=n CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n +CONFIG_RTE_USE_LIBBSD=n # # Recognize/ignore the AVX/AVX512 CPU flags for performance/power testing. @@ -113,7 +134,7 @@ CONFIG_RTE_MAX_QUEUES_PER_PORT=1024 CONFIG_RTE_LIBRTE_IEEE1588=n CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS=16 CONFIG_RTE_ETHDEV_RXTX_CALLBACKS=y -CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n +CONFIG_RTE_ETHDEV_PROFILE_WITH_VTUNE=n # # Turn off Tx preparation stage @@ -123,6 +144,16 @@ CONFIG_RTE_ETHDEV_PROFILE_ITT_WASTED_RX_ITERATIONS=n # CONFIG_RTE_ETHDEV_TX_PREPARE_NOOP=n +# +# Common libraries, before Bus/PMDs +# +CONFIG_RTE_LIBRTE_COMMON_DPAAX=n + +# +# Compile the Intel FPGA bus +# +CONFIG_RTE_LIBRTE_IFPGA_BUS=y + # # Compile PCI bus driver # @@ -143,6 +174,17 @@ CONFIG_RTE_LIBRTE_ARK_DEBUG_TX=n CONFIG_RTE_LIBRTE_ARK_DEBUG_STATS=n CONFIG_RTE_LIBRTE_ARK_DEBUG_TRACE=n +# +# Compile Aquantia Atlantic PMD driver +# +CONFIG_RTE_LIBRTE_ATLANTIC_PMD=y + +# +# Compile AMD PMD +# +CONFIG_RTE_LIBRTE_AXGBE_PMD=y +CONFIG_RTE_LIBRTE_AXGBE_PMD_DEBUG=n + # # Compile burst-oriented Broadcom PMD driver # @@ -189,11 +231,12 @@ CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=y # Compile burst-oriented NXP DPAA2 PMD driver # CONFIG_RTE_LIBRTE_DPAA2_PMD=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_INIT=n CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_RX=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX=n -CONFIG_RTE_LIBRTE_DPAA2_DEBUG_TX_FREE=n + +# +# Compile NXP ENETC PMD Driver +# +CONFIG_RTE_LIBRTE_ENETC_PMD=n # # Compile burst-oriented Amazon ENA PMD driver @@ -242,8 +285,6 @@ CONFIG_RTE_LIBRTE_I40E_INC_VECTOR=y CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=n CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF=64 CONFIG_RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM=4 -# interval up to 8160 us, aligned to 2 (or default value) -CONFIG_RTE_LIBRTE_I40E_ITR_INTERVAL=-1 # # Compile burst-oriented FM10K PMD @@ -256,6 +297,15 @@ CONFIG_RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE=y CONFIG_RTE_LIBRTE_FM10K_INC_VECTOR=y # +# Compile burst-oriented ICE PMD driver +# +CONFIG_RTE_LIBRTE_ICE_PMD=y +CONFIG_RTE_LIBRTE_ICE_DEBUG_RX=n +CONFIG_RTE_LIBRTE_ICE_DEBUG_TX=n +CONFIG_RTE_LIBRTE_ICE_DEBUG_TX_FREE=n +CONFIG_RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC=y +CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=n + # Compile burst-oriented AVF PMD driver # CONFIG_RTE_LIBRTE_AVF_PMD=y @@ -271,15 +321,14 @@ CONFIG_RTE_LIBRTE_AVF_16BYTE_RX_DESC=n CONFIG_RTE_LIBRTE_MLX4_PMD=n CONFIG_RTE_LIBRTE_MLX4_DEBUG=n CONFIG_RTE_LIBRTE_MLX4_DLOPEN_DEPS=n -CONFIG_RTE_LIBRTE_MLX4_TX_MP_CACHE=8 # -# Compile burst-oriented Mellanox ConnectX-4 & ConnectX-5 (MLX5) PMD +# Compile burst-oriented Mellanox ConnectX-4, ConnectX-5, +# ConnectX-6 & Bluefield (MLX5) PMD # CONFIG_RTE_LIBRTE_MLX5_PMD=n CONFIG_RTE_LIBRTE_MLX5_DEBUG=n CONFIG_RTE_LIBRTE_MLX5_DLOPEN_DEPS=n -CONFIG_RTE_LIBRTE_MLX5_TX_MP_CACHE=8 # # Compile burst-oriented Netronome NFP PMD driver @@ -307,11 +356,6 @@ CONFIG_RTE_LIBRTE_SFC_EFX_DEBUG=n # Compile software PMD backed by SZEDATA2 device # CONFIG_RTE_LIBRTE_PMD_SZEDATA2=n -# -# Defines firmware type address space. -# See documentation for supported values. -# Other values raise compile time error. -CONFIG_RTE_LIBRTE_PMD_SZEDATA2_AS=0 # # Compile burst-oriented Cavium Thunderx NICVF PMD driver @@ -385,6 +429,24 @@ CONFIG_RTE_LIBRTE_PMD_FAILSAFE=y # CONFIG_RTE_LIBRTE_MVPP2_PMD=n +# +# Compile Marvell MVNETA PMD driver +# +CONFIG_RTE_LIBRTE_MVNETA_PMD=n + +# +# Compile support for VMBus library +# +CONFIG_RTE_LIBRTE_VMBUS=n + +# +# Compile native PMD for Hyper-V/Azure +# +CONFIG_RTE_LIBRTE_NETVSC_PMD=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_RX=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_TX=n +CONFIG_RTE_LIBRTE_NETVSC_DEBUG_DUMP=n + # # Compile virtual device driver for NetVSC on Hyper-V/Azure # @@ -410,7 +472,7 @@ CONFIG_RTE_PMD_RING_MAX_TX_RINGS=16 # # Compile SOFTNIC PMD # -CONFIG_RTE_LIBRTE_PMD_SOFTNIC=y +CONFIG_RTE_LIBRTE_PMD_SOFTNIC=n # # Compile the TAP PMD @@ -428,6 +490,7 @@ CONFIG_RTE_PMD_PACKET_PREFETCH=y # CONFIG_RTE_LIBRTE_BBDEV=y CONFIG_RTE_BBDEV_MAX_DEVS=128 +CONFIG_RTE_BBDEV_OFFLOAD_COST=y # # Compile PMD for NULL bbdev device @@ -443,7 +506,6 @@ CONFIG_RTE_LIBRTE_PMD_BBDEV_TURBO_SW=n # Compile generic crypto device library # CONFIG_RTE_LIBRTE_CRYPTODEV=y -CONFIG_RTE_LIBRTE_CRYPTODEV_DEBUG=n CONFIG_RTE_CRYPTO_MAX_DEVS=64 # @@ -452,56 +514,63 @@ CONFIG_RTE_CRYPTO_MAX_DEVS=64 CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO=n CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO_DEBUG=n +# +# Compile NXP CAAM JR crypto Driver +# +CONFIG_RTE_LIBRTE_PMD_CAAM_JR=n +CONFIG_RTE_LIBRTE_PMD_CAAM_JR_BE=n + # # Compile NXP DPAA2 crypto sec driver for CAAM HW # CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=n -CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_INIT=n -CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_DRIVER=n -CONFIG_RTE_LIBRTE_DPAA2_SEC_DEBUG_RX=n -CONFIG_RTE_DPAA2_SEC_PMD_MAX_NB_SESSIONS=2048 # # NXP DPAA caam - crypto driver # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC=n -CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_INIT=n -CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_DRIVER=n -CONFIG_RTE_LIBRTE_DPAA_SEC_DEBUG_RX=n CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4 -CONFIG_RTE_DPAA_SEC_PMD_MAX_NB_SESSIONS=2048 # -# Compile PMD for QuickAssist based devices +# Compile PMD for Cavium OCTEON TX crypto device # -CONFIG_RTE_LIBRTE_PMD_QAT=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_INIT=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_TX=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_RX=n -CONFIG_RTE_LIBRTE_PMD_QAT_DEBUG_DRIVER=n +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y + +# +# Compile PMD for QuickAssist based devices - see docs for details +# +CONFIG_RTE_LIBRTE_PMD_QAT=y +CONFIG_RTE_LIBRTE_PMD_QAT_SYM=n # -# Number of sessions to create in the session memory pool -# on a single QuickAssist device. +# Max. number of QuickAssist devices, which can be detected and attached # -CONFIG_RTE_QAT_PMD_MAX_NB_SESSIONS=2048 +CONFIG_RTE_PMD_QAT_MAX_PCI_DEVICES=48 +CONFIG_RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS=16 +CONFIG_RTE_PMD_QAT_COMP_IM_BUFFER_SIZE=65536 + +# +# Compile PMD for virtio crypto devices +# +CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO=y +# +# Number of maximum virtio crypto devices +# +CONFIG_RTE_MAX_VIRTIO_CRYPTO=32 # # Compile PMD for AESNI backed device # CONFIG_RTE_LIBRTE_PMD_AESNI_MB=n -CONFIG_RTE_LIBRTE_PMD_AESNI_MB_DEBUG=n # # Compile PMD for Software backed device # CONFIG_RTE_LIBRTE_PMD_OPENSSL=n -CONFIG_RTE_LIBRTE_PMD_OPENSSL_DEBUG=n # # Compile PMD for AESNI GCM device # CONFIG_RTE_LIBRTE_PMD_AESNI_GCM=n -CONFIG_RTE_LIBRTE_PMD_AESNI_GCM_DEBUG=n # # Compile PMD for SNOW 3G device @@ -513,36 +582,62 @@ CONFIG_RTE_LIBRTE_PMD_SNOW3G_DEBUG=n # Compile PMD for KASUMI device # CONFIG_RTE_LIBRTE_PMD_KASUMI=n -CONFIG_RTE_LIBRTE_PMD_KASUMI_DEBUG=n # # Compile PMD for ZUC device # CONFIG_RTE_LIBRTE_PMD_ZUC=n -CONFIG_RTE_LIBRTE_PMD_ZUC_DEBUG=n -# # Compile PMD for Crypto Scheduler device # CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER=y -CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n # # Compile PMD for NULL Crypto device # CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y +# +# Compile PMD for AMD CCP crypto device +# +CONFIG_RTE_LIBRTE_PMD_CCP=n + # # Compile PMD for Marvell Crypto device # -CONFIG_RTE_LIBRTE_PMD_MRVL_CRYPTO=n -CONFIG_RTE_LIBRTE_PMD_MRVL_CRYPTO_DEBUG=n +CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=n # # Compile generic security library # CONFIG_RTE_LIBRTE_SECURITY=y +# +# Compile generic compression device library +# +CONFIG_RTE_LIBRTE_COMPRESSDEV=y +CONFIG_RTE_COMPRESS_MAX_DEVS=64 + +# +# Compile compressdev unit test +# +CONFIG_RTE_COMPRESSDEV_TEST=n + +# +# Compile PMD for Octeontx ZIPVF compression device +# +CONFIG_RTE_LIBRTE_PMD_OCTEONTX_ZIPVF=y + +# +# Compile PMD for ISA-L compression device +# +CONFIG_RTE_LIBRTE_PMD_ISAL=n + +# +# Compile PMD for ZLIB compression device +# +CONFIG_RTE_LIBRTE_PMD_ZLIB=n + # # Compile generic event device library # @@ -550,6 +645,10 @@ CONFIG_RTE_LIBRTE_EVENTDEV=y CONFIG_RTE_LIBRTE_EVENTDEV_DEBUG=n CONFIG_RTE_EVENT_MAX_DEVS=16 CONFIG_RTE_EVENT_MAX_QUEUES_PER_DEV=64 +CONFIG_RTE_EVENT_TIMER_ADAPTER_NUM_MAX=32 +CONFIG_RTE_EVENT_ETH_INTR_RING_SIZE=1024 +CONFIG_RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE=32 +CONFIG_RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE=32 # # Compile PMD for skeleton event device @@ -562,6 +661,11 @@ CONFIG_RTE_LIBRTE_PMD_SKELETON_EVENTDEV_DEBUG=n # CONFIG_RTE_LIBRTE_PMD_SW_EVENTDEV=y +# +# Compile PMD for distributed software event device +# +CONFIG_RTE_LIBRTE_PMD_DSW_EVENTDEV=y + # # Compile PMD for octeontx sso event device # @@ -590,11 +694,25 @@ CONFIG_RTE_LIBRTE_RAWDEV=y CONFIG_RTE_RAWDEV_MAX_DEVS=10 CONFIG_RTE_LIBRTE_PMD_SKELETON_RAWDEV=y +# +# Compile PMD for NXP DPAA2 CMDIF raw device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV=n + +# +# Compile PMD for NXP DPAA2 QDMA raw device +# +CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=n + +# +# Compile PMD for Intel FPGA raw device +# +CONFIG_RTE_LIBRTE_PMD_IFPGA_RAWDEV=y + # # Compile librte_ring # CONFIG_RTE_LIBRTE_RING=y -CONFIG_RTE_RING_USE_C11_MEM_MODEL=n # # Compile librte_mempool @@ -606,6 +724,8 @@ CONFIG_RTE_LIBRTE_MEMPOOL_DEBUG=n # # Compile Mempool drivers # +CONFIG_RTE_DRIVER_MEMPOOL_BUCKET=y +CONFIG_RTE_DRIVER_MEMPOOL_BUCKET_SIZE_KB=64 CONFIG_RTE_DRIVER_MEMPOOL_RING=y CONFIG_RTE_DRIVER_MEMPOOL_STACK=y @@ -676,6 +796,11 @@ CONFIG_RTE_LIBRTE_BITRATE=y # CONFIG_RTE_LIBRTE_LATENCY_STATS=y +# +# Compile librte_telemetry +# +CONFIG_RTE_LIBRTE_TELEMETRY=n + # # Compile librte_lpm # @@ -795,6 +920,25 @@ CONFIG_RTE_LIBRTE_VHOST_DEBUG=n # CONFIG_RTE_LIBRTE_PMD_VHOST=n +# +# Compile IFC driver +# To compile, CONFIG_RTE_LIBRTE_VHOST and CONFIG_RTE_EAL_VFIO +# should be enabled. +# +CONFIG_RTE_LIBRTE_IFC_PMD=n + +# +# Compile librte_bpf +# +CONFIG_RTE_LIBRTE_BPF=y +# allow load BPF from ELF files (requires libelf) +CONFIG_RTE_LIBRTE_BPF_ELF=n + +# +# Compile librte_ipsec +# +CONFIG_RTE_LIBRTE_IPSEC=y + # # Compile the test application # @@ -818,6 +962,11 @@ CONFIG_RTE_TEST_PMD_RECORD_BURST_STATS=n # CONFIG_RTE_TEST_BBDEV=y +# +# Compile the compression performance application +# +CONFIG_RTE_APP_COMPRESS_PERF=y + # # Compile the crypto performance application #