X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=doc%2Fguides%2Fnics%2Fice.rst;h=f95fef8cf0a0310114209603e439d98c0b818fc5;hb=34fd4373ce76efd0236e59397c495762c2ec9e64;hp=22a19b8bbae55fa6d7152f6b350d771512fc1281;hpb=79d559de896b29f6b557a27a8b6381944e39a87d;p=dpdk.git

diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst
index 22a19b8bba..f95fef8cf0 100644
--- a/doc/guides/nics/ice.rst
+++ b/doc/guides/nics/ice.rst
@@ -28,7 +28,8 @@ Linux Prerequisites
 Windows Prerequisites
 ---------------------
 
-- Follow the DPDK `Getting Started Guide for Windows <https://doc.dpdk.org/guides/windows_gsg/index.html>`_ to setup the basic DPDK environment.
+- Follow the :doc:`guide for Windows <../windows_gsg/run_apps>`
+  to setup the basic DPDK environment.
 
 - Identify the Intel® Ethernet adapter and get the latest NVM/FW version.
 
@@ -55,6 +56,8 @@ The detailed information can refer to chapter Tested Platforms/Tested NICs in re
    +-----------+---------------+-----------------+-----------+--------------+-----------+
    |    21.02  |     1.4.11    |      1.3.24     |  1.3.28   |    1.3.4     |    2.4    |
    +-----------+---------------+-----------------+-----------+--------------+-----------+
+   |    21.05  |     1.6.5     |      1.3.26     |  1.3.30   |    1.3.6     |    3.0    |
+   +-----------+---------------+-----------------+-----------+--------------+-----------+
 
 Pre-Installation Configuration
 ------------------------------
@@ -217,6 +220,26 @@ Runtime Config Options
 
   These ICE_DBG_XXX are defined in ``drivers/net/ice/base/ice_type.h``.
 
+- ``1PPS out support``
+
+  The E810 supports four single-ended GPIO signals (SDP[20:23]). The 1PPS
+  signal outputs via SDP[20:23]. User can select GPIO pin index flexibly.
+  Pin index 0 means SDP20, 1 means SDP21 and so on. For example::
+
+    -a af:00.0,pps_out='[pin:0]'
+
+- ``Low Rx latency`` (default ``0``)
+
+  vRAN workloads require low latency DPDK interface for the front haul
+  interface connection to Radio. By specifying ``1`` for parameter
+  ``rx_low_latency``, each completed Rx descriptor can be written immediately
+  to host memory and the Rx interrupt latency can be reduced to 2us::
+
+    -a 0000:88:00.0,rx_low_latency=1
+
+  As a trade-off, this configuration may cause the packet processing performance
+  degradation due to the PCI bandwidth limitation.
+
 Driver compilation and testing
 ------------------------------