X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=doc%2Fguides%2Fnics%2Focteontx2.rst;h=258c1693fcfd2762774573db2aab8d33452308d1;hb=1b14508b3b34e768ad92c757ecace48b6e23c485;hp=adf7c7131dcce064f1cea62ac1fdf3134ff7a2da;hpb=87195879a066258bacb0252712d438955c72d7c5;p=dpdk.git diff --git a/doc/guides/nics/octeontx2.rst b/doc/guides/nics/octeontx2.rst index adf7c7131d..258c1693fc 100644 --- a/doc/guides/nics/octeontx2.rst +++ b/doc/guides/nics/octeontx2.rst @@ -4,7 +4,7 @@ OCTEON TX2 Poll Mode driver =========================== -The OCTEON TX2 ETHDEV PMD (**librte_pmd_octeontx2**) provides poll mode ethdev +The OCTEON TX2 ETHDEV PMD (**librte_net_octeontx2**) provides poll mode ethdev driver support for the inbuilt network device found in **Marvell OCTEON TX2** SoC family as well as for their virtual functions (VF) in SR-IOV context. @@ -38,20 +38,14 @@ Features of the OCTEON TX2 Ethdev PMD are: - IEEE1588 timestamping - HW offloaded `ethdev Rx queue` to `eventdev event queue` packet injection - Support Rx interrupt +- Inline IPsec processing support +- :ref:`Traffic Management API ` Prerequisites ------------- See :doc:`../platform/octeontx2` for setup information. -Compile time Config Options ---------------------------- - -The following options may be modified in the ``config`` file. - -- ``CONFIG_RTE_LIBRTE_OCTEONTX2_PMD`` (default ``y``) - - Toggle compilation of the ``librte_pmd_octeontx2`` driver. Driver compilation and testing ------------------------------ @@ -59,9 +53,6 @@ Driver compilation and testing Refer to the document :ref:`compiling and testing a PMD for a NIC ` for details. -To compile the OCTEON TX2 PMD for Linux arm64 gcc, -use arm64-octeontx2-linux-gcc as target. - #. Running testpmd: Follow instructions available in the document @@ -72,7 +63,7 @@ use arm64-octeontx2-linux-gcc as target. .. code-block:: console - ./build/app/testpmd -c 0x300 -w 0002:02:00.0 -- --portmask=0x1 --nb-cores=1 --port-topology=loop --rxq=1 --txq=1 + .//app/dpdk-testpmd -c 0x300 -a 0002:02:00.0 -- --portmask=0x1 --nb-cores=1 --port-topology=loop --rxq=1 --txq=1 EAL: Detected 24 lcore(s) EAL: Detected 1 NUMA nodes EAL: Multi-process socket /var/run/dpdk/rte/mp_socket @@ -113,11 +104,6 @@ use arm64-octeontx2-linux-gcc as target. Runtime Config Options ---------------------- -- ``HW offload ptype parsing disable`` (default ``0``) - - Packet type parsing is HW offloaded by default and this feature may be toggled - using ``ptype_disable`` ``devargs`` parameter. - - ``Rx&Tx scalar mode enable`` (default ``0``) Ethdev supports both scalar and vector mode, it may be selected at runtime @@ -130,7 +116,7 @@ Runtime Config Options For example:: - -w 0002:02:00.0,reta_size=256 + -a 0002:02:00.0,reta_size=256 With the above configuration, reta table of size 256 is populated. @@ -141,7 +127,7 @@ Runtime Config Options For example:: - -w 0002:02:00.0,flow_max_priority=10 + -a 0002:02:00.0,flow_max_priority=10 With the above configuration, priority level was set to 10 (0-9). Max priority level supported is 32. @@ -153,7 +139,7 @@ Runtime Config Options For example:: - -w 0002:02:00.0,flow_prealloc_size=4 + -a 0002:02:00.0,flow_prealloc_size=4 With the above configuration, pre alloc size was set to 4. Max pre alloc size supported is 32. @@ -165,23 +151,69 @@ Runtime Config Options For example:: - -w 0002:02:00.0,max_sqb_count=64 + -a 0002:02:00.0,max_sqb_count=64 With the above configuration, each send queue's decscriptor buffer count is limited to a maximum of 64 buffers. -- ``switch header enable`` (default ``none``) +- ``Switch header enable`` (default ``none``) A port can be configured to a specific switch header type by using ``switch_header`` ``devargs`` parameter. For example:: - -w 0002:02:00.0,switch_header="higig2" + -a 0002:02:00.0,switch_header="higig2" With the above configuration, higig2 will be enabled on that port and the traffic on this port should be higig2 traffic only. Supported switch header - types are "higig2" and "dsa". + types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa". + +- ``RSS tag as XOR`` (default ``0``) + + C0 HW revision onward, The HW gives an option to configure the RSS adder as + + * ``rss_adder<7:0> = flow_tag<7:0> ^ flow_tag<15:8> ^ flow_tag<23:16> ^ flow_tag<31:24>`` + + * ``rss_adder<7:0> = flow_tag<7:0>`` + + Latter one aligns with standard NIC behavior vs former one is a legacy + RSS adder scheme used in OCTEON TX2 products. + + By default, the driver runs in the latter mode from C0 HW revision onward. + Setting this flag to 1 to select the legacy mode. + + For example to select the legacy mode(RSS tag adder as XOR):: + + -a 0002:02:00.0,tag_as_xor=1 + +- ``Max SPI for inbound inline IPsec`` (default ``1``) + + Max SPI supported for inbound inline IPsec processing can be specified by + ``ipsec_in_max_spi`` ``devargs`` parameter. + + For example:: + + -a 0002:02:00.0,ipsec_in_max_spi=128 + + With the above configuration, application can enable inline IPsec processing + on 128 SAs (SPI 0-127). + +- ``Lock Rx contexts in NDC cache`` + + Lock Rx contexts in NDC cache by using ``lock_rx_ctx`` parameter. + + For example:: + + -a 0002:02:00.0,lock_rx_ctx=1 + +- ``Lock Tx contexts in NDC cache`` + + Lock Tx contexts in NDC cache by using ``lock_tx_ctx`` parameter. + + For example:: + + -a 0002:02:00.0,lock_tx_ctx=1 .. note:: @@ -189,6 +221,34 @@ Runtime Config Options parameters to all the PCIe devices if application requires to configure on all the ethdev ports. +- ``Lock NPA contexts in NDC`` + + Lock NPA aura and pool contexts in NDC cache. + The device args take hexadecimal bitmask where each bit represent the + corresponding aura/pool id. + + For example:: + + -a 0002:02:00.0,npa_lock_mask=0xf + +.. _otx2_tmapi: + +Traffic Management API +---------------------- + +OCTEON TX2 PMD supports generic DPDK Traffic Management API which allows to +configure the following features: + +#. Hierarchical scheduling +#. Single rate - Two color, Two rate - Three color shaping + +Both DWRR and Static Priority(SP) hierarchial scheduling is supported. + +Every parent can have atmost 10 SP Children and unlimited DWRR children. + +Both PF & VF supports traffic management API with PF supporting 6 levels +and VF supporting 5 levels of topology. + Limitations ----------- @@ -212,6 +272,18 @@ Multicast MAC filtering ``net_octeontx2`` pmd supports multicast mac filtering feature only on physical function devices. +SDP interface support +~~~~~~~~~~~~~~~~~~~~~ +OCTEON TX2 SDP interface support is limited to PF device, No VF support. + +Inline Protocol Processing +~~~~~~~~~~~~~~~~~~~~~~~~~~ +``net_octeontx2`` pmd doesn't support the following features for packets to be +inline protocol processed. +- TSO offload +- VLAN/QinQ offload +- Fragmentation + Debugging Options ----------------- @@ -288,6 +360,10 @@ Patterns: +----+--------------------------------+ | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY | +----+--------------------------------+ + | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 | + +----+--------------------------------+ + | 25 | RTE_FLOW_ITEM_TYPE_RAW | + +----+--------------------------------+ .. note:: @@ -300,38 +376,87 @@ Actions: .. table:: Ingress action types - +----+--------------------------------+ - | # | Action Type | - +====+================================+ - | 1 | RTE_FLOW_ACTION_TYPE_VOID | - +----+--------------------------------+ - | 2 | RTE_FLOW_ACTION_TYPE_MARK | - +----+--------------------------------+ - | 3 | RTE_FLOW_ACTION_TYPE_FLAG | - +----+--------------------------------+ - | 4 | RTE_FLOW_ACTION_TYPE_COUNT | - +----+--------------------------------+ - | 5 | RTE_FLOW_ACTION_TYPE_DROP | - +----+--------------------------------+ - | 6 | RTE_FLOW_ACTION_TYPE_QUEUE | - +----+--------------------------------+ - | 7 | RTE_FLOW_ACTION_TYPE_RSS | - +----+--------------------------------+ - | 8 | RTE_FLOW_ACTION_TYPE_SECURITY | - +----+--------------------------------+ - | 9 | RTE_FLOW_ACTION_TYPE_PF | - +----+--------------------------------+ - | 10 | RTE_FLOW_ACTION_TYPE_VF | - +----+--------------------------------+ + +----+-----------------------------------------+ + | # | Action Type | + +====+=========================================+ + | 1 | RTE_FLOW_ACTION_TYPE_VOID | + +----+-----------------------------------------+ + | 2 | RTE_FLOW_ACTION_TYPE_MARK | + +----+-----------------------------------------+ + | 3 | RTE_FLOW_ACTION_TYPE_FLAG | + +----+-----------------------------------------+ + | 4 | RTE_FLOW_ACTION_TYPE_COUNT | + +----+-----------------------------------------+ + | 5 | RTE_FLOW_ACTION_TYPE_DROP | + +----+-----------------------------------------+ + | 6 | RTE_FLOW_ACTION_TYPE_QUEUE | + +----+-----------------------------------------+ + | 7 | RTE_FLOW_ACTION_TYPE_RSS | + +----+-----------------------------------------+ + | 8 | RTE_FLOW_ACTION_TYPE_SECURITY | + +----+-----------------------------------------+ + | 9 | RTE_FLOW_ACTION_TYPE_PF | + +----+-----------------------------------------+ + | 10 | RTE_FLOW_ACTION_TYPE_VF | + +----+-----------------------------------------+ + | 11 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN | + +----+-----------------------------------------+ + | 12 | RTE_FLOW_ACTION_TYPE_PORT_ID | + +----+-----------------------------------------+ + +.. note:: + + ``RTE_FLOW_ACTION_TYPE_PORT_ID`` is only supported between PF and its VFs. .. _table_octeontx2_supported_egress_action_types: .. table:: Egress action types - +----+--------------------------------+ - | # | Action Type | - +====+================================+ - | 1 | RTE_FLOW_ACTION_TYPE_COUNT | - +----+--------------------------------+ - | 2 | RTE_FLOW_ACTION_TYPE_DROP | - +----+--------------------------------+ + +----+-----------------------------------------+ + | # | Action Type | + +====+=========================================+ + | 1 | RTE_FLOW_ACTION_TYPE_COUNT | + +----+-----------------------------------------+ + | 2 | RTE_FLOW_ACTION_TYPE_DROP | + +----+-----------------------------------------+ + | 3 | RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN | + +----+-----------------------------------------+ + | 4 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID | + +----+-----------------------------------------+ + | 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP | + +----+-----------------------------------------+ + +Custom protocols supported in RTE Flow +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols. + +* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level. +* ``NGIO`` can be parsed at L3 level. + +For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the +respective switch header. + +For example:: + + -a 0002:02:00.0,switch_header="vlan_exdsa" + +The below fields of ``struct rte_flow_item_raw`` shall be used to specify the +pattern. + +- ``relative`` Selects the layer at which parsing is done. + + - 0 for ``exdsa`` and ``vlan_exdsa``. + + - 1 for ``NGIO``. + +- ``offset`` The offset in the header where the pattern should be matched. +- ``length`` Length of the pattern. +- ``pattern`` Pattern as a byte string. + +Example usage in testpmd:: + + ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \ + --rx-offloads=0x00080000 --rxq 8 --txq 8 + testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \ + spec ab pattern mask ab offset is 4 / end actions queue index 1 / end