X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fbaseband%2Facc100%2Frte_acc100_pmd.h;h=03ed0b3e1a311ea827b29fd16f3c8794c0783623;hb=b29890822981ccb1baa64737a218dc416a079404;hp=6525d6642e5ab2651150583debe1f1084e605009;hpb=4cf9007979782945635b2489d7b0f5fe415abc0c;p=dpdk.git

diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h
index 6525d6642e..03ed0b3e1a 100644
--- a/drivers/baseband/acc100/rte_acc100_pmd.h
+++ b/drivers/baseband/acc100/rte_acc100_pmd.h
@@ -7,6 +7,7 @@
 
 #include "acc100_pf_enum.h"
 #include "acc100_vf_enum.h"
+#include "rte_acc100_cfg.h"
 
 /* Helper macro for logging */
 #define rte_bbdev_log(level, fmt, ...) \
@@ -87,6 +88,8 @@
 #define ACC100_TMPL_PRI_3      0x0f0e0d0c
 #define ACC100_QUEUE_ENABLE    0x80000000  /* Bit to mark Queue as Enabled */
 #define ACC100_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
+#define ACC100_FDONE    0x80000000
+#define ACC100_SDONE    0x40000000
 
 #define ACC100_NUM_TMPL       32
 /* Mapping of signals for the available engines */
@@ -98,6 +101,13 @@
 #define ACC100_SIG_UL_4G_LAST 21
 #define ACC100_SIG_DL_4G      27
 #define ACC100_SIG_DL_4G_LAST 31
+#define ACC100_NUM_ACCS       5
+#define ACC100_ACCMAP_0       0
+#define ACC100_ACCMAP_1       2
+#define ACC100_ACCMAP_2       1
+#define ACC100_ACCMAP_3       3
+#define ACC100_ACCMAP_4       4
+#define ACC100_PF_VAL         2
 
 /* max number of iterations to allocate memory block for all rings */
 #define ACC100_SW_RING_MEM_ALLOC_ATTEMPTS 5
@@ -112,6 +122,9 @@
 #define ACC100_FCW_TD_BLEN                24
 #define ACC100_FCW_LE_BLEN                32
 #define ACC100_FCW_LD_BLEN                36
+#define ACC100_5GUL_SIZE_0                16
+#define ACC100_5GUL_SIZE_1                40
+#define ACC100_5GUL_OFFSET_0              36
 
 #define ACC100_FCW_VER         2
 #define ACC100_MUX_5GDL_DESC   6
@@ -145,6 +158,7 @@
 #define ACC100_RESET_HARD       0x1FF
 #define ACC100_ENGINES_MAX      9
 #define ACC100_LONG_WAIT        1000
+#define ACC100_GPEX_AXIMAP_NUM  17
 
 /* ACC100 DMA Descriptor triplet */
 struct acc100_dma_triplet {
@@ -394,6 +408,7 @@ struct __rte_packed acc100_dma_req_desc {
 union acc100_dma_desc {
 	struct acc100_dma_req_desc req;
 	union acc100_dma_rsp_desc rsp;
+	uint64_t atom_hdr;
 };
 
 
@@ -514,11 +529,74 @@ static const struct acc100_registry_addr vf_reg_addr = {
 	.ddr_range = HWVfDmaDdrBaseRangeRoVf,
 };
 
+/* Structure associated with each queue. */
+struct __rte_cache_aligned acc100_queue {
+	union acc100_dma_desc *ring_addr;  /* Virtual address of sw ring */
+	rte_iova_t ring_addr_iova;  /* IOVA address of software ring */
+	uint32_t sw_ring_head;  /* software ring head */
+	uint32_t sw_ring_tail;  /* software ring tail */
+	/* software ring size (descriptors, not bytes) */
+	uint32_t sw_ring_depth;
+	/* mask used to wrap enqueued descriptors on the sw ring */
+	uint32_t sw_ring_wrap_mask;
+	/* MMIO register used to enqueue descriptors */
+	void *mmio_reg_enqueue;
+	uint8_t vf_id;  /* VF ID (max = 63) */
+	uint8_t qgrp_id;  /* Queue Group ID */
+	uint16_t aq_id;  /* Atomic Queue ID */
+	uint16_t aq_depth;  /* Depth of atomic queue */
+	uint32_t aq_enqueued;  /* Count how many "batches" have been enqueued */
+	uint32_t aq_dequeued;  /* Count how many "batches" have been dequeued */
+	uint32_t irq_enable;  /* Enable ops dequeue interrupts if set to 1 */
+	struct rte_mempool *fcw_mempool;  /* FCW mempool */
+	enum rte_bbdev_op_type op_type;  /* Type of this Queue: TE or TD */
+	/* Internal Buffers for loopback input */
+	uint8_t *lb_in;
+	uint8_t *lb_out;
+	rte_iova_t lb_in_addr_iova;
+	rte_iova_t lb_out_addr_iova;
+	struct acc100_device *d;
+};
+
 /* Private data structure for each ACC100 device */
 struct acc100_device {
 	void *mmio_base;  /**< Base address of MMIO registers (BAR0) */
+	void *sw_rings_base;  /* Base addr of un-aligned memory for sw rings */
+	void *sw_rings;  /* 64MBs of 64MB aligned memory for sw rings */
+	rte_iova_t sw_rings_iova;  /* IOVA address of sw_rings */
+	/* Virtual address of the info memory routed to the this function under
+	 * operation, whether it is PF or VF.
+	 * HW may DMA information data at this location asynchronously
+	 */
+	union acc100_info_ring_data *info_ring;
+
+	union acc100_harq_layout_data *harq_layout;
+	/* Virtual Info Ring head */
+	uint16_t info_ring_head;
+	/* Number of bytes available for each queue in device, depending on
+	 * how many queues are enabled with configure()
+	 */
+	uint32_t sw_ring_size;
+	uint32_t ddr_size; /* Size in kB */
+	uint32_t *tail_ptrs; /* Base address of response tail pointer buffer */
+	rte_iova_t tail_ptr_iova; /* IOVA address of tail pointers */
+	/* Max number of entries available for each queue in device, depending
+	 * on how many queues are enabled with configure()
+	 */
+	uint32_t sw_ring_max_depth;
+	struct rte_acc100_conf acc100_conf; /* ACC100 Initial configuration */
+	/* Bitmap capturing which Queues have already been assigned */
+	uint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];
 	bool pf_device; /**< True if this is a PF ACC100 device */
 	bool configured; /**< True if this ACC100 device is configured */
 };
 
+/**
+ * Structure with details about RTE_BBDEV_EVENT_DEQUEUE event. It's passed to
+ * the callback function.
+ */
+struct acc100_deq_intr_details {
+	uint16_t queue_id;
+};
+
 #endif /* _RTE_ACC100_PMD_H_ */