X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fbaseband%2Ffpga_5gnr_fec%2Ffpga_5gnr_fec.h;h=e72c95e93687552053f9388ccf048326bcf5499e;hb=e74e1bb6280de764428b6560b9211e645fe796f4;hp=b39c92f5d832f4f1ea7ec8fa81cde5c51b6b31d9;hpb=c58109a8871d50081991601e8af83a9f5390c9ba;p=dpdk.git

diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
index b39c92f5d8..e72c95e936 100644
--- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
+++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h
@@ -53,6 +53,15 @@
 #define FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES 8
 #define FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES 8
 
+/* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */
+#define N_ZC_1 66 /* N = 66 Zc for BG 1 */
+#define N_ZC_2 50 /* N = 50 Zc for BG 2 */
+#define K0_1_1 17 /* K0 fraction numerator for rv 1 and BG 1 */
+#define K0_1_2 13 /* K0 fraction numerator for rv 1 and BG 2 */
+#define K0_2_1 33 /* K0 fraction numerator for rv 2 and BG 1 */
+#define K0_2_2 25 /* K0 fraction numerator for rv 2 and BG 2 */
+#define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */
+#define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */
 
 /* FPGA 5GNR FEC Register mapping on BAR0 */
 enum {
@@ -346,4 +355,34 @@ fpga_reg_read_32(void *mmio_base, uint32_t offset)
 	return rte_le_to_cpu_32(ret);
 }
 
+#ifdef RTE_LIBRTE_BBDEV_DEBUG
+
+/* Read a register of FPGA 5GNR FEC device */
+static inline uint16_t
+fpga_reg_read_16(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint16_t ret = *((volatile uint16_t *)(reg_addr));
+	return rte_le_to_cpu_16(ret);
+}
+
+#endif
+
+/* Read a register of FPGA 5GNR FEC device */
+static inline uint8_t
+fpga_reg_read_8(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	return *((volatile uint8_t *)(reg_addr));
+}
+
+/* Read a register of FPGA 5GNR FEC device */
+static inline uint64_t
+fpga_reg_read_64(void *mmio_base, uint32_t offset)
+{
+	void *reg_addr = RTE_PTR_ADD(mmio_base, offset);
+	uint64_t ret = *((volatile uint64_t *)(reg_addr));
+	return rte_le_to_cpu_64(ret);
+}
+
 #endif /* _FPGA_5GNR_FEC_H_ */