X-Git-Url: http://git.droids-corp.org/?a=blobdiff_plain;f=drivers%2Fbaseband%2Ffpga_5gnr_fec%2Frte_fpga_5gnr_fec.c;h=930718cd47a7043d11907c15f62da95a268eb140;hb=3cc6ecfdfe85d2577fef30e1791bb7534e3d60b3;hp=2d0fb4fda41a0de1adee857de545dba3dca031d6;hpb=44dc6faa796f13f8f15f4c7d52ceb50979e94bc9;p=dpdk.git diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 2d0fb4fda4..930718cd47 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -21,9 +21,168 @@ #include #include "fpga_5gnr_fec.h" +#include "rte_pmd_fpga_5gnr_fec.h" -/* 5GNR SW PMD logging ID */ -static int fpga_5gnr_fec_logtype; +#ifdef RTE_LIBRTE_BBDEV_DEBUG +RTE_LOG_REGISTER(fpga_5gnr_fec_logtype, pmd.bb.fpga_5gnr_fec, DEBUG); +#else +RTE_LOG_REGISTER(fpga_5gnr_fec_logtype, pmd.bb.fpga_5gnr_fec, NOTICE); +#endif + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + +/* Read Ring Control Register of FPGA 5GNR FEC device */ +static inline void +print_ring_reg_debug_info(void *mmio_base, uint32_t offset) +{ + rte_bbdev_log_debug( + "FPGA MMIO base address @ %p | Ring Control Register @ offset = 0x%08" + PRIx32, mmio_base, offset); + rte_bbdev_log_debug( + "RING_BASE_ADDR = 0x%016"PRIx64, + fpga_reg_read_64(mmio_base, offset)); + rte_bbdev_log_debug( + "RING_HEAD_ADDR = 0x%016"PRIx64, + fpga_reg_read_64(mmio_base, offset + + FPGA_5GNR_FEC_RING_HEAD_ADDR)); + rte_bbdev_log_debug( + "RING_SIZE = 0x%04"PRIx16, + fpga_reg_read_16(mmio_base, offset + + FPGA_5GNR_FEC_RING_SIZE)); + rte_bbdev_log_debug( + "RING_MISC = 0x%02"PRIx8, + fpga_reg_read_8(mmio_base, offset + + FPGA_5GNR_FEC_RING_MISC)); + rte_bbdev_log_debug( + "RING_ENABLE = 0x%02"PRIx8, + fpga_reg_read_8(mmio_base, offset + + FPGA_5GNR_FEC_RING_ENABLE)); + rte_bbdev_log_debug( + "RING_FLUSH_QUEUE_EN = 0x%02"PRIx8, + fpga_reg_read_8(mmio_base, offset + + FPGA_5GNR_FEC_RING_FLUSH_QUEUE_EN)); + rte_bbdev_log_debug( + "RING_SHADOW_TAIL = 0x%04"PRIx16, + fpga_reg_read_16(mmio_base, offset + + FPGA_5GNR_FEC_RING_SHADOW_TAIL)); + rte_bbdev_log_debug( + "RING_HEAD_POINT = 0x%04"PRIx16, + fpga_reg_read_16(mmio_base, offset + + FPGA_5GNR_FEC_RING_HEAD_POINT)); +} + +/* Read Static Register of FPGA 5GNR FEC device */ +static inline void +print_static_reg_debug_info(void *mmio_base) +{ + uint16_t config = fpga_reg_read_16(mmio_base, + FPGA_5GNR_FEC_CONFIGURATION); + uint8_t qmap_done = fpga_reg_read_8(mmio_base, + FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE); + uint16_t lb_factor = fpga_reg_read_16(mmio_base, + FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR); + uint16_t ring_desc_len = fpga_reg_read_16(mmio_base, + FPGA_5GNR_FEC_RING_DESC_LEN); + uint16_t flr_time_out = fpga_reg_read_16(mmio_base, + FPGA_5GNR_FEC_FLR_TIME_OUT); + + rte_bbdev_log_debug("UL.DL Weights = %u.%u", + ((uint8_t)config), ((uint8_t)(config >> 8))); + rte_bbdev_log_debug("UL.DL Load Balance = %u.%u", + ((uint8_t)lb_factor), ((uint8_t)(lb_factor >> 8))); + rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s", + (qmap_done > 0) ? "READY" : "NOT-READY"); + rte_bbdev_log_debug("Ring Descriptor Size = %u bytes", + ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES); + rte_bbdev_log_debug("FLR Timeout = %f usec", + (float)flr_time_out*FPGA_FLR_TIMEOUT_UNIT); +} + +/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */ +static void +print_dma_dec_desc_debug_info(union fpga_dma_desc *desc) +{ + rte_bbdev_log_debug("DMA response desc %p\n" + "\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")" + " | crcb_pass (%"PRIu32") | error(%"PRIu32")\n" + "\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | " + "bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n" + "\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") " + "| irq_en(%"PRIu32")\n" + "\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | " + "drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n" + "\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n" + "\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n" + "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")" + "| out_add (0x%08"PRIx32"%08"PRIx32")", + desc, + (uint32_t)desc->dec_req.done, + (uint32_t)desc->dec_req.iter, + (uint32_t)desc->dec_req.et_pass, + (uint32_t)desc->dec_req.crcb_pass, + (uint32_t)desc->dec_req.error, + (uint32_t)desc->dec_req.qm_idx, + (uint32_t)desc->dec_req.max_iter, + (uint32_t)desc->dec_req.bg_idx, + (uint32_t)desc->dec_req.harqin_en, + (uint32_t)desc->dec_req.zc, + (uint32_t)desc->dec_req.hbstroe_offset, + (uint32_t)desc->dec_req.num_null, + (uint32_t)desc->dec_req.irq_en, + (uint32_t)desc->dec_req.ncb, + (uint32_t)desc->dec_req.desc_idx, + (uint32_t)desc->dec_req.drop_crc24b, + (uint32_t)desc->dec_req.rv, + (uint32_t)desc->dec_req.crc24b_ind, + (uint32_t)desc->dec_req.et_dis, + (uint32_t)desc->dec_req.harq_input_length, + (uint32_t)desc->dec_req.rm_e, + (uint32_t)desc->dec_req.cbs_in_op, + (uint32_t)desc->dec_req.in_addr_hi, + (uint32_t)desc->dec_req.in_addr_lw, + (uint32_t)desc->dec_req.out_addr_hi, + (uint32_t)desc->dec_req.out_addr_lw); + uint32_t *word = (uint32_t *) desc; + rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n" + "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n", + word[0], word[1], word[2], word[3], + word[4], word[5], word[6], word[7]); +} + +/* Print decode DMA Descriptor of FPGA 5GNR encoder device */ +static void +print_dma_enc_desc_debug_info(union fpga_dma_desc *desc) +{ + rte_bbdev_log_debug("DMA response desc %p\n" + "%"PRIu32" %"PRIu32"\n" + "K' %"PRIu32" E %"PRIu32" desc %"PRIu32" Z %"PRIu32"\n" + "BG %"PRIu32" Qm %"PRIu32" CRC %"PRIu32" IRQ %"PRIu32"\n" + "k0 %"PRIu32" Ncb %"PRIu32" F %"PRIu32"\n", + desc, + (uint32_t)desc->enc_req.done, + (uint32_t)desc->enc_req.error, + + (uint32_t)desc->enc_req.k_, + (uint32_t)desc->enc_req.rm_e, + (uint32_t)desc->enc_req.desc_idx, + (uint32_t)desc->enc_req.zc, + + (uint32_t)desc->enc_req.bg_idx, + (uint32_t)desc->enc_req.qm_idx, + (uint32_t)desc->enc_req.crc_en, + (uint32_t)desc->enc_req.irq_en, + + (uint32_t)desc->enc_req.k0, + (uint32_t)desc->enc_req.ncb, + (uint32_t)desc->enc_req.num_null); + uint32_t *word = (uint32_t *) desc; + rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n" + "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n", + word[0], word[1], word[2], word[3], + word[4], word[5], word[6], word[7]); +} + +#endif static int fpga_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id) @@ -168,6 +327,8 @@ fpga_dev_info_get(struct rte_bbdev *dev, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE | + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK | + RTE_BBDEV_LDPC_DEC_INTERRUPTS | RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS, .llr_size = 6, .llr_decimals = 2, @@ -360,6 +521,10 @@ fpga_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, rte_bbdev_log_debug("BBDEV queue[%d] set up for FPGA queue[%d]", queue_id, q_idx); +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Read FPGA Ring Control Registers after configuration*/ + print_ring_reg_debug_info(d->mmio_base, ring_offset); +#endif return 0; } @@ -475,15 +640,154 @@ fpga_queue_stop(struct rte_bbdev *dev, uint16_t queue_id) return 0; } +static inline uint16_t +get_queue_id(struct rte_bbdev_data *data, uint8_t q_idx) +{ + uint16_t queue_id; + + for (queue_id = 0; queue_id < data->num_queues; ++queue_id) { + struct fpga_queue *q = data->queues[queue_id].queue_private; + if (q != NULL && q->q_idx == q_idx) + return queue_id; + } + + return -1; +} + +/* Interrupt handler triggered by FPGA dev for handling specific interrupt */ +static void +fpga_dev_interrupt_handler(void *cb_arg) +{ + struct rte_bbdev *dev = cb_arg; + struct fpga_5gnr_fec_device *fpga_dev = dev->data->dev_private; + struct fpga_queue *q; + uint64_t ring_head; + uint64_t q_idx; + uint16_t queue_id; + uint8_t i; + + /* Scan queue assigned to this device */ + for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) { + q_idx = 1ULL << i; + if (fpga_dev->q_bound_bit_map & q_idx) { + queue_id = get_queue_id(dev->data, i); + if (queue_id == (uint16_t) -1) + continue; + + /* Check if completion head was changed */ + q = dev->data->queues[queue_id].queue_private; + ring_head = *q->ring_head_addr; + if (q->shadow_completion_head != ring_head && + q->irq_enable == 1) { + q->shadow_completion_head = ring_head; + rte_bbdev_pmd_callback_process( + dev, + RTE_BBDEV_EVENT_DEQUEUE, + &queue_id); + } + } + } +} + +static int +fpga_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + + if (!rte_intr_cap_multiple(dev->intr_handle)) + return -ENOTSUP; + + q->irq_enable = 1; + + return 0; +} + +static int +fpga_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id) +{ + struct fpga_queue *q = dev->data->queues[queue_id].queue_private; + q->irq_enable = 0; + + return 0; +} + +static int +fpga_intr_enable(struct rte_bbdev *dev) +{ + int ret; + uint8_t i; + + if (!rte_intr_cap_multiple(dev->intr_handle)) { + rte_bbdev_log(ERR, "Multiple intr vector is not supported by FPGA (%s)", + dev->data->name); + return -ENOTSUP; + } + + /* Create event file descriptors for each of 64 queue. Event fds will be + * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where + * the IRQ number is a direct translation to the queue number. + * + * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable() + * mapped the first IRQ to already created interrupt event file + * descriptor (intr_handle->fd). + */ + if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) { + rte_bbdev_log(ERR, "Failed to create fds for %u queues", + dev->data->num_queues); + return -1; + } + + /* TODO Each event file descriptor is overwritten by interrupt event + * file descriptor. That descriptor is added to epoll observed list. + * It ensures that callback function assigned to that descriptor will + * invoked when any FPGA queue issues interrupt. + */ + for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) + dev->intr_handle->efds[i] = dev->intr_handle->fd; + + if (!dev->intr_handle->intr_vec) { + dev->intr_handle->intr_vec = rte_zmalloc("intr_vec", + dev->data->num_queues * sizeof(int), 0); + if (!dev->intr_handle->intr_vec) { + rte_bbdev_log(ERR, "Failed to allocate %u vectors", + dev->data->num_queues); + return -ENOMEM; + } + } + + ret = rte_intr_enable(dev->intr_handle); + if (ret < 0) { + rte_bbdev_log(ERR, + "Couldn't enable interrupts for device: %s", + dev->data->name); + return ret; + } + + ret = rte_intr_callback_register(dev->intr_handle, + fpga_dev_interrupt_handler, dev); + if (ret < 0) { + rte_bbdev_log(ERR, + "Couldn't register interrupt callback for device: %s", + dev->data->name); + return ret; + } + + return 0; +} + static const struct rte_bbdev_ops fpga_ops = { .setup_queues = fpga_setup_queues, + .intr_enable = fpga_intr_enable, .close = fpga_dev_close, .info_get = fpga_dev_info_get, .queue_setup = fpga_queue_setup, .queue_stop = fpga_queue_stop, .queue_start = fpga_queue_start, .queue_release = fpga_queue_release, + .queue_intr_enable = fpga_queue_intr_enable, + .queue_intr_disable = fpga_queue_intr_disable }; + static inline void fpga_dma_enqueue(struct fpga_queue *q, uint16_t num_desc, struct rte_bbdev_stats *queue_stats) @@ -519,6 +823,54 @@ check_bit(uint32_t bitmap, uint32_t bitmask) return bitmap & bitmask; } +/* Print an error if a descriptor error has occurred. + * Return 0 on success, 1 on failure + */ +static inline int +check_desc_error(uint32_t error_code) { + switch (error_code) { + case DESC_ERR_NO_ERR: + return 0; + case DESC_ERR_K_P_OUT_OF_RANGE: + rte_bbdev_log(ERR, "Encode block size K' is out of range"); + break; + case DESC_ERR_Z_C_NOT_LEGAL: + rte_bbdev_log(ERR, "Zc is illegal"); + break; + case DESC_ERR_DESC_OFFSET_ERR: + rte_bbdev_log(ERR, + "Queue offset does not meet the expectation in the FPGA" + ); + break; + case DESC_ERR_DESC_READ_FAIL: + rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read"); + break; + case DESC_ERR_DESC_READ_TIMEOUT: + rte_bbdev_log(ERR, "Descriptor read time-out"); + break; + case DESC_ERR_DESC_READ_TLP_POISONED: + rte_bbdev_log(ERR, "Descriptor read TLP poisoned"); + break; + case DESC_ERR_CB_READ_FAIL: + rte_bbdev_log(ERR, "Unsuccessful completion for code block"); + break; + case DESC_ERR_CB_READ_TIMEOUT: + rte_bbdev_log(ERR, "Code block read time-out"); + break; + case DESC_ERR_CB_READ_TLP_POISONED: + rte_bbdev_log(ERR, "Code block read TLP poisoned"); + break; + case DESC_ERR_HBSTORE_ERR: + rte_bbdev_log(ERR, "Hbstroe exceeds HARQ buffer size."); + break; + default: + rte_bbdev_log(ERR, "Descriptor error unknown error code %u", + error_code); + break; + } + return 1; +} + /* Compute value of k0. * Based on 3GPP 38.212 Table 5.4.2.1-2 * Starting position of different redundancy versions, k0 @@ -680,6 +1032,96 @@ fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, return 0; } +#ifdef RTE_LIBRTE_BBDEV_DEBUG +/* Validates LDPC encoder parameters */ +static int +validate_enc_op(struct rte_bbdev_enc_op *op __rte_unused) +{ + struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc; + struct rte_bbdev_op_enc_ldpc_cb_params *cb = NULL; + struct rte_bbdev_op_enc_ldpc_tb_params *tb = NULL; + + + if (ldpc_enc->input.length > + RTE_BBDEV_LDPC_MAX_CB_SIZE >> 3) { + rte_bbdev_log(ERR, "CB size (%u) is too big, max: %d", + ldpc_enc->input.length, + RTE_BBDEV_LDPC_MAX_CB_SIZE); + return -1; + } + + if (op->mempool == NULL) { + rte_bbdev_log(ERR, "Invalid mempool pointer"); + return -1; + } + if (ldpc_enc->input.data == NULL) { + rte_bbdev_log(ERR, "Invalid input pointer"); + return -1; + } + if (ldpc_enc->output.data == NULL) { + rte_bbdev_log(ERR, "Invalid output pointer"); + return -1; + } + if ((ldpc_enc->basegraph > 2) || (ldpc_enc->basegraph == 0)) { + rte_bbdev_log(ERR, + "basegraph (%u) is out of range 1 <= value <= 2", + ldpc_enc->basegraph); + return -1; + } + if (ldpc_enc->code_block_mode > 1) { + rte_bbdev_log(ERR, + "code_block_mode (%u) is out of range 0:Tb 1:CB", + ldpc_enc->code_block_mode); + return -1; + } + + if (ldpc_enc->code_block_mode == 0) { + tb = &ldpc_enc->tb_params; + if (tb->c == 0) { + rte_bbdev_log(ERR, + "c (%u) is out of range 1 <= value <= %u", + tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS); + return -1; + } + if (tb->cab > tb->c) { + rte_bbdev_log(ERR, + "cab (%u) is greater than c (%u)", + tb->cab, tb->c); + return -1; + } + if ((tb->ea < RTE_BBDEV_LDPC_MIN_CB_SIZE) + && tb->r < tb->cab) { + rte_bbdev_log(ERR, + "ea (%u) is less than %u or it is not even", + tb->ea, RTE_BBDEV_LDPC_MIN_CB_SIZE); + return -1; + } + if ((tb->eb < RTE_BBDEV_LDPC_MIN_CB_SIZE) + && tb->c > tb->cab) { + rte_bbdev_log(ERR, + "eb (%u) is less than %u", + tb->eb, RTE_BBDEV_LDPC_MIN_CB_SIZE); + return -1; + } + if (tb->r > (tb->c - 1)) { + rte_bbdev_log(ERR, + "r (%u) is greater than c - 1 (%u)", + tb->r, tb->c - 1); + return -1; + } + } else { + cb = &ldpc_enc->cb_params; + if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) { + rte_bbdev_log(ERR, + "e (%u) is less than %u or it is not even", + cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE); + return -1; + } + } + return 0; +} +#endif + static inline char * mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len) { @@ -692,6 +1134,203 @@ mbuf_append(struct rte_mbuf *m_head, struct rte_mbuf *m, uint16_t len) return tail; } +#ifdef RTE_LIBRTE_BBDEV_DEBUG +/* Validates LDPC decoder parameters */ +static int +validate_dec_op(struct rte_bbdev_dec_op *op __rte_unused) +{ + struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec; + struct rte_bbdev_op_dec_ldpc_cb_params *cb = NULL; + struct rte_bbdev_op_dec_ldpc_tb_params *tb = NULL; + + if (op->mempool == NULL) { + rte_bbdev_log(ERR, "Invalid mempool pointer"); + return -1; + } + if (ldpc_dec->rv_index > 3) { + rte_bbdev_log(ERR, + "rv_index (%u) is out of range 0 <= value <= 3", + ldpc_dec->rv_index); + return -1; + } + + if (ldpc_dec->iter_max == 0) { + rte_bbdev_log(ERR, + "iter_max (%u) is equal to 0", + ldpc_dec->iter_max); + return -1; + } + + if (ldpc_dec->code_block_mode > 1) { + rte_bbdev_log(ERR, + "code_block_mode (%u) is out of range 0 <= value <= 1", + ldpc_dec->code_block_mode); + return -1; + } + + if (ldpc_dec->code_block_mode == 0) { + tb = &ldpc_dec->tb_params; + if (tb->c < 1) { + rte_bbdev_log(ERR, + "c (%u) is out of range 1 <= value <= %u", + tb->c, RTE_BBDEV_LDPC_MAX_CODE_BLOCKS); + return -1; + } + if (tb->cab > tb->c) { + rte_bbdev_log(ERR, + "cab (%u) is greater than c (%u)", + tb->cab, tb->c); + return -1; + } + } else { + cb = &ldpc_dec->cb_params; + if (cb->e < RTE_BBDEV_LDPC_MIN_CB_SIZE) { + rte_bbdev_log(ERR, + "e (%u) is out of range %u <= value <= %u", + cb->e, RTE_BBDEV_LDPC_MIN_CB_SIZE, + RTE_BBDEV_LDPC_MAX_CB_SIZE); + return -1; + } + } + + return 0; +} +#endif + +static inline int +fpga_harq_write_loopback(struct fpga_5gnr_fec_device *fpga_dev, + struct rte_mbuf *harq_input, uint16_t harq_in_length, + uint32_t harq_in_offset, uint32_t harq_out_offset) +{ + uint32_t out_offset = harq_out_offset; + uint32_t in_offset = harq_in_offset; + uint32_t left_length = harq_in_length; + uint32_t reg_32, increment = 0; + uint64_t *input = NULL; + uint32_t last_transaction = left_length + % FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + uint64_t last_word; + + if (last_transaction > 0) + left_length -= last_transaction; + + /* + * Get HARQ buffer size for each VF/PF: When 0x00, there is no + * available DDR space for the corresponding VF/PF. + */ + reg_32 = fpga_reg_read_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); + if (reg_32 < harq_in_length) { + left_length = reg_32; + rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n"); + } + + input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_input, + uint8_t *, in_offset); + + while (left_length > 0) { + if (fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) { + fpga_reg_write_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS, + out_offset); + fpga_reg_write_64(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS, + input[increment]); + left_length -= FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + out_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + increment++; + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1); + } + } + while (last_transaction > 0) { + if (fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS) == 1) { + fpga_reg_write_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS, + out_offset); + last_word = input[increment]; + last_word &= (uint64_t)(1 << (last_transaction * 4)) + - 1; + fpga_reg_write_64(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS, + last_word); + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS, 1); + last_transaction = 0; + } + } + return 1; +} + +static inline int +fpga_harq_read_loopback(struct fpga_5gnr_fec_device *fpga_dev, + struct rte_mbuf *harq_output, uint16_t harq_in_length, + uint32_t harq_in_offset, uint32_t harq_out_offset) +{ + uint32_t left_length, in_offset = harq_in_offset; + uint64_t reg; + uint32_t increment = 0; + uint64_t *input = NULL; + uint32_t last_transaction = harq_in_length + % FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + + if (last_transaction > 0) + harq_in_length += (8 - last_transaction); + + reg = fpga_reg_read_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS); + if (reg < harq_in_length) { + harq_in_length = reg; + rte_bbdev_log(ERR, "HARQ in length > HARQ buffer size\n"); + } + + if (!mbuf_append(harq_output, harq_output, harq_in_length)) { + rte_bbdev_log(ERR, "HARQ output buffer warning %d %d\n", + harq_output->buf_len - + rte_pktmbuf_headroom(harq_output), + harq_in_length); + harq_in_length = harq_output->buf_len - + rte_pktmbuf_headroom(harq_output); + if (!mbuf_append(harq_output, harq_output, harq_in_length)) { + rte_bbdev_log(ERR, "HARQ output buffer issue %d %d\n", + harq_output->buf_len, harq_in_length); + return -1; + } + } + left_length = harq_in_length; + + input = (uint64_t *)rte_pktmbuf_mtod_offset(harq_output, + uint8_t *, harq_out_offset); + + while (left_length > 0) { + fpga_reg_write_32(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS, in_offset); + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 1); + reg = fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS); + while (reg != 1) { + reg = fpga_reg_read_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS); + if (reg == FPGA_DDR_OVERFLOW) { + rte_bbdev_log(ERR, + "Read address is overflow!\n"); + return -1; + } + } + input[increment] = fpga_reg_read_64(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_DATA_REGS); + left_length -= FPGA_5GNR_FEC_DDR_RD_DATA_LEN_IN_BYTES; + in_offset += FPGA_5GNR_FEC_DDR_WR_DATA_LEN_IN_BYTES; + increment++; + fpga_reg_write_8(fpga_dev->mmio_base, + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS, 0); + } + return 1; +} + static inline int enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_offset) @@ -710,6 +1349,15 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op, uint16_t ring_offset; uint16_t K, k_; +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Validate op structure */ + /* FIXME */ + if (validate_enc_op(op) == -1) { + rte_bbdev_log(ERR, "LDPC encoder validation failed"); + return -EINVAL; + } +#endif + /* Clear op status */ op->status = 0; @@ -771,6 +1419,9 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_queue *q, struct rte_bbdev_enc_op *op, return -1; } +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_dma_enc_desc_debug_info(desc); +#endif return 1; } @@ -793,6 +1444,14 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op, uint16_t out_offset = dec->hard_output.offset; uint32_t harq_offset = 0; +#ifdef RTE_LIBRTE_BBDEV_DEBUG + /* Validate op structure */ + if (validate_dec_op(op) == -1) { + rte_bbdev_log(ERR, "LDPC decoder validation failed"); + return -EINVAL; + } +#endif + /* Clear op status */ op->status = 0; @@ -800,6 +1459,42 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op, ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); desc = q->ring_addr + ring_offset; + if (check_bit(dec->op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) { + struct rte_mbuf *harq_in = dec->harq_combined_input.data; + struct rte_mbuf *harq_out = dec->harq_combined_output.data; + harq_in_length = dec->harq_combined_input.length; + uint32_t harq_in_offset = dec->harq_combined_input.offset; + uint32_t harq_out_offset = dec->harq_combined_output.offset; + + if (check_bit(dec->op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE + )) { + ret = fpga_harq_write_loopback(q->d, harq_in, + harq_in_length, harq_in_offset, + harq_out_offset); + } else if (check_bit(dec->op_flags, + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE + )) { + ret = fpga_harq_read_loopback(q->d, harq_out, + harq_in_length, harq_in_offset, + harq_out_offset); + dec->harq_combined_output.length = harq_in_length; + } else { + rte_bbdev_log(ERR, "OP flag Err!"); + ret = -1; + } + /* Set descriptor for dequeue */ + desc->dec_req.done = 1; + desc->dec_req.error = 0; + desc->dec_req.op_addr = op; + desc->dec_req.cbs_in_op = 1; + /* Mark this dummy descriptor to be dropped by HW */ + desc->dec_req.desc_idx = (ring_offset + 1) + & q->sw_ring_wrap_mask; + return ret; /* Error or number of CB */ + } + if (m_in == NULL || m_out == NULL) { rte_bbdev_log(ERR, "Invalid mbuf pointer"); op->status = 1 << RTE_BBDEV_DATA_ERROR; @@ -864,6 +1559,10 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op *op, return -1; } +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_dma_dec_desc_debug_info(desc); +#endif + return 1; } @@ -982,11 +1681,11 @@ fpga_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, static inline int dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, - struct rte_bbdev_enc_op **op __rte_unused, + struct rte_bbdev_enc_op **op, uint16_t desc_offset) { union fpga_dma_desc *desc; - + int desc_error; /* Set current desc */ desc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); @@ -1000,6 +1699,15 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_queue *q, rte_bbdev_log_debug("DMA response desc %p", desc); +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_dma_enc_desc_debug_info(desc); +#endif + + *op = desc->enc_req.op_addr; + /* Check the descriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->enc_req.error); + (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR; + return 1; } @@ -1009,7 +1717,7 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op, uint16_t desc_offset) { union fpga_dma_desc *desc; - + int desc_error; /* Set descriptor */ desc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); @@ -1021,6 +1729,10 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op, /* make sure the response is read atomically */ rte_smp_rmb(); +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_dma_dec_desc_debug_info(desc); +#endif + *op = desc->dec_req.op_addr; if (check_bit((*op)->ldpc_dec.op_flags, @@ -1036,6 +1748,9 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_queue *q, struct rte_bbdev_dec_op **op, (*op)->status = 1 << RTE_BBDEV_CRC_ERROR; /* et_pass = 0 when decoder fails */ (*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR; + /* Check the descriptor error field, return 1 on error */ + desc_error = check_desc_error(desc->dec_req.error); + (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR; return 1; } @@ -1173,6 +1888,17 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv, rte_bbdev_log_debug("bbdev id = %u [%s]", bbdev->data->dev_id, dev_name); + struct fpga_5gnr_fec_device *d = bbdev->data->dev_private; + uint32_t version_id = fpga_reg_read_32(d->mmio_base, + FPGA_5GNR_FEC_VERSION_ID); + rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u", + ((uint16_t)(version_id >> 16)), ((uint16_t)version_id)); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + if (!strcmp(bbdev->device->driver->name, + RTE_STR(FPGA_5GNR_FEC_PF_DRIVER_NAME))) + print_static_reg_debug_info(d->mmio_base); +#endif return 0; } @@ -1217,6 +1943,201 @@ fpga_5gnr_fec_remove(struct rte_pci_device *pci_dev) return 0; } +static inline void +set_default_fpga_conf(struct fpga_5gnr_fec_conf *def_conf) +{ + /* clear default configuration before initialization */ + memset(def_conf, 0, sizeof(struct fpga_5gnr_fec_conf)); + /* Set pf mode to true */ + def_conf->pf_mode_en = true; + + /* Set ratio between UL and DL to 1:1 (unit of weight is 3 CBs) */ + def_conf->ul_bandwidth = 3; + def_conf->dl_bandwidth = 3; + + /* Set Load Balance Factor to 64 */ + def_conf->dl_load_balance = 64; + def_conf->ul_load_balance = 64; +} + +/* Initial configuration of FPGA 5GNR FEC device */ +int +fpga_5gnr_fec_configure(const char *dev_name, + const struct fpga_5gnr_fec_conf *conf) +{ + uint32_t payload_32, address; + uint16_t payload_16; + uint8_t payload_8; + uint16_t q_id, vf_id, total_q_id, total_ul_q_id, total_dl_q_id; + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + struct fpga_5gnr_fec_conf def_conf; + + if (bbdev == NULL) { + rte_bbdev_log(ERR, + "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + + struct fpga_5gnr_fec_device *d = bbdev->data->dev_private; + + if (conf == NULL) { + rte_bbdev_log(ERR, + "FPGA Configuration was not provided. Default configuration will be loaded."); + set_default_fpga_conf(&def_conf); + conf = &def_conf; + } + + /* + * Configure UL:DL ratio. + * [7:0]: UL weight + * [15:8]: DL weight + */ + payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth; + address = FPGA_5GNR_FEC_CONFIGURATION; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Clear all queues registers */ + payload_32 = FPGA_INVALID_HW_QUEUE_ID; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP; + fpga_reg_write_32(d->mmio_base, address, payload_32); + } + + /* + * If PF mode is enabled allocate all queues for PF only. + * + * For VF mode each VF can have different number of UL and DL queues. + * Total number of queues to configure cannot exceed FPGA + * capabilities - 64 queues - 32 queues for UL and 32 queues for DL. + * Queues mapping is done according to configuration: + * + * UL queues: + * | Q_ID | VF_ID | + * | 0 | 0 | + * | ... | 0 | + * | conf->vf_dl_queues_number[0] - 1 | 0 | + * | conf->vf_dl_queues_number[0] | 1 | + * | ... | 1 | + * | conf->vf_dl_queues_number[1] - 1 | 1 | + * | ... | ... | + * | conf->vf_dl_queues_number[7] - 1 | 7 | + * + * DL queues: + * | Q_ID | VF_ID | + * | 32 | 0 | + * | ... | 0 | + * | conf->vf_ul_queues_number[0] - 1 | 0 | + * | conf->vf_ul_queues_number[0] | 1 | + * | ... | 1 | + * | conf->vf_ul_queues_number[1] - 1 | 1 | + * | ... | ... | + * | conf->vf_ul_queues_number[7] - 1 | 7 | + * + * Example of configuration: + * conf->vf_ul_queues_number[0] = 4; -> 4 UL queues for VF0 + * conf->vf_dl_queues_number[0] = 4; -> 4 DL queues for VF0 + * conf->vf_ul_queues_number[1] = 2; -> 2 UL queues for VF1 + * conf->vf_dl_queues_number[1] = 2; -> 2 DL queues for VF1 + * + * UL: + * | Q_ID | VF_ID | + * | 0 | 0 | + * | 1 | 0 | + * | 2 | 0 | + * | 3 | 0 | + * | 4 | 1 | + * | 5 | 1 | + * + * DL: + * | Q_ID | VF_ID | + * | 32 | 0 | + * | 33 | 0 | + * | 34 | 0 | + * | 35 | 0 | + * | 36 | 1 | + * | 37 | 1 | + */ + if (conf->pf_mode_en) { + payload_32 = 0x1; + for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP; + fpga_reg_write_32(d->mmio_base, address, payload_32); + } + } else { + /* Calculate total number of UL and DL queues to configure */ + total_ul_q_id = total_dl_q_id = 0; + for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { + total_ul_q_id += conf->vf_ul_queues_number[vf_id]; + total_dl_q_id += conf->vf_dl_queues_number[vf_id]; + } + total_q_id = total_dl_q_id + total_ul_q_id; + /* + * Check if total number of queues to configure does not exceed + * FPGA capabilities (64 queues - 32 UL and 32 DL queues) + */ + if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) || + (total_dl_q_id > FPGA_NUM_DL_QUEUES) || + (total_q_id > FPGA_TOTAL_NUM_QUEUES)) { + rte_bbdev_log(ERR, + "FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u", + total_ul_q_id, total_dl_q_id, + FPGA_TOTAL_NUM_QUEUES); + return -EINVAL; + } + total_ul_q_id = 0; + for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { + for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id]; + ++q_id, ++total_ul_q_id) { + address = (total_ul_q_id << 2) + + FPGA_5GNR_FEC_QUEUE_MAP; + payload_32 = ((0x80 + vf_id) << 16) | 0x1; + fpga_reg_write_32(d->mmio_base, address, + payload_32); + } + } + total_dl_q_id = 0; + for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { + for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id]; + ++q_id, ++total_dl_q_id) { + address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES) + << 2) + FPGA_5GNR_FEC_QUEUE_MAP; + payload_32 = ((0x80 + vf_id) << 16) | 0x1; + fpga_reg_write_32(d->mmio_base, address, + payload_32); + } + } + } + + /* Setting Load Balance Factor */ + payload_16 = (conf->dl_load_balance << 8) | (conf->ul_load_balance); + address = FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Setting length of ring descriptor entry */ + payload_16 = FPGA_RING_DESC_ENTRY_LENGTH; + address = FPGA_5GNR_FEC_RING_DESC_LEN; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Setting FLR timeout value */ + payload_16 = conf->flr_time_out; + address = FPGA_5GNR_FEC_FLR_TIME_OUT; + fpga_reg_write_16(d->mmio_base, address, payload_16); + + /* Queue PF/VF mapping table is ready */ + payload_8 = 0x1; + address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE; + fpga_reg_write_8(d->mmio_base, address, payload_8); + + rte_bbdev_log_debug("PF FPGA 5GNR FEC configuration complete for %s", + dev_name); + +#ifdef RTE_LIBRTE_BBDEV_DEBUG + print_static_reg_debug_info(d->mmio_base); +#endif + return 0; +} + /* FPGA 5GNR FEC PCI PF address map */ static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = { { @@ -1256,14 +2177,3 @@ RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_PF_DRIVER_NAME, RTE_PMD_REGISTER_PCI(FPGA_5GNR_FEC_VF_DRIVER_NAME, fpga_5gnr_fec_pci_vf_driver); RTE_PMD_REGISTER_PCI_TABLE(FPGA_5GNR_FEC_VF_DRIVER_NAME, pci_id_fpga_5gnr_fec_vf_map); - -RTE_INIT(fpga_5gnr_fec_init_log) -{ - fpga_5gnr_fec_logtype = rte_log_register("pmd.bb.fpga_5gnr_fec"); - if (fpga_5gnr_fec_logtype >= 0) -#ifdef RTE_LIBRTE_BBDEV_DEBUG - rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_DEBUG); -#else - rte_log_set_level(fpga_5gnr_fec_logtype, RTE_LOG_NOTICE); -#endif -}